1 From cec5fc1572ae50252a492ceeabe1b896f8d521b2 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Thu, 21 Apr 2022 16:29:43 +0200
4 Subject: [PATCH] drm/vc4: Warn if some v3d code is run on BCM2711
6 The BCM2711 has a separate driver for the v3d, and thus we can't call
7 into any of the driver entrypoints that rely on the v3d being there.
9 Let's add a bunch of checks and complain loudly if that ever happen.
11 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
13 drivers/gpu/drm/vc4/vc4_bo.c | 49 ++++++++++++++++++++++
14 drivers/gpu/drm/vc4/vc4_drv.c | 11 +++++
15 drivers/gpu/drm/vc4/vc4_drv.h | 6 +++
16 drivers/gpu/drm/vc4/vc4_gem.c | 40 ++++++++++++++++++
17 drivers/gpu/drm/vc4/vc4_irq.c | 16 +++++++
18 drivers/gpu/drm/vc4/vc4_kms.c | 4 ++
19 drivers/gpu/drm/vc4/vc4_perfmon.c | 47 ++++++++++++++++++++-
20 drivers/gpu/drm/vc4/vc4_render_cl.c | 4 ++
21 drivers/gpu/drm/vc4/vc4_v3d.c | 15 +++++++
22 drivers/gpu/drm/vc4/vc4_validate.c | 16 +++++++
23 drivers/gpu/drm/vc4/vc4_validate_shaders.c | 4 ++
24 11 files changed, 211 insertions(+), 1 deletion(-)
26 --- a/drivers/gpu/drm/vc4/vc4_bo.c
27 +++ b/drivers/gpu/drm/vc4/vc4_bo.c
28 @@ -248,6 +248,9 @@ void vc4_bo_add_to_purgeable_pool(struct
30 struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
32 + if (WARN_ON_ONCE(vc4->is_vc5))
35 mutex_lock(&vc4->purgeable.lock);
36 list_add_tail(&bo->size_head, &vc4->purgeable.list);
38 @@ -259,6 +262,9 @@ static void vc4_bo_remove_from_purgeable
40 struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
42 + if (WARN_ON_ONCE(vc4->is_vc5))
45 /* list_del_init() is used here because the caller might release
46 * the purgeable lock in order to acquire the madv one and update the
48 @@ -389,6 +395,9 @@ struct drm_gem_object *vc4_create_object
49 struct vc4_dev *vc4 = to_vc4_dev(dev);
52 + if (WARN_ON_ONCE(vc4->is_vc5))
53 + return ERR_PTR(-ENODEV);
55 bo = kzalloc(sizeof(*bo), GFP_KERNEL);
58 @@ -415,6 +424,9 @@ struct vc4_bo *vc4_bo_create(struct drm_
59 struct drm_gem_cma_object *cma_obj;
62 + if (WARN_ON_ONCE(vc4->is_vc5))
63 + return ERR_PTR(-ENODEV);
66 return ERR_PTR(-EINVAL);
68 @@ -477,9 +489,13 @@ int vc4_bo_dumb_create(struct drm_file *
69 struct drm_device *dev,
70 struct drm_mode_create_dumb *args)
72 + struct vc4_dev *vc4 = to_vc4_dev(dev);
73 struct vc4_bo *bo = NULL;
76 + if (WARN_ON_ONCE(vc4->is_vc5))
79 ret = vc4_dumb_fixup_args(args);
82 @@ -600,8 +616,12 @@ static void vc4_bo_cache_time_work(struc
84 int vc4_bo_inc_usecnt(struct vc4_bo *bo)
86 + struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
89 + if (WARN_ON_ONCE(vc4->is_vc5))
92 /* Fast path: if the BO is already retained by someone, no need to
93 * check the madv status.
95 @@ -636,6 +656,11 @@ int vc4_bo_inc_usecnt(struct vc4_bo *bo)
97 void vc4_bo_dec_usecnt(struct vc4_bo *bo)
99 + struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
101 + if (WARN_ON_ONCE(vc4->is_vc5))
104 /* Fast path: if the BO is still retained by someone, no need to test
107 @@ -761,6 +786,9 @@ int vc4_create_bo_ioctl(struct drm_devic
108 struct vc4_bo *bo = NULL;
111 + if (WARN_ON_ONCE(vc4->is_vc5))
114 ret = vc4_grab_bin_bo(vc4, vc4file);
117 @@ -784,9 +812,13 @@ int vc4_create_bo_ioctl(struct drm_devic
118 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data,
119 struct drm_file *file_priv)
121 + struct vc4_dev *vc4 = to_vc4_dev(dev);
122 struct drm_vc4_mmap_bo *args = data;
123 struct drm_gem_object *gem_obj;
125 + if (WARN_ON_ONCE(vc4->is_vc5))
128 gem_obj = drm_gem_object_lookup(file_priv, args->handle);
130 DRM_DEBUG("Failed to look up GEM BO %d\n", args->handle);
131 @@ -810,6 +842,9 @@ vc4_create_shader_bo_ioctl(struct drm_de
132 struct vc4_bo *bo = NULL;
135 + if (WARN_ON_ONCE(vc4->is_vc5))
141 @@ -880,11 +915,15 @@ fail:
142 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data,
143 struct drm_file *file_priv)
145 + struct vc4_dev *vc4 = to_vc4_dev(dev);
146 struct drm_vc4_set_tiling *args = data;
147 struct drm_gem_object *gem_obj;
151 + if (WARN_ON_ONCE(vc4->is_vc5))
154 if (args->flags != 0)
157 @@ -923,10 +962,14 @@ int vc4_set_tiling_ioctl(struct drm_devi
158 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data,
159 struct drm_file *file_priv)
161 + struct vc4_dev *vc4 = to_vc4_dev(dev);
162 struct drm_vc4_get_tiling *args = data;
163 struct drm_gem_object *gem_obj;
166 + if (WARN_ON_ONCE(vc4->is_vc5))
169 if (args->flags != 0 || args->modifier != 0)
172 @@ -953,6 +996,9 @@ int vc4_bo_cache_init(struct drm_device
173 struct vc4_dev *vc4 = to_vc4_dev(dev);
176 + if (WARN_ON_ONCE(vc4->is_vc5))
179 /* Create the initial set of BO labels that the kernel will
180 * use. This lets us avoid a bunch of string reallocation in
181 * the kernel's draw and BO allocation paths.
182 @@ -1012,6 +1058,9 @@ int vc4_label_bo_ioctl(struct drm_device
183 struct drm_gem_object *gem_obj;
186 + if (WARN_ON_ONCE(vc4->is_vc5))
192 --- a/drivers/gpu/drm/vc4/vc4_drv.c
193 +++ b/drivers/gpu/drm/vc4/vc4_drv.c
194 @@ -101,6 +101,9 @@ static int vc4_get_param_ioctl(struct dr
198 + if (WARN_ON_ONCE(vc4->is_vc5))
204 @@ -144,11 +147,16 @@ static int vc4_get_param_ioctl(struct dr
206 static int vc4_open(struct drm_device *dev, struct drm_file *file)
208 + struct vc4_dev *vc4 = to_vc4_dev(dev);
209 struct vc4_file *vc4file;
211 + if (WARN_ON_ONCE(vc4->is_vc5))
214 vc4file = kzalloc(sizeof(*vc4file), GFP_KERNEL);
217 + vc4file->dev = vc4;
219 vc4_perfmon_open_file(vc4file);
220 file->driver_priv = vc4file;
221 @@ -160,6 +168,9 @@ static void vc4_close(struct drm_device
222 struct vc4_dev *vc4 = to_vc4_dev(dev);
223 struct vc4_file *vc4file = file->driver_priv;
225 + if (WARN_ON_ONCE(vc4->is_vc5))
228 if (vc4file->bin_bo_used)
229 vc4_v3d_bin_bo_put(vc4);
231 --- a/drivers/gpu/drm/vc4/vc4_drv.h
232 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
233 @@ -49,6 +49,8 @@ enum vc4_kernel_bo_type {
234 * done. This way, only events related to a specific job will be counted.
237 + struct vc4_dev *dev;
239 /* Tracks the number of users of the perfmon, when this counter reaches
240 * zero the perfmon is destroyed.
242 @@ -612,6 +614,8 @@ to_vc4_crtc_state(struct drm_crtc_state
243 #define VC4_REG32(reg) { .name = #reg, .offset = reg }
245 struct vc4_exec_info {
246 + struct vc4_dev *dev;
248 /* Sequence number for this bin/render job. */
251 @@ -733,6 +737,8 @@ struct vc4_exec_info {
252 * released when the DRM file is closed should be placed here.
255 + struct vc4_dev *dev;
260 --- a/drivers/gpu/drm/vc4/vc4_gem.c
261 +++ b/drivers/gpu/drm/vc4/vc4_gem.c
262 @@ -76,6 +76,9 @@ vc4_get_hang_state_ioctl(struct drm_devi
266 + if (WARN_ON_ONCE(vc4->is_vc5))
270 DRM_DEBUG("VC4_GET_HANG_STATE with no VC4 V3D probed\n");
272 @@ -386,6 +389,9 @@ vc4_wait_for_seqno(struct drm_device *de
273 unsigned long timeout_expire;
276 + if (WARN_ON_ONCE(vc4->is_vc5))
279 if (vc4->finished_seqno >= seqno)
282 @@ -468,6 +474,9 @@ vc4_submit_next_bin_job(struct drm_devic
283 struct vc4_dev *vc4 = to_vc4_dev(dev);
284 struct vc4_exec_info *exec;
286 + if (WARN_ON_ONCE(vc4->is_vc5))
290 exec = vc4_first_bin_job(vc4);
292 @@ -511,6 +520,9 @@ vc4_submit_next_render_job(struct drm_de
296 + if (WARN_ON_ONCE(vc4->is_vc5))
299 /* A previous RCL may have written to one of our textures, and
300 * our full cache flush at bin time may have occurred before
301 * that RCL completed. Flush the texture cache now, but not
302 @@ -528,6 +540,9 @@ vc4_move_job_to_render(struct drm_device
303 struct vc4_dev *vc4 = to_vc4_dev(dev);
304 bool was_empty = list_empty(&vc4->render_job_list);
306 + if (WARN_ON_ONCE(vc4->is_vc5))
309 list_move_tail(&exec->head, &vc4->render_job_list);
311 vc4_submit_next_render_job(dev);
312 @@ -992,6 +1007,9 @@ vc4_job_handle_completed(struct vc4_dev
313 unsigned long irqflags;
314 struct vc4_seqno_cb *cb, *cb_temp;
316 + if (WARN_ON_ONCE(vc4->is_vc5))
319 spin_lock_irqsave(&vc4->job_lock, irqflags);
320 while (!list_empty(&vc4->job_done_list)) {
321 struct vc4_exec_info *exec =
322 @@ -1028,6 +1046,9 @@ int vc4_queue_seqno_cb(struct drm_device
323 struct vc4_dev *vc4 = to_vc4_dev(dev);
324 unsigned long irqflags;
326 + if (WARN_ON_ONCE(vc4->is_vc5))
330 INIT_WORK(&cb->work, vc4_seqno_cb_work);
332 @@ -1078,8 +1099,12 @@ int
333 vc4_wait_seqno_ioctl(struct drm_device *dev, void *data,
334 struct drm_file *file_priv)
336 + struct vc4_dev *vc4 = to_vc4_dev(dev);
337 struct drm_vc4_wait_seqno *args = data;
339 + if (WARN_ON_ONCE(vc4->is_vc5))
342 return vc4_wait_for_seqno_ioctl_helper(dev, args->seqno,
345 @@ -1088,11 +1113,15 @@ int
346 vc4_wait_bo_ioctl(struct drm_device *dev, void *data,
347 struct drm_file *file_priv)
349 + struct vc4_dev *vc4 = to_vc4_dev(dev);
351 struct drm_vc4_wait_bo *args = data;
352 struct drm_gem_object *gem_obj;
355 + if (WARN_ON_ONCE(vc4->is_vc5))
361 @@ -1135,6 +1164,9 @@ vc4_submit_cl_ioctl(struct drm_device *d
362 struct dma_fence *in_fence;
365 + if (WARN_ON_ONCE(vc4->is_vc5))
369 DRM_DEBUG("VC4_SUBMIT_CL with no VC4 V3D probed\n");
371 @@ -1158,6 +1190,7 @@ vc4_submit_cl_ioctl(struct drm_device *d
372 DRM_ERROR("malloc failure on exec struct\n");
377 ret = vc4_v3d_pm_get(vc4);
379 @@ -1267,6 +1300,9 @@ int vc4_gem_init(struct drm_device *dev)
381 struct vc4_dev *vc4 = to_vc4_dev(dev);
383 + if (WARN_ON_ONCE(vc4->is_vc5))
386 vc4->dma_fence_context = dma_fence_context_alloc(1);
388 INIT_LIST_HEAD(&vc4->bin_job_list);
389 @@ -1312,11 +1348,15 @@ static void vc4_gem_destroy(struct drm_d
390 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data,
391 struct drm_file *file_priv)
393 + struct vc4_dev *vc4 = to_vc4_dev(dev);
394 struct drm_vc4_gem_madvise *args = data;
395 struct drm_gem_object *gem_obj;
399 + if (WARN_ON_ONCE(vc4->is_vc5))
402 switch (args->madv) {
403 case VC4_MADV_DONTNEED:
404 case VC4_MADV_WILLNEED:
405 --- a/drivers/gpu/drm/vc4/vc4_irq.c
406 +++ b/drivers/gpu/drm/vc4/vc4_irq.c
407 @@ -260,6 +260,9 @@ vc4_irq_enable(struct drm_device *dev)
409 struct vc4_dev *vc4 = to_vc4_dev(dev);
411 + if (WARN_ON_ONCE(vc4->is_vc5))
417 @@ -274,6 +277,9 @@ vc4_irq_disable(struct drm_device *dev)
419 struct vc4_dev *vc4 = to_vc4_dev(dev);
421 + if (WARN_ON_ONCE(vc4->is_vc5))
427 @@ -291,8 +297,12 @@ vc4_irq_disable(struct drm_device *dev)
429 int vc4_irq_install(struct drm_device *dev, int irq)
431 + struct vc4_dev *vc4 = to_vc4_dev(dev);
434 + if (WARN_ON_ONCE(vc4->is_vc5))
437 if (irq == IRQ_NOTCONNECTED)
440 @@ -311,6 +321,9 @@ void vc4_irq_uninstall(struct drm_device
442 struct vc4_dev *vc4 = to_vc4_dev(dev);
444 + if (WARN_ON_ONCE(vc4->is_vc5))
447 vc4_irq_disable(dev);
448 free_irq(vc4->irq, dev);
450 @@ -321,6 +334,9 @@ void vc4_irq_reset(struct drm_device *de
451 struct vc4_dev *vc4 = to_vc4_dev(dev);
452 unsigned long irqflags;
454 + if (WARN_ON_ONCE(vc4->is_vc5))
457 /* Acknowledge any stale IRQs. */
458 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS);
460 --- a/drivers/gpu/drm/vc4/vc4_kms.c
461 +++ b/drivers/gpu/drm/vc4/vc4_kms.c
462 @@ -485,8 +485,12 @@ static struct drm_framebuffer *vc4_fb_cr
463 struct drm_file *file_priv,
464 const struct drm_mode_fb_cmd2 *mode_cmd)
466 + struct vc4_dev *vc4 = to_vc4_dev(dev);
467 struct drm_mode_fb_cmd2 mode_cmd_local;
469 + if (WARN_ON_ONCE(vc4->is_vc5))
470 + return ERR_PTR(-ENODEV);
472 /* If the user didn't specify a modifier, use the
473 * vc4_set_tiling_ioctl() state for the BO.
475 --- a/drivers/gpu/drm/vc4/vc4_perfmon.c
476 +++ b/drivers/gpu/drm/vc4/vc4_perfmon.c
479 void vc4_perfmon_get(struct vc4_perfmon *perfmon)
481 + struct vc4_dev *vc4 = perfmon->dev;
483 + if (WARN_ON_ONCE(vc4->is_vc5))
487 refcount_inc(&perfmon->refcnt);
490 void vc4_perfmon_put(struct vc4_perfmon *perfmon)
492 - if (perfmon && refcount_dec_and_test(&perfmon->refcnt))
493 + struct vc4_dev *vc4;
498 + vc4 = perfmon->dev;
499 + if (WARN_ON_ONCE(vc4->is_vc5))
502 + if (refcount_dec_and_test(&perfmon->refcnt))
506 @@ -32,6 +46,9 @@ void vc4_perfmon_start(struct vc4_dev *v
510 + if (WARN_ON_ONCE(vc4->is_vc5))
513 if (WARN_ON_ONCE(!perfmon || vc4->active_perfmon))
516 @@ -49,6 +66,9 @@ void vc4_perfmon_stop(struct vc4_dev *vc
520 + if (WARN_ON_ONCE(vc4->is_vc5))
523 if (WARN_ON_ONCE(!vc4->active_perfmon ||
524 perfmon != vc4->active_perfmon))
526 @@ -64,8 +84,12 @@ void vc4_perfmon_stop(struct vc4_dev *vc
528 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id)
530 + struct vc4_dev *vc4 = vc4file->dev;
531 struct vc4_perfmon *perfmon;
533 + if (WARN_ON_ONCE(vc4->is_vc5))
536 mutex_lock(&vc4file->perfmon.lock);
537 perfmon = idr_find(&vc4file->perfmon.idr, id);
538 vc4_perfmon_get(perfmon);
539 @@ -76,8 +100,14 @@ struct vc4_perfmon *vc4_perfmon_find(str
541 void vc4_perfmon_open_file(struct vc4_file *vc4file)
543 + struct vc4_dev *vc4 = vc4file->dev;
545 + if (WARN_ON_ONCE(vc4->is_vc5))
548 mutex_init(&vc4file->perfmon.lock);
549 idr_init_base(&vc4file->perfmon.idr, VC4_PERFMONID_MIN);
550 + vc4file->dev = vc4;
553 static int vc4_perfmon_idr_del(int id, void *elem, void *data)
554 @@ -91,6 +121,11 @@ static int vc4_perfmon_idr_del(int id, v
556 void vc4_perfmon_close_file(struct vc4_file *vc4file)
558 + struct vc4_dev *vc4 = vc4file->dev;
560 + if (WARN_ON_ONCE(vc4->is_vc5))
563 mutex_lock(&vc4file->perfmon.lock);
564 idr_for_each(&vc4file->perfmon.idr, vc4_perfmon_idr_del, NULL);
565 idr_destroy(&vc4file->perfmon.idr);
566 @@ -107,6 +142,9 @@ int vc4_perfmon_create_ioctl(struct drm_
570 + if (WARN_ON_ONCE(vc4->is_vc5))
574 DRM_DEBUG("Creating perfmon no VC4 V3D probed\n");
576 @@ -127,6 +165,7 @@ int vc4_perfmon_create_ioctl(struct drm_
580 + perfmon->dev = vc4;
582 for (i = 0; i < req->ncounters; i++)
583 perfmon->events[i] = req->events[i];
584 @@ -157,6 +196,9 @@ int vc4_perfmon_destroy_ioctl(struct drm
585 struct drm_vc4_perfmon_destroy *req = data;
586 struct vc4_perfmon *perfmon;
588 + if (WARN_ON_ONCE(vc4->is_vc5))
592 DRM_DEBUG("Destroying perfmon no VC4 V3D probed\n");
594 @@ -182,6 +224,9 @@ int vc4_perfmon_get_values_ioctl(struct
595 struct vc4_perfmon *perfmon;
598 + if (WARN_ON_ONCE(vc4->is_vc5))
602 DRM_DEBUG("Getting perfmon no VC4 V3D probed\n");
604 --- a/drivers/gpu/drm/vc4/vc4_render_cl.c
605 +++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
606 @@ -593,11 +593,15 @@ vc4_rcl_render_config_surface_setup(stru
608 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec)
610 + struct vc4_dev *vc4 = to_vc4_dev(dev);
611 struct vc4_rcl_setup setup = {0};
612 struct drm_vc4_submit_cl *args = exec->args;
613 bool has_bin = args->bin_cl_size != 0;
616 + if (WARN_ON_ONCE(vc4->is_vc5))
619 if (args->min_x_tile > args->max_x_tile ||
620 args->min_y_tile > args->max_y_tile) {
621 DRM_DEBUG("Bad render tile set (%d,%d)-(%d,%d)\n",
622 --- a/drivers/gpu/drm/vc4/vc4_v3d.c
623 +++ b/drivers/gpu/drm/vc4/vc4_v3d.c
624 @@ -127,6 +127,9 @@ static int vc4_v3d_debugfs_ident(struct
626 vc4_v3d_pm_get(struct vc4_dev *vc4)
628 + if (WARN_ON_ONCE(vc4->is_vc5))
631 mutex_lock(&vc4->power_lock);
632 if (vc4->power_refcount++ == 0) {
633 int ret = pm_runtime_get_sync(&vc4->v3d->pdev->dev);
634 @@ -145,6 +148,9 @@ vc4_v3d_pm_get(struct vc4_dev *vc4)
636 vc4_v3d_pm_put(struct vc4_dev *vc4)
638 + if (WARN_ON_ONCE(vc4->is_vc5))
641 mutex_lock(&vc4->power_lock);
642 if (--vc4->power_refcount == 0) {
643 pm_runtime_mark_last_busy(&vc4->v3d->pdev->dev);
644 @@ -172,6 +178,9 @@ int vc4_v3d_get_bin_slot(struct vc4_dev
646 struct vc4_exec_info *exec;
648 + if (WARN_ON_ONCE(vc4->is_vc5))
652 spin_lock_irqsave(&vc4->job_lock, irqflags);
653 slot = ffs(~vc4->bin_alloc_used);
654 @@ -316,6 +325,9 @@ int vc4_v3d_bin_bo_get(struct vc4_dev *v
658 + if (WARN_ON_ONCE(vc4->is_vc5))
661 mutex_lock(&vc4->bin_bo_lock);
664 @@ -348,6 +360,9 @@ static void bin_bo_release(struct kref *
666 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4)
668 + if (WARN_ON_ONCE(vc4->is_vc5))
671 mutex_lock(&vc4->bin_bo_lock);
672 kref_put(&vc4->bin_bo_kref, bin_bo_release);
673 mutex_unlock(&vc4->bin_bo_lock);
674 --- a/drivers/gpu/drm/vc4/vc4_validate.c
675 +++ b/drivers/gpu/drm/vc4/vc4_validate.c
676 @@ -105,9 +105,13 @@ size_is_lt(uint32_t width, uint32_t heig
677 struct drm_gem_cma_object *
678 vc4_use_bo(struct vc4_exec_info *exec, uint32_t hindex)
680 + struct vc4_dev *vc4 = exec->dev;
681 struct drm_gem_cma_object *obj;
684 + if (WARN_ON_ONCE(vc4->is_vc5))
687 if (hindex >= exec->bo_count) {
688 DRM_DEBUG("BO index %d greater than BO count %d\n",
689 hindex, exec->bo_count);
690 @@ -160,10 +164,14 @@ vc4_check_tex_size(struct vc4_exec_info
691 uint32_t offset, uint8_t tiling_format,
692 uint32_t width, uint32_t height, uint8_t cpp)
694 + struct vc4_dev *vc4 = exec->dev;
695 uint32_t aligned_width, aligned_height, stride, size;
696 uint32_t utile_w = utile_width(cpp);
697 uint32_t utile_h = utile_height(cpp);
699 + if (WARN_ON_ONCE(vc4->is_vc5))
702 /* The shaded vertex format stores signed 12.4 fixed point
703 * (-2048,2047) offsets from the viewport center, so we should
704 * never have a render target larger than 4096. The texture
705 @@ -482,10 +490,14 @@ vc4_validate_bin_cl(struct drm_device *d
707 struct vc4_exec_info *exec)
709 + struct vc4_dev *vc4 = to_vc4_dev(dev);
710 uint32_t len = exec->args->bin_cl_size;
711 uint32_t dst_offset = 0;
712 uint32_t src_offset = 0;
714 + if (WARN_ON_ONCE(vc4->is_vc5))
717 while (src_offset < len) {
718 void *dst_pkt = validated + dst_offset;
719 void *src_pkt = unvalidated + src_offset;
720 @@ -926,9 +938,13 @@ int
721 vc4_validate_shader_recs(struct drm_device *dev,
722 struct vc4_exec_info *exec)
724 + struct vc4_dev *vc4 = to_vc4_dev(dev);
728 + if (WARN_ON_ONCE(vc4->is_vc5))
731 for (i = 0; i < exec->shader_state_count; i++) {
732 ret = validate_gl_shader_rec(dev, exec, &exec->shader_state[i]);
734 --- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c
735 +++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
736 @@ -778,6 +778,7 @@ vc4_handle_branch_target(struct vc4_shad
737 struct vc4_validated_shader_info *
738 vc4_validate_shader(struct drm_gem_cma_object *shader_obj)
740 + struct vc4_dev *vc4 = to_vc4_dev(shader_obj->base.dev);
741 bool found_shader_end = false;
742 int shader_end_ip = 0;
743 uint32_t last_thread_switch_ip = -3;
744 @@ -785,6 +786,9 @@ vc4_validate_shader(struct drm_gem_cma_o
745 struct vc4_validated_shader_info *validated_shader = NULL;
746 struct vc4_shader_validation_state validation_state;
748 + if (WARN_ON_ONCE(vc4->is_vc5))
751 memset(&validation_state, 0, sizeof(validation_state));
752 validation_state.shader = shader_obj->vaddr;
753 validation_state.max_ip = shader_obj->base.size / sizeof(uint64_t);