1 From e2262c8ab4755ab574580611d7da22509f07871c Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Wed, 21 Aug 2019 14:55:56 +0100
4 Subject: [PATCH] clk-raspberrypi: Also support v3d clock
6 Signed-off-by: popcornmix <popcornmix@gmail.com>
8 drivers/clk/bcm/clk-raspberrypi.c | 501 ++++++++++++++++++++++++------
9 1 file changed, 412 insertions(+), 89 deletions(-)
11 --- a/drivers/clk/bcm/clk-raspberrypi.c
12 +++ b/drivers/clk/bcm/clk-raspberrypi.c
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
18 +#include <dt-bindings/clock/bcm2835.h>
19 #include <soc/bcm2835/raspberrypi-firmware.h>
21 #define RPI_FIRMWARE_ARM_CLK_ID 0x00000003
22 +#define RPI_FIRMWARE_V3D_CLK_ID 0x00000005
24 #define RPI_FIRMWARE_STATE_ENABLE_BIT BIT(0)
25 #define RPI_FIRMWARE_STATE_WAIT_BIT BIT(1)
28 - * Even though the firmware interface alters 'pllb' the frequencies are
29 - * provided as per 'pllb_arm'. We need to scale before passing them trough.
31 -#define RPI_FIRMWARE_PLLB_ARM_DIV_RATE 2
33 #define A2W_PLL_FRAC_BITS 20
35 +#define SOC_BCM2835 BIT(0)
36 +#define SOC_BCM2711 BIT(1)
37 +#define SOC_ALL (SOC_BCM2835 | SOC_BCM2711)
39 struct raspberrypi_clk {
41 struct rpi_firmware *firmware;
42 struct platform_device *cpufreq;
45 +typedef int (*raspberrypi_clk_register)(struct raspberrypi_clk *rpi,
49 +/* assignment helper macros for different clock types */
50 +#define _REGISTER(f, s, ...) { .clk_register = (raspberrypi_clk_register)f, \
52 + .data = __VA_ARGS__ }
53 +#define REGISTER_PLL(s, ...) _REGISTER(&raspberrypi_register_pll, \
55 + &(struct raspberrypi_pll_data) \
57 +#define REGISTER_PLL_DIV(s, ...) _REGISTER(&raspberrypi_register_pll_divider, \
59 + &(struct raspberrypi_pll_divider_data) \
61 +#define REGISTER_CLK(s, ...) _REGISTER(&raspberrypi_register_clock, \
63 + &(struct raspberrypi_clock_data) \
67 +struct raspberrypi_pll_data {
69 + const char *const *parents;
74 +struct raspberrypi_clock_data {
76 + const char *const *parents;
82 +struct raspberrypi_pll_divider_data {
84 + const char *divider_name;
86 + const char *source_pll;
93 - unsigned long min_rate;
94 - unsigned long max_rate;
95 +struct raspberrypi_clk_desc {
96 + raspberrypi_clk_register clk_register;
97 + unsigned int supported;
101 - struct clk_hw pllb;
102 - struct clk_hw *pllb_arm;
103 - struct clk_lookup *pllb_arm_lookup;
104 +struct raspberrypi_clock {
106 + struct raspberrypi_clk *rpi;
109 + const struct raspberrypi_clock_data *data;
112 +struct raspberrypi_pll {
114 + struct raspberrypi_clk *rpi;
117 + const struct raspberrypi_pll_data *data;
120 +struct raspberrypi_pll_divider {
121 + struct clk_divider div;
122 + struct raspberrypi_clk *rpi;
125 + const struct raspberrypi_pll_divider_data *data;
129 @@ -83,56 +153,49 @@ static int raspberrypi_clock_property(st
133 -static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
134 +static int raspberrypi_fw_is_on(struct raspberrypi_clk *rpi, u32 clock_id, const char *name)
136 - struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
141 ret = raspberrypi_clock_property(rpi->firmware,
142 RPI_FIRMWARE_GET_CLOCK_STATE,
143 - RPI_FIRMWARE_ARM_CLK_ID, &val);
148 return !!(val & RPI_FIRMWARE_STATE_ENABLE_BIT);
152 -static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
153 - unsigned long parent_rate)
154 +static unsigned long raspberrypi_fw_get_rate(struct raspberrypi_clk *rpi,
155 + u32 clock_id, const char *name, unsigned long parent_rate)
157 - struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
162 ret = raspberrypi_clock_property(rpi->firmware,
163 RPI_FIRMWARE_GET_CLOCK_RATE,
164 - RPI_FIRMWARE_ARM_CLK_ID,
170 - return val * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
171 + dev_err_ratelimited(rpi->dev, "Failed to get %s frequency: %d",
176 -static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
177 - unsigned long parent_rate)
178 +static int raspberrypi_fw_set_rate(struct raspberrypi_clk *rpi,
179 + u32 clock_id, const char *name, u32 rate,
180 + unsigned long parent_rate)
182 - struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
184 - u32 new_rate = rate / RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
187 ret = raspberrypi_clock_property(rpi->firmware,
188 RPI_FIRMWARE_SET_CLOCK_RATE,
189 - RPI_FIRMWARE_ARM_CLK_ID,
194 dev_err_ratelimited(rpi->dev, "Failed to change %s frequency: %d",
195 - clk_hw_get_name(hw), ret);
200 @@ -141,16 +204,18 @@ static int raspberrypi_fw_pll_set_rate(s
201 * Sadly there is no firmware rate rounding interface. We borrowed it from
204 -static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
205 +static int raspberrypi_determine_rate(struct raspberrypi_clk *rpi,
206 + u32 clock_id, const char *name, unsigned long min_rate, unsigned long max_rate,
207 struct clk_rate_request *req)
209 - struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
212 + req->rate = clamp(req->rate, min_rate, max_rate);
217 /* We can't use req->rate directly as it would overflow */
218 - final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate);
219 + final_rate = clamp(req->rate, min_rate, max_rate);
221 div = (u64)final_rate << A2W_PLL_FRAC_BITS;
222 do_div(div, req->best_parent_rate);
223 @@ -163,9 +228,129 @@ static int raspberrypi_pll_determine_rat
225 req->rate = final_rate >> A2W_PLL_FRAC_BITS;
231 +static int raspberrypi_fw_clock_is_on(struct clk_hw *hw)
233 + struct raspberrypi_clock *pll = container_of(hw, struct raspberrypi_clock, hw);
234 + struct raspberrypi_clk *rpi = pll->rpi;
235 + const struct raspberrypi_clock_data *data = pll->data;
237 + return raspberrypi_fw_is_on(rpi, data->clock_id, data->name);
240 +static unsigned long raspberrypi_fw_clock_get_rate(struct clk_hw *hw,
241 + unsigned long parent_rate)
243 + struct raspberrypi_clock *pll = container_of(hw, struct raspberrypi_clock, hw);
244 + struct raspberrypi_clk *rpi = pll->rpi;
245 + const struct raspberrypi_clock_data *data = pll->data;
247 + return raspberrypi_fw_get_rate(rpi, data->clock_id, data->name, parent_rate);
250 +static int raspberrypi_fw_clock_set_rate(struct clk_hw *hw, unsigned long rate,
251 + unsigned long parent_rate)
253 + struct raspberrypi_clock *pll = container_of(hw, struct raspberrypi_clock, hw);
254 + struct raspberrypi_clk *rpi = pll->rpi;
255 + const struct raspberrypi_clock_data *data = pll->data;
257 + return raspberrypi_fw_set_rate(rpi, data->clock_id, data->name, rate, parent_rate);
260 +static int raspberrypi_clock_determine_rate(struct clk_hw *hw,
261 + struct clk_rate_request *req)
263 + struct raspberrypi_clock *pll = container_of(hw, struct raspberrypi_clock, hw);
264 + struct raspberrypi_clk *rpi = pll->rpi;
265 + const struct raspberrypi_clock_data *data = pll->data;
267 + return raspberrypi_determine_rate(rpi, data->clock_id, data->name, pll->min_rate, pll->max_rate, req);
270 +static int raspberrypi_fw_pll_is_on(struct clk_hw *hw)
272 + struct raspberrypi_pll *pll = container_of(hw, struct raspberrypi_pll, hw);
273 + struct raspberrypi_clk *rpi = pll->rpi;
274 + const struct raspberrypi_pll_data *data = pll->data;
276 + return raspberrypi_fw_is_on(rpi, data->clock_id, data->name);
279 +static unsigned long raspberrypi_fw_pll_get_rate(struct clk_hw *hw,
280 + unsigned long parent_rate)
282 + struct raspberrypi_pll *pll = container_of(hw, struct raspberrypi_pll, hw);
283 + struct raspberrypi_clk *rpi = pll->rpi;
284 + const struct raspberrypi_pll_data *data = pll->data;
286 + return raspberrypi_fw_get_rate(rpi, data->clock_id, data->name, parent_rate);
289 +static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
290 + unsigned long parent_rate)
292 + struct raspberrypi_pll *pll = container_of(hw, struct raspberrypi_pll, hw);
293 + struct raspberrypi_clk *rpi = pll->rpi;
294 + const struct raspberrypi_pll_data *data = pll->data;
296 + return raspberrypi_fw_set_rate(rpi, data->clock_id, data->name, rate, parent_rate);
299 +static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
300 + struct clk_rate_request *req)
302 + struct raspberrypi_pll *pll = container_of(hw, struct raspberrypi_pll, hw);
303 + struct raspberrypi_clk *rpi = pll->rpi;
304 + const struct raspberrypi_pll_data *data = pll->data;
306 + return raspberrypi_determine_rate(rpi, data->clock_id, data->name, pll->min_rate, pll->max_rate, req);
310 +static int raspberrypi_fw_pll_div_is_on(struct clk_hw *hw)
312 + struct raspberrypi_pll_divider *pll = container_of(hw, struct raspberrypi_pll_divider, div.hw);
313 + struct raspberrypi_clk *rpi = pll->rpi;
314 + const struct raspberrypi_pll_divider_data *data = pll->data;
316 + return raspberrypi_fw_is_on(rpi, data->clock_id, data->name);
319 +static unsigned long raspberrypi_fw_pll_div_get_rate(struct clk_hw *hw,
320 + unsigned long parent_rate)
322 + struct raspberrypi_pll_divider *pll = container_of(hw, struct raspberrypi_pll_divider, div.hw);
323 + struct raspberrypi_clk *rpi = pll->rpi;
324 + const struct raspberrypi_pll_divider_data *data = pll->data;
326 + return raspberrypi_fw_get_rate(rpi, data->clock_id, data->name, parent_rate);
329 +static int raspberrypi_fw_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
330 + unsigned long parent_rate)
332 + struct raspberrypi_pll_divider *pll = container_of(hw, struct raspberrypi_pll_divider, div.hw);
333 + struct raspberrypi_clk *rpi = pll->rpi;
334 + const struct raspberrypi_pll_divider_data *data = pll->data;
336 + return raspberrypi_fw_set_rate(rpi, data->clock_id, data->name, rate, parent_rate);
339 +static int raspberrypi_pll_div_determine_rate(struct clk_hw *hw,
340 + struct clk_rate_request *req)
342 + struct raspberrypi_pll_divider *pll = container_of(hw, struct raspberrypi_pll_divider, div.hw);
343 + struct raspberrypi_clk *rpi = pll->rpi;
344 + const struct raspberrypi_pll_divider_data *data = pll->data;
346 + return raspberrypi_determine_rate(rpi, data->clock_id, data->name, pll->min_rate, pll->max_rate, req);
350 static const struct clk_ops raspberrypi_firmware_pll_clk_ops = {
351 .is_prepared = raspberrypi_fw_pll_is_on,
352 .recalc_rate = raspberrypi_fw_pll_get_rate,
353 @@ -173,87 +358,225 @@ static const struct clk_ops raspberrypi_
354 .determine_rate = raspberrypi_pll_determine_rate,
357 -static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
358 +static const struct clk_ops raspberrypi_firmware_pll_divider_clk_ops = {
359 + .is_prepared = raspberrypi_fw_pll_div_is_on,
360 + .recalc_rate = raspberrypi_fw_pll_div_get_rate,
361 + .set_rate = raspberrypi_fw_pll_div_set_rate,
362 + .determine_rate = raspberrypi_pll_div_determine_rate,
365 +static const struct clk_ops raspberrypi_firmware_clk_ops = {
366 + .is_prepared = raspberrypi_fw_clock_is_on,
367 + .recalc_rate = raspberrypi_fw_clock_get_rate,
368 + .set_rate = raspberrypi_fw_clock_set_rate,
369 + .determine_rate = raspberrypi_clock_determine_rate,
373 +static int raspberrypi_get_clock_range(struct raspberrypi_clk *rpi, u32 clock_id, u32 *min_rate, u32 *max_rate)
375 - u32 min_rate = 0, max_rate = 0;
378 + /* Get min & max rates set by the firmware */
379 + ret = raspberrypi_clock_property(rpi->firmware,
380 + RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
384 + dev_err(rpi->dev, "Failed to get clock %d min freq: %d (%d)\n",
385 + clock_id, *min_rate, ret);
389 + ret = raspberrypi_clock_property(rpi->firmware,
390 + RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
394 + dev_err(rpi->dev, "Failed to get clock %d max freq: %d (%d)\n",
395 + clock_id, *max_rate, ret);
402 +static int raspberrypi_register_pll(struct raspberrypi_clk *rpi,
403 + const struct raspberrypi_pll_data *data)
405 + struct raspberrypi_pll *pll;
406 struct clk_init_data init;
409 memset(&init, 0, sizeof(init));
411 /* All of the PLLs derive from the external oscillator. */
412 - init.parent_names = (const char *[]){ "osc" };
413 - init.num_parents = 1;
414 - init.name = "pllb";
415 + init.parent_names = data->parents;
416 + init.num_parents = data->num_parents;
417 + init.name = data->name;
418 init.ops = &raspberrypi_firmware_pll_clk_ops;
419 init.flags = CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED;
421 - /* Get min & max rates set by the firmware */
422 - ret = raspberrypi_clock_property(rpi->firmware,
423 - RPI_FIRMWARE_GET_MIN_CLOCK_RATE,
424 - RPI_FIRMWARE_ARM_CLK_ID,
426 + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
431 + pll->hw.init = &init;
433 + ret = raspberrypi_get_clock_range(rpi, data->clock_id, &pll->min_rate, &pll->max_rate);
435 - dev_err(rpi->dev, "Failed to get %s min freq: %d\n",
437 + dev_err(rpi->dev, "%s: raspberrypi_get_clock_range(%s) failed: %d\n", __func__, init.name, ret);
441 - ret = raspberrypi_clock_property(rpi->firmware,
442 - RPI_FIRMWARE_GET_MAX_CLOCK_RATE,
443 - RPI_FIRMWARE_ARM_CLK_ID,
445 + ret = devm_clk_hw_register(rpi->dev, &pll->hw);
447 - dev_err(rpi->dev, "Failed to get %s max freq: %d\n",
449 + dev_err(rpi->dev, "%s: devm_clk_hw_register(%s) failed: %d\n", __func__, init.name, ret);
455 - if (!min_rate || !max_rate) {
456 - dev_err(rpi->dev, "Unexpected frequency range: min %u, max %u\n",
457 - min_rate, max_rate);
461 +raspberrypi_register_pll_divider(struct raspberrypi_clk *rpi,
462 + const struct raspberrypi_pll_divider_data *data)
464 + struct raspberrypi_pll_divider *divider;
465 + struct clk_init_data init;
468 + memset(&init, 0, sizeof(init));
470 + init.parent_names = &data->source_pll;
471 + init.num_parents = 1;
472 + init.name = data->name;
473 + init.ops = &raspberrypi_firmware_pll_divider_clk_ops;
474 + init.flags = data->flags | CLK_IGNORE_UNUSED;
476 - dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
477 - min_rate, max_rate);
478 + divider = devm_kzalloc(rpi->dev, sizeof(*divider), GFP_KERNEL);
482 + divider->div.hw.init = &init;
483 + divider->rpi = rpi;
484 + divider->data = data;
486 + ret = raspberrypi_get_clock_range(rpi, data->clock_id, ÷r->min_rate, ÷r->max_rate);
488 + dev_err(rpi->dev, "%s: raspberrypi_get_clock_range(%s) failed: %d\n", __func__, init.name, ret);
492 - rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
493 - rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
494 + ret = devm_clk_hw_register(rpi->dev, ÷r->div.hw);
496 + dev_err(rpi->dev, "%s: devm_clk_hw_register(%s) failed: %d\n", __func__, init.name, ret);
500 - rpi->pllb.init = &init;
502 + * PLLH's channels have a fixed divide by 10 afterwards, which
503 + * is what our consumers are actually using.
505 + if (data->fixed_divider != 0) {
506 + struct clk_lookup *lookup;
507 + struct clk_hw *clk = clk_hw_register_fixed_factor(rpi->dev,
508 + data->divider_name,
510 + CLK_SET_RATE_PARENT,
512 + data->fixed_divider);
514 + dev_err(rpi->dev, "%s: clk_hw_register_fixed_factor(%s) failed: %ld\n", __func__, init.name, PTR_ERR(clk));
515 + return PTR_ERR(clk);
517 + if (data->lookup) {
518 + lookup = clkdev_hw_create(clk, NULL, data->lookup);
519 + if (IS_ERR(lookup)) {
520 + dev_err(rpi->dev, "%s: clk_hw_register_fixed_factor(%s) failed: %ld\n", __func__, init.name, PTR_ERR(lookup));
521 + return PTR_ERR(lookup);
526 - return devm_clk_hw_register(rpi->dev, &rpi->pllb);
530 -static int raspberrypi_register_pllb_arm(struct raspberrypi_clk *rpi)
531 +static int raspberrypi_register_clock(struct raspberrypi_clk *rpi,
532 + const struct raspberrypi_clock_data *data)
534 - rpi->pllb_arm = clk_hw_register_fixed_factor(rpi->dev,
535 - "pllb_arm", "pllb",
536 - CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
538 - if (IS_ERR(rpi->pllb_arm)) {
539 - dev_err(rpi->dev, "Failed to initialize pllb_arm\n");
540 - return PTR_ERR(rpi->pllb_arm);
542 + struct raspberrypi_clock *clock;
543 + struct clk_init_data init;
547 + memset(&init, 0, sizeof(init));
548 + init.parent_names = data->parents;
549 + init.num_parents = data->num_parents;
550 + init.name = data->name;
551 + init.flags = data->flags | CLK_IGNORE_UNUSED;
553 - rpi->pllb_arm_lookup = clkdev_hw_create(rpi->pllb_arm, NULL, "cpu0");
554 - if (!rpi->pllb_arm_lookup) {
555 - dev_err(rpi->dev, "Failed to initialize pllb_arm_lookup\n");
556 - clk_hw_unregister_fixed_factor(rpi->pllb_arm);
557 + init.ops = &raspberrypi_firmware_clk_ops;
559 + clock = devm_kzalloc(rpi->dev, sizeof(*clock), GFP_KERNEL);
565 + clock->data = data;
566 + clock->hw.init = &init;
568 + ret = raspberrypi_get_clock_range(rpi, data->clock_id, &clock->min_rate, &clock->max_rate);
570 + dev_err(rpi->dev, "%s: raspberrypi_get_clock_range(%s) failed: %d\n", __func__, init.name, ret);
573 + clk = devm_clk_register(rpi->dev, &clock->hw);
575 + dev_err(rpi->dev, "%s: devm_clk_register(%s) failed: %ld\n", __func__, init.name, PTR_ERR(clk));
576 + return PTR_ERR(clk);
578 + ret = clk_register_clkdev(clk, init.name, NULL);
580 + dev_err(rpi->dev, "%s: clk_register_clkdev(%s) failed: %d\n", __func__, init.name, ret);
588 + * the real definition of all the pll, pll_dividers and clocks
589 + * these make use of the above REGISTER_* macros
591 +static const struct raspberrypi_clk_desc clk_desc_array[] = {
592 + /* the PLL + PLL dividers */
593 + [BCM2835_CLOCK_V3D] = REGISTER_CLK(
596 + .parents = (const char *[]){ "osc" },
598 + .clock_id = RPI_FIRMWARE_V3D_CLK_ID),
599 + [BCM2835_PLLB_ARM] = REGISTER_PLL_DIV(
602 + .source_pll = "osc",
603 + .divider_name = "pllb_arm",
605 + .fixed_divider = 1,
606 + .clock_id = RPI_FIRMWARE_ARM_CLK_ID,
607 + .flags = CLK_SET_RATE_PARENT),
610 static int raspberrypi_clk_probe(struct platform_device *pdev)
612 struct device_node *firmware_node;
613 struct device *dev = &pdev->dev;
614 struct rpi_firmware *firmware;
615 struct raspberrypi_clk *rpi;
617 + const struct raspberrypi_clk_desc *desc;
618 + const size_t asize = ARRAY_SIZE(clk_desc_array);
621 firmware_node = of_find_compatible_node(NULL, NULL,
622 "raspberrypi,bcm2835-firmware");
623 @@ -275,16 +598,16 @@ static int raspberrypi_clk_probe(struct
624 rpi->firmware = firmware;
625 platform_set_drvdata(pdev, rpi);
627 - ret = raspberrypi_register_pllb(rpi);
629 - dev_err(dev, "Failed to initialize pllb, %d\n", ret);
631 + for (i = 0; i < asize; i++) {
632 + desc = &clk_desc_array[i];
633 + if (desc->clk_register && desc->data /*&&
634 + (desc->supported & pdata->soc)*/) {
635 + int ret = desc->clk_register(rpi, desc->data);
641 - ret = raspberrypi_register_pllb_arm(rpi);
645 rpi->cpufreq = platform_device_register_data(dev, "raspberrypi-cpufreq",