1 From fe90ee51b283f7cbbce9980b76b3da8b31d39c60 Mon Sep 17 00:00:00 2001
2 From: MikeDK <m.kaplan@evva.com>
3 Date: Fri, 31 Jan 2020 10:57:21 +0100
4 Subject: [PATCH] overlays: Add ssd1306-spi, ssh1106-spi, ssd-1351-spi
6 Add overlays for SSD1306, SH1106 and SSD1351 based OLED displays.
7 SH1106 is present in many 1.3 inch OLEDs and SSD1351 is present in
8 1.5 inch RGB OLEDs from AliExpress.
10 This will load the staging fbtft drivers.
12 Signed-off-by: Michael Kaplan <m.kaplan@evva.com>
14 arch/arm/boot/dts/overlays/Makefile | 3 +
15 arch/arm/boot/dts/overlays/README | 35 ++++++++
16 .../boot/dts/overlays/sh1106-spi-overlay.dts | 84 +++++++++++++++++++
17 .../boot/dts/overlays/ssd1306-spi-overlay.dts | 84 +++++++++++++++++++
18 .../boot/dts/overlays/ssd1351-spi-overlay.dts | 83 ++++++++++++++++++
19 5 files changed, 289 insertions(+)
20 create mode 100644 arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts
21 create mode 100644 arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts
22 create mode 100644 arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts
24 --- a/arch/arm/boot/dts/overlays/Makefile
25 +++ b/arch/arm/boot/dts/overlays/Makefile
26 @@ -145,6 +145,7 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
34 @@ -168,6 +169,8 @@ dtbo-$(CONFIG_ARCH_BCM2835) += \
40 superaudioboard.dtbo \
43 --- a/arch/arm/boot/dts/overlays/README
44 +++ b/arch/arm/boot/dts/overlays/README
45 @@ -2145,6 +2145,18 @@ Params: overclock_50 Clock (i
50 +Info: Overlay for SH1106 OLED via SPI using fbtft staging driver.
51 +Load: dtoverlay=sh1106-spi,<param>=<val>
52 +Params: speed SPI bus speed (default 4000000)
53 + rotate Display rotation (0, 90, 180 or 270; default 0)
54 + fps Delay between frame updates (default 25)
55 + debug Debug output level (0-7; default 0)
56 + dc_pin GPIO pin for D/C (default 24)
57 + reset_pin GPIO pin for RESET (default 25)
58 + height Display height (32 or 64; default 64)
62 Info: Enables the Secondary Memory Interface peripheral. Uses GPIOs 2-25!
64 @@ -2428,6 +2440,29 @@ Params: address Location
65 https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf
69 +Info: Overlay for SSD1306 OLED via SPI using fbtft staging driver.
70 +Load: dtoverlay=ssd1306-spi,<param>=<val>
71 +Params: speed SPI bus speed (default 10000000)
72 + rotate Display rotation (0, 90, 180 or 270; default 0)
73 + fps Delay between frame updates (default 25)
74 + debug Debug output level (0-7; default 0)
75 + dc_pin GPIO pin for D/C (default 24)
76 + reset_pin GPIO pin for RESET (default 25)
77 + height Display height (32 or 64; default 64)
81 +Info: Overlay for SSD1351 OLED via SPI using fbtft staging driver.
82 +Load: dtoverlay=ssd1351-spi,<param>=<val>
83 +Params: speed SPI bus speed (default 4500000)
84 + rotate Display rotation (0, 90, 180 or 270; default 0)
85 + fps Delay between frame updates (default 25)
86 + debug Debug output level (0-7; default 0)
87 + dc_pin GPIO pin for D/C (default 24)
88 + reset_pin GPIO pin for RESET (default 25)
92 Info: Configures the SuperAudioBoard sound card
93 Load: dtoverlay=superaudioboard,<param>=<val>
95 +++ b/arch/arm/boot/dts/overlays/sh1106-spi-overlay.dts
98 + * Device Tree overlay for SH1106 based SPI OLED display
106 + compatible = "brcm,bcm2835";
116 + target = <&spidev0>;
118 + status = "disabled";
123 + target = <&spidev1>;
125 + status = "disabled";
132 + sh1106_pins: sh1106_pins {
133 + brcm,pins = <25 24>;
134 + brcm,function = <1 1>; /* out out */
142 + /* needed to avoid dtc warning */
143 + #address-cells = <1>;
147 + compatible = "sinowealth,sh1106";
149 + pinctrl-names = "default";
150 + pinctrl-0 = <&sh1106_pins>;
152 + spi-max-frequency = <4000000>;
158 + reset-gpios = <&gpio 25 0>;
159 + dc-gpios = <&gpio 24 0>;
162 + sinowealth,height = <64>;
163 + sinowealth,width = <128>;
164 + sinowealth,page-offset = <0>;
170 + speed = <&sh1106>,"spi-max-frequency:0";
171 + rotate = <&sh1106>,"rotate:0";
172 + fps = <&sh1106>,"fps:0";
173 + debug = <&sh1106>,"debug:0";
174 + dc_pin = <&sh1106>,"dc-gpios:4",
175 + <&sh1106_pins>,"brcm,pins:4";
176 + reset_pin = <&sh1106>,"reset-gpios:4",
177 + <&sh1106_pins>,"brcm,pins:0";
178 + height = <&sh1106>,"sinowealth,height:0";
182 +++ b/arch/arm/boot/dts/overlays/ssd1306-spi-overlay.dts
185 + * Device Tree overlay for SSD1306 based SPI OLED display
193 + compatible = "brcm,bcm2835";
203 + target = <&spidev0>;
205 + status = "disabled";
210 + target = <&spidev1>;
212 + status = "disabled";
219 + ssd1306_pins: ssd1306_pins {
220 + brcm,pins = <25 24>;
221 + brcm,function = <1 1>; /* out out */
229 + /* needed to avoid dtc warning */
230 + #address-cells = <1>;
233 + ssd1306: ssd1306@0{
234 + compatible = "solomon,ssd1306";
236 + pinctrl-names = "default";
237 + pinctrl-0 = <&ssd1306_pins>;
239 + spi-max-frequency = <10000000>;
245 + reset-gpios = <&gpio 25 0>;
246 + dc-gpios = <&gpio 24 0>;
249 + solomon,height = <64>;
250 + solomon,width = <128>;
251 + solomon,page-offset = <0>;
257 + speed = <&ssd1306>,"spi-max-frequency:0";
258 + rotate = <&ssd1306>,"rotate:0";
259 + fps = <&ssd1306>,"fps:0";
260 + debug = <&ssd1306>,"debug:0";
261 + dc_pin = <&ssd1306>,"dc-gpios:4",
262 + <&ssd1306_pins>,"brcm,pins:4";
263 + reset_pin = <&ssd1306>,"reset-gpios:4",
264 + <&ssd1306_pins>,"brcm,pins:0";
265 + height = <&ssd1306>,"solomon,height:0";
269 +++ b/arch/arm/boot/dts/overlays/ssd1351-spi-overlay.dts
272 + * Device Tree overlay for SSD1351 based SPI OLED display
280 + compatible = "brcm,bcm2835";
290 + target = <&spidev0>;
292 + status = "disabled";
297 + target = <&spidev1>;
299 + status = "disabled";
306 + ssd1351_pins: ssd1351_pins {
307 + brcm,pins = <25 24>;
308 + brcm,function = <1 1>; /* out out */
316 + /* needed to avoid dtc warning */
317 + #address-cells = <1>;
320 + ssd1351: ssd1351@0{
321 + compatible = "solomon,ssd1351";
323 + pinctrl-names = "default";
324 + pinctrl-0 = <&ssd1351_pins>;
326 + spi-max-frequency = <4500000>;
332 + reset-gpios = <&gpio 25 0>;
333 + dc-gpios = <&gpio 24 0>;
336 + solomon,height = <128>;
337 + solomon,width = <128>;
338 + solomon,page-offset = <0>;
344 + speed = <&ssd1351>,"spi-max-frequency:0";
345 + rotate = <&ssd1351>,"rotate:0";
346 + fps = <&ssd1351>,"fps:0";
347 + debug = <&ssd1351>,"debug:0";
348 + dc_pin = <&ssd1351>,"dc-gpios:4",
349 + <&ssd1351_pins>,"brcm,pins:4";
350 + reset_pin = <&ssd1351>,"reset-gpios:4",
351 + <&ssd1351_pins>,"brcm,pins:0";