1 From 19a0ac654994661f63f7c9e099ed91a1210af161 Mon Sep 17 00:00:00 2001
2 From: Stefan Wahren <wahrenst@gmx.net>
3 Date: Sun, 6 Oct 2019 15:41:25 +0200
4 Subject: [PATCH] ARM: dts: Add minimal Raspberry Pi 4 support
6 This adds minimal support for the new Raspberry Pi 4 without the
7 fancy stuff like GENET, PCIe, xHCI, 40 bit DMA and V3D. The RPi 4 is
8 available in 3 different variants (1, 2 and 4 GB RAM), so leave the memory
9 size to zero and let the bootloader take care of it. The DWC2 is still
10 usable as peripheral via the USB-C port.
12 Other differences to the Raspberry Pi 3:
13 - additional GIC 400 Interrupt controller
14 - new thermal IP and HWRNG
15 - additional MMC interface (emmc2)
16 - additional UART, I2C, SPI and PWM interfaces
17 - clock stretching bug in I2C IP has been fixed
19 Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
20 Acked-by: Eric Anholt <eric@anholt.net>
21 Acked-by: Florian Fanelli <f.fainelli@gmail.com>
23 arch/arm/boot/dts/Makefile | 1 +
24 arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 123 +++
25 arch/arm/boot/dts/bcm2711.dtsi | 844 ++++++++++++++++++
26 .../boot/dts/bcm283x-rpi-usb-peripheral.dtsi | 7 +
27 4 files changed, 975 insertions(+)
28 create mode 100644 arch/arm/boot/dts/bcm2711-rpi-4-b.dts
29 create mode 100644 arch/arm/boot/dts/bcm2711.dtsi
30 create mode 100644 arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi
32 --- a/arch/arm/boot/dts/Makefile
33 +++ b/arch/arm/boot/dts/Makefile
34 @@ -97,6 +97,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += \
36 bcm2837-rpi-3-b-plus.dtb \
37 bcm2837-rpi-cm3-io3.dtb \
38 + bcm2711-rpi-4-b.dtb \
39 bcm2835-rpi-zero.dtb \
40 bcm2835-rpi-zero-w.dtb
41 dtb-$(CONFIG_ARCH_BCM_5301X) += \
43 +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
45 +// SPDX-License-Identifier: GPL-2.0
47 +#include "bcm2711.dtsi"
48 +#include "bcm2835-rpi.dtsi"
49 +#include "bcm283x-rpi-usb-peripheral.dtsi"
52 + compatible = "raspberrypi,4-model-b", "brcm,bcm2711";
53 + model = "Raspberry Pi 4 Model B";
56 + /* 8250 auxiliary UART instead of pl011 */
57 + stdout-path = "serial1:115200n8";
60 + /* Will be filled by the bootloader */
62 + device_type = "memory";
68 + gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;
73 + gpios = <&expgpio 2 GPIO_ACTIVE_LOW>;
77 + wifi_pwrseq: wifi-pwrseq {
78 + compatible = "mmc-pwrseq-simple";
79 + reset-gpios = <&expgpio 1 GPIO_ACTIVE_LOW>;
82 + sd_io_1v8_reg: sd_io_1v8_reg {
83 + compatible = "regulator-gpio";
84 + regulator-name = "vdd-sd-io";
85 + regulator-min-microvolt = <1800000>;
86 + regulator-max-microvolt = <3300000>;
88 + regulator-always-on;
89 + regulator-settling-time-us = <5000>;
90 + gpios = <&expgpio 4 GPIO_ACTIVE_HIGH>;
91 + states = <1800000 0x1
99 + compatible = "raspberrypi,firmware-gpio";
102 + gpio-line-names = "BT_ON",
115 + pinctrl-names = "default";
116 + pinctrl-0 = <&pwm1_0_gpio40 &pwm1_1_gpio41>;
120 +/* SDHCI is used to control the SDIO for wireless */
122 + #address-cells = <1>;
124 + pinctrl-names = "default";
125 + pinctrl-0 = <&emmc_gpio34>;
128 + mmc-pwrseq = <&wifi_pwrseq>;
133 + compatible = "brcm,bcm4329-fmac";
137 +/* EMMC2 is used to drive the SD card */
139 + vqmmc-supply = <&sd_io_1v8_reg>;
144 +/* uart0 communicates with the BT module */
146 + pinctrl-names = "default";
147 + pinctrl-0 = <&uart0_ctsrts_gpio30 &uart0_gpio32>;
152 + compatible = "brcm,bcm43438-bt";
153 + max-speed = <2000000>;
154 + shutdown-gpios = <&expgpio 0 GPIO_ACTIVE_HIGH>;
158 +/* uart1 is mapped to the pin header */
160 + pinctrl-names = "default";
161 + pinctrl-0 = <&uart1_gpio14>;
166 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
169 +++ b/arch/arm/boot/dts/bcm2711.dtsi
171 +// SPDX-License-Identifier: GPL-2.0
172 +#include "bcm283x.dtsi"
174 +#include <dt-bindings/interrupt-controller/arm-gic.h>
175 +#include <dt-bindings/soc/bcm2835-pm.h>
178 + compatible = "brcm,bcm2711";
180 + #address-cells = <2>;
183 + interrupt-parent = <&gicv2>;
188 + * Common BCM283x peripherals
189 + * BCM2711-specific peripherals
190 + * ARM-local peripherals
192 + ranges = <0x7e000000 0x0 0xfe000000 0x01800000>,
193 + <0x7c000000 0x0 0xfc000000 0x02000000>,
194 + <0x40000000 0x0 0xff800000 0x00800000>;
195 + /* Emulate a contiguous 30-bit address range for DMA */
196 + dma-ranges = <0xc0000000 0x0 0x00000000 0x3c000000>;
199 + * This node is the provider for the enable-method for
200 + * bringing up secondary cores.
202 + local_intc: local_intc@40000000 {
203 + compatible = "brcm,bcm2836-l1-intc";
204 + reg = <0x40000000 0x100>;
207 + gicv2: interrupt-controller@40041000 {
208 + interrupt-controller;
209 + #interrupt-cells = <3>;
210 + compatible = "arm,gic-400";
211 + reg = <0x40041000 0x1000>,
212 + <0x40042000 0x2000>,
213 + <0x40044000 0x2000>,
214 + <0x40046000 0x2000>;
215 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
216 + IRQ_TYPE_LEVEL_HIGH)>;
219 + dma: dma@7e007000 {
220 + compatible = "brcm,bcm2835-dma";
221 + reg = <0x7e007000 0xb00>;
222 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
223 + <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
224 + <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
225 + <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
226 + <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
227 + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
228 + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
229 + /* DMA lite 7 - 10 */
230 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
231 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
232 + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
233 + <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
234 + interrupt-names = "dma0",
246 + brcm,dma-channel-mask = <0x07f5>;
249 + pm: watchdog@7e100000 {
250 + compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
251 + #power-domain-cells = <1>;
252 + #reset-cells = <1>;
253 + reg = <0x7e100000 0x114>,
256 + clocks = <&clocks BCM2835_CLOCK_V3D>,
257 + <&clocks BCM2835_CLOCK_PERI_IMAGE>,
258 + <&clocks BCM2835_CLOCK_H264>,
259 + <&clocks BCM2835_CLOCK_ISP>;
260 + clock-names = "v3d", "peri_image", "h264", "isp";
261 + system-power-controller;
265 + interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
267 + /* RNG is incompatible with brcm,bcm2835-rng */
268 + status = "disabled";
271 + uart2: serial@7e201400 {
272 + compatible = "arm,pl011", "arm,primecell";
273 + reg = <0x7e201400 0x200>;
274 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
275 + clocks = <&clocks BCM2835_CLOCK_UART>,
276 + <&clocks BCM2835_CLOCK_VPU>;
277 + clock-names = "uartclk", "apb_pclk";
278 + arm,primecell-periphid = <0x00241011>;
279 + status = "disabled";
282 + uart3: serial@7e201600 {
283 + compatible = "arm,pl011", "arm,primecell";
284 + reg = <0x7e201600 0x200>;
285 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
286 + clocks = <&clocks BCM2835_CLOCK_UART>,
287 + <&clocks BCM2835_CLOCK_VPU>;
288 + clock-names = "uartclk", "apb_pclk";
289 + arm,primecell-periphid = <0x00241011>;
290 + status = "disabled";
293 + uart4: serial@7e201800 {
294 + compatible = "arm,pl011", "arm,primecell";
295 + reg = <0x7e201800 0x200>;
296 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
297 + clocks = <&clocks BCM2835_CLOCK_UART>,
298 + <&clocks BCM2835_CLOCK_VPU>;
299 + clock-names = "uartclk", "apb_pclk";
300 + arm,primecell-periphid = <0x00241011>;
301 + status = "disabled";
304 + uart5: serial@7e201a00 {
305 + compatible = "arm,pl011", "arm,primecell";
306 + reg = <0x7e201a00 0x200>;
307 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
308 + clocks = <&clocks BCM2835_CLOCK_UART>,
309 + <&clocks BCM2835_CLOCK_VPU>;
310 + clock-names = "uartclk", "apb_pclk";
311 + arm,primecell-periphid = <0x00241011>;
312 + status = "disabled";
315 + spi3: spi@7e204600 {
316 + compatible = "brcm,bcm2835-spi";
317 + reg = <0x7e204600 0x0200>;
318 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
319 + clocks = <&clocks BCM2835_CLOCK_VPU>;
320 + #address-cells = <1>;
322 + status = "disabled";
325 + spi4: spi@7e204800 {
326 + compatible = "brcm,bcm2835-spi";
327 + reg = <0x7e204800 0x0200>;
328 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
329 + clocks = <&clocks BCM2835_CLOCK_VPU>;
330 + #address-cells = <1>;
332 + status = "disabled";
335 + spi5: spi@7e204a00 {
336 + compatible = "brcm,bcm2835-spi";
337 + reg = <0x7e204a00 0x0200>;
338 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
339 + clocks = <&clocks BCM2835_CLOCK_VPU>;
340 + #address-cells = <1>;
342 + status = "disabled";
345 + spi6: spi@7e204c00 {
346 + compatible = "brcm,bcm2835-spi";
347 + reg = <0x7e204c00 0x0200>;
348 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
349 + clocks = <&clocks BCM2835_CLOCK_VPU>;
350 + #address-cells = <1>;
352 + status = "disabled";
355 + i2c3: i2c@7e205600 {
356 + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
357 + reg = <0x7e205600 0x200>;
358 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
359 + clocks = <&clocks BCM2835_CLOCK_VPU>;
360 + #address-cells = <1>;
362 + status = "disabled";
365 + i2c4: i2c@7e205800 {
366 + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
367 + reg = <0x7e205800 0x200>;
368 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
369 + clocks = <&clocks BCM2835_CLOCK_VPU>;
370 + #address-cells = <1>;
372 + status = "disabled";
375 + i2c5: i2c@7e205a00 {
376 + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
377 + reg = <0x7e205a00 0x200>;
378 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
379 + clocks = <&clocks BCM2835_CLOCK_VPU>;
380 + #address-cells = <1>;
382 + status = "disabled";
385 + i2c6: i2c@7e205c00 {
386 + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
387 + reg = <0x7e205c00 0x200>;
388 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
389 + clocks = <&clocks BCM2835_CLOCK_VPU>;
390 + #address-cells = <1>;
392 + status = "disabled";
395 + pwm1: pwm@7e20c800 {
396 + compatible = "brcm,bcm2835-pwm";
397 + reg = <0x7e20c800 0x28>;
398 + clocks = <&clocks BCM2835_CLOCK_PWM>;
399 + assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
400 + assigned-clock-rates = <10000000>;
402 + status = "disabled";
405 + emmc2: emmc2@7e340000 {
406 + compatible = "brcm,bcm2711-emmc2";
407 + reg = <0x7e340000 0x100>;
408 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
409 + clocks = <&clocks BCM2711_CLOCK_EMMC2>;
410 + status = "disabled";
414 + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
419 + compatible = "arm,cortex-a72-pmu", "arm,armv8-pmuv3";
420 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
421 + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
422 + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
423 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
424 + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
428 + compatible = "arm,armv8-timer";
429 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
430 + IRQ_TYPE_LEVEL_LOW)>,
431 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
432 + IRQ_TYPE_LEVEL_LOW)>,
433 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
434 + IRQ_TYPE_LEVEL_LOW)>,
435 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
436 + IRQ_TYPE_LEVEL_LOW)>;
437 + /* This only applies to the ARMv7 stub */
438 + arm,cpu-registers-not-fw-configured;
442 + #address-cells = <1>;
444 + enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
447 + device_type = "cpu";
448 + compatible = "arm,cortex-a72";
450 + enable-method = "spin-table";
451 + cpu-release-addr = <0x0 0x000000d8>;
455 + device_type = "cpu";
456 + compatible = "arm,cortex-a72";
458 + enable-method = "spin-table";
459 + cpu-release-addr = <0x0 0x000000e0>;
463 + device_type = "cpu";
464 + compatible = "arm,cortex-a72";
466 + enable-method = "spin-table";
467 + cpu-release-addr = <0x0 0x000000e8>;
471 + device_type = "cpu";
472 + compatible = "arm,cortex-a72";
474 + enable-method = "spin-table";
475 + cpu-release-addr = <0x0 0x000000f0>;
481 + clock-frequency = <54000000>;
485 + compatible = "brcm,bcm2711-cprman";
489 + coefficients = <(-487) 410040>;
493 + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
497 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
501 + compatible = "brcm,bcm2711-gpio";
502 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
503 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
504 + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
505 + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
507 + gpclk0_gpio49: gpclk0_gpio49 {
514 + gpclk1_gpio50: gpclk1_gpio50 {
521 + gpclk2_gpio51: gpclk2_gpio51 {
529 + i2c0_gpio46: i2c0_gpio46 {
541 + i2c1_gpio46: i2c1_gpio46 {
553 + i2c3_gpio2: i2c3_gpio2 {
565 + i2c3_gpio4: i2c3_gpio4 {
577 + i2c4_gpio6: i2c4_gpio6 {
589 + i2c4_gpio8: i2c4_gpio8 {
601 + i2c5_gpio10: i2c5_gpio10 {
613 + i2c5_gpio12: i2c5_gpio12 {
625 + i2c6_gpio0: i2c6_gpio0 {
637 + i2c6_gpio22: i2c6_gpio22 {
649 + i2c_slave_gpio8: i2c_slave_gpio8 {
659 + jtag_gpio48: jtag_gpio48 {
671 + mii_gpio28: mii_gpio28 {
680 + mii_gpio36: mii_gpio36 {
690 + pcm_gpio50: pcm_gpio50 {
700 + pwm0_0_gpio12: pwm0_0_gpio12 {
707 + pwm0_0_gpio18: pwm0_0_gpio18 {
714 + pwm1_0_gpio40: pwm1_0_gpio40 {
721 + pwm0_1_gpio13: pwm0_1_gpio13 {
728 + pwm0_1_gpio19: pwm0_1_gpio19 {
735 + pwm1_1_gpio41: pwm1_1_gpio41 {
742 + pwm0_1_gpio45: pwm0_1_gpio45 {
749 + pwm0_0_gpio52: pwm0_0_gpio52 {
756 + pwm0_1_gpio53: pwm0_1_gpio53 {
764 + rgmii_gpio35: rgmii_gpio35 {
774 + rgmii_irq_gpio34: rgmii_irq_gpio34 {
780 + rgmii_irq_gpio39: rgmii_irq_gpio39 {
786 + rgmii_mdio_gpio28: rgmii_mdio_gpio28 {
793 + rgmii_mdio_gpio37: rgmii_mdio_gpio37 {
801 + spi0_gpio46: spi0_gpio46 {
810 + spi2_gpio46: spi2_gpio46 {
820 + spi3_gpio0: spi3_gpio0 {
829 + spi4_gpio4: spi4_gpio4 {
838 + spi5_gpio12: spi5_gpio12 {
847 + spi6_gpio18: spi6_gpio18 {
857 + uart2_gpio0: uart2_gpio0 {
869 + uart2_ctsrts_gpio2: uart2_ctsrts_gpio2 {
881 + uart3_gpio4: uart3_gpio4 {
893 + uart3_ctsrts_gpio6: uart3_ctsrts_gpio6 {
905 + uart4_gpio8: uart4_gpio8 {
917 + uart4_ctsrts_gpio10: uart4_ctsrts_gpio10 {
929 + uart5_gpio12: uart5_gpio12 {
941 + uart5_ctsrts_gpio14: uart5_ctsrts_gpio14 {
956 + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
957 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
961 + compatible = "brcm,bcm2711-i2c", "brcm,bcm2835-i2c";
962 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
966 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
970 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
974 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
978 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
982 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
986 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
990 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
991 + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
992 + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
993 + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
997 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1001 + interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1005 + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1009 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1013 + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1016 +++ b/arch/arm/boot/dts/bcm283x-rpi-usb-peripheral.dtsi
1018 +// SPDX-License-Identifier: GPL-2.0
1020 + dr_mode = "peripheral";
1021 + g-rx-fifo-size = <256>;
1022 + g-np-tx-fifo-size = <32>;
1023 + g-tx-fifo-size = <256 256 512 512 512 768 768>;