1 From 0ec0bc884f6cf1ec9775c750f78ce28be7da4340 Mon Sep 17 00:00:00 2001
2 From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
3 Date: Mon, 16 Dec 2019 12:01:08 +0100
4 Subject: [PATCH] ARM: dts: bcm2711: Enable PCIe controller
6 commit d5c8dc0d4c880fbde5293cc186b1ab23466254c4 upstream.
8 This enables bcm2711's PCIe bus, which is hardwired to a VIA
9 Technologies XHCI USB 3.0 controller.
11 Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
12 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
14 arch/arm/boot/dts/bcm2711.dtsi | 31 ++++++++++++++++++++++++++++++-
15 1 file changed, 30 insertions(+), 1 deletion(-)
17 --- a/arch/arm/boot/dts/bcm2711.dtsi
18 +++ b/arch/arm/boot/dts/bcm2711.dtsi
23 - ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>;
24 + ranges = <0x0 0x7c000000 0x0 0xfc000000 0x03800000>,
25 + <0x6 0x00000000 0x6 0x00000000 0x40000000>;
27 + pcie0: pcie@7d500000 {
28 + compatible = "brcm,bcm2711-pcie";
29 + reg = <0x0 0x7d500000 0x9310>;
30 + device_type = "pci";
31 + #address-cells = <3>;
32 + #interrupt-cells = <1>;
34 + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
35 + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
36 + interrupt-names = "pcie", "msi";
37 + interrupt-map-mask = <0x0 0x0 0x0 0x7>;
38 + interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
39 + IRQ_TYPE_LEVEL_HIGH>;
41 + msi-parent = <&pcie0>;
43 + ranges = <0x02000000 0x0 0xf8000000 0x6 0x00000000
46 + * The wrapper around the PCIe block has a bug
47 + * preventing it from accessing beyond the first 3GB of
50 + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
55 genet: ethernet@7d580000 {
56 compatible = "brcm,bcm2711-genet-v5";