1 From a106e57a643c957af9a71eb2ec3a62df69a1f371 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Thu, 26 Dec 2019 13:49:17 +0100
4 Subject: [PATCH] drm/vc4: crtc: Rename HVS channel to output
6 In vc5, the HVS has 6 outputs and 3 FIFOs (or channels), with
7 pixelvalves each being assigned to a given output, but each output can
8 then be muxed to feed from multiple FIFOs.
10 Since vc4 had that entirely static, both were probably equivalent, but
11 since that changes, let's rename hvs_channel to hvs_output in the
12 vc4_crtc_data, since a pixelvalve is really connected to an output, and
15 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
17 drivers/gpu/drm/vc4/vc4_crtc.c | 10 +++++-----
18 drivers/gpu/drm/vc4/vc4_drv.h | 4 ++--
19 2 files changed, 7 insertions(+), 7 deletions(-)
21 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
22 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
23 @@ -1057,7 +1057,7 @@ static const struct drm_crtc_helper_func
26 static const struct vc4_crtc_data bcm2835_pv0_data = {
29 .debugfs_name = "crtc0_regs",
30 .pixels_per_clock = 1,
32 @@ -1067,7 +1067,7 @@ static const struct vc4_crtc_data bcm283
35 static const struct vc4_crtc_data bcm2835_pv1_data = {
38 .debugfs_name = "crtc1_regs",
39 .pixels_per_clock = 1,
41 @@ -1077,7 +1077,7 @@ static const struct vc4_crtc_data bcm283
44 static const struct vc4_crtc_data bcm2835_pv2_data = {
47 .debugfs_name = "crtc2_regs",
48 .pixels_per_clock = 1,
50 @@ -1106,7 +1106,7 @@ static void vc4_set_crtc_possible_masks(
53 /* HVS FIFO2 can feed the TXP IP. */
54 - if (crtc_data->hvs_channel == 2 &&
55 + if (crtc_data->hvs_output == 2 &&
56 encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) {
57 encoder->possible_crtcs |= drm_crtc_mask(crtc);
59 @@ -1168,7 +1168,7 @@ static int vc4_crtc_bind(struct device *
60 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
61 &vc4_crtc_funcs, NULL);
62 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
63 - vc4_crtc->channel = vc4_crtc->data->hvs_channel;
64 + vc4_crtc->channel = vc4_crtc->data->hvs_output;
65 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
66 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
68 --- a/drivers/gpu/drm/vc4/vc4_drv.h
69 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
70 @@ -452,8 +452,8 @@ to_vc4_encoder(struct drm_encoder *encod
73 struct vc4_crtc_data {
74 - /* Which channel of the HVS this pixelvalve sources from. */
76 + /* Which output of the HVS this pixelvalve sources from. */
79 /* Number of pixels output per clock period */