1 From aa43601d97bf9136b657259f44c03a6a30b70d07 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Thu, 26 Dec 2019 11:35:58 +0100
4 Subject: [PATCH] drm/vc4: crtc: Add BCM2711 pixelvalves
6 The BCM2711 has 5 pixelvalves, so now that our driver is ready, let's add
9 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
11 drivers/gpu/drm/vc4/vc4_crtc.c | 82 +++++++++++++++++++++++++++++++++-
12 drivers/gpu/drm/vc4/vc4_regs.h | 6 +++
13 2 files changed, 86 insertions(+), 2 deletions(-)
15 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
16 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
17 @@ -273,6 +273,13 @@ static u32 vc4_get_fifo_full_level(struc
18 case PV_CONTROL_FORMAT_24:
19 case PV_CONTROL_FORMAT_DSIV_24:
22 + * For some reason, the pixelvalve4 doesn't work with
23 + * the usual formula and will only work with 32.
25 + if (vc4_crtc->data->hvs_output == 5)
28 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
31 @@ -281,8 +288,14 @@ static u32 vc4_crtc_get_fifo_full_level_
34 u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
35 - return VC4_SET_FIELD(level & 0x3f,
36 - PV_CONTROL_FIFO_LEVEL);
40 + ret |= VC4_SET_FIELD((level >> 6) & 0x3,
41 + PV5_CONTROL_FIFO_LEVEL_HIGH);
43 + return ret | VC4_SET_FIELD(level & 0x3f,
44 + PV_CONTROL_FIFO_LEVEL);
48 @@ -328,6 +341,9 @@ static void vc4_crtc_config_pv(struct dr
49 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
50 CRTC_WRITE(PV_CONTROL, 0);
52 + CRTC_WRITE(PV_MUX_CFG,
53 + VC4_SET_FIELD(8, PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
56 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
58 @@ -1115,10 +1131,72 @@ static const struct vc4_crtc_data bcm283
62 +static const struct vc4_crtc_data bcm2711_pv0_data = {
63 + .debugfs_name = "crtc0_regs",
64 + .hvs_available_channels = BIT(0),
67 + .pixels_per_clock = 1,
69 + [0] = VC4_ENCODER_TYPE_DSI0,
70 + [1] = VC4_ENCODER_TYPE_DPI,
74 +static const struct vc4_crtc_data bcm2711_pv1_data = {
75 + .debugfs_name = "crtc1_regs",
76 + .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
79 + .pixels_per_clock = 1,
81 + [0] = VC4_ENCODER_TYPE_DSI1,
82 + [1] = VC4_ENCODER_TYPE_SMI,
86 +static const struct vc4_crtc_data bcm2711_pv2_data = {
87 + .debugfs_name = "crtc2_regs",
88 + .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
91 + .pixels_per_clock = 2,
93 + [0] = VC4_ENCODER_TYPE_HDMI0,
97 +static const struct vc4_crtc_data bcm2711_pv3_data = {
98 + .debugfs_name = "crtc3_regs",
99 + .hvs_available_channels = BIT(1),
102 + .pixels_per_clock = 1,
104 + [0] = VC4_ENCODER_TYPE_VEC,
108 +static const struct vc4_crtc_data bcm2711_pv4_data = {
109 + .debugfs_name = "crtc4_regs",
110 + .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
113 + .pixels_per_clock = 2,
115 + [0] = VC4_ENCODER_TYPE_HDMI1,
119 static const struct of_device_id vc4_crtc_dt_match[] = {
120 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
121 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
122 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
123 + { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
124 + { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
125 + { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
126 + { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
127 + { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
131 --- a/drivers/gpu/drm/vc4/vc4_regs.h
132 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
134 #define V3D_ERRSTAT 0x00f20
136 #define PV_CONTROL 0x00
137 +# define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK VC4_MASK(26, 25)
138 +# define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT 25
139 # define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)
140 # define PV_CONTROL_FORMAT_SHIFT 21
141 # define PV_CONTROL_FORMAT_24 0
144 #define PV_HACT_ACT 0x30
146 +#define PV_MUX_CFG 0x34
147 +# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK VC4_MASK(5, 2)
148 +# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT 2
150 #define SCALER_CHANNELS_COUNT 3
152 #define SCALER_DISPCTRL 0x00000000