1 From 661edd663841d94bded4e95acfd0a4947cb079b5 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Wed, 12 Feb 2020 12:26:40 +0100
4 Subject: [PATCH] ARM: dts: bcm2711: Enable the display pipeline
6 Now that all the drivers have been adjusted for it, let's bring in the
7 necessary device tree changes.
9 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
11 arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 40 ++++++++++
12 arch/arm/boot/dts/bcm2711.dtsi | 110 ++++++++++++++++++++++++++
13 2 files changed, 150 insertions(+)
15 --- a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
16 +++ b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
18 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
61 // =============================================
62 // Downstream rpi- changes
64 --- a/arch/arm/boot/dts/bcm2711.dtsi
65 +++ b/arch/arm/boot/dts/bcm2711.dtsi
71 + compatible = "brcm,bcm2711-vc5";
72 + status = "disabled";
75 clk_108MHz: clk-108M {
77 compatible = "fixed-clock";
82 + pixelvalve0: pixelvalve@7e206000 {
83 + compatible = "brcm,bcm2711-pixelvalve0";
84 + reg = <0x7e206000 0x100>;
85 + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
86 + status = "disabled";
89 + pixelvalve1: pixelvalve@7e207000 {
90 + compatible = "brcm,bcm2711-pixelvalve1";
91 + reg = <0x7e207000 0x100>;
92 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
93 + status = "disabled";
96 + pixelvalve2: pixelvalve@7e20a000 {
97 + compatible = "brcm,bcm2711-pixelvalve2";
98 + reg = <0x7e20a000 0x100>;
99 + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
100 + status = "disabled";
104 compatible = "brcm,bcm2835-pwm";
105 reg = <0x7e20c800 0x28>;
110 + pixelvalve4: pixelvalve@7e216000 {
111 + compatible = "brcm,bcm2711-pixelvalve4";
112 + reg = <0x7e216000 0x100>;
113 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
114 + status = "disabled";
117 emmc2: emmc2@7e340000 {
118 compatible = "brcm,bcm2711-emmc2";
119 reg = <0x7e340000 0x100>;
121 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
124 + pixelvalve3: pixelvalve@7ec12000 {
125 + compatible = "brcm,bcm2711-pixelvalve3";
126 + reg = <0x7ec12000 0x100>;
127 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
128 + status = "disabled";
131 dvp: clock@7ef00000 {
132 compatible = "brcm,brcm2711-dvp";
133 reg = <0x7ef00000 0x10>;
139 + hdmi0: hdmi@7ef00700 {
140 + compatible = "brcm,bcm2711-hdmi0";
141 + reg = <0x7ef00700 0x300>,
142 + <0x7ef00300 0x200>,
145 + <0x7ef01b00 0x200>,
146 + <0x7ef01f00 0x400>,
148 + <0x7ef04300 0x100>,
149 + <0x7ef20000 0x100>;
150 + reg-names = "hdmi",
159 + clocks = <&firmware_clocks 13>;
160 + clock-names = "hdmi";
163 + status = "disabled";
166 + ddc0: i2c@7ef04500 {
167 + compatible = "brcm,bcm2711-hdmi-i2c";
168 + reg = <0x7ef04500 0x100>, <0x7ef00b00 0x300>;
169 + reg-names = "bsc", "auto-i2c";
170 + clock-frequency = <390000>;
171 + status = "disabled";
174 + hdmi1: hdmi@7ef05700 {
175 + compatible = "brcm,bcm2711-hdmi1";
176 + reg = <0x7ef05700 0x300>,
177 + <0x7ef05300 0x200>,
180 + <0x7ef06b00 0x200>,
181 + <0x7ef06f00 0x400>,
183 + <0x7ef09300 0x100>,
184 + <0x7ef20000 0x100>;
185 + reg-names = "hdmi",
195 + clocks = <&firmware_clocks 13>;
196 + clock-names = "hdmi";
198 + status = "disabled";
201 + ddc1: i2c@7ef09500 {
202 + compatible = "brcm,bcm2711-hdmi-i2c";
203 + reg = <0x7ef09500 0x100>, <0x7ef05b00 0x300>;
204 + reg-names = "bsc", "auto-i2c";
205 + clock-frequency = <390000>;
206 + status = "disabled";