target/linux/bcm27xx/patches-6.1/950-0115-Add-SMI-driver.patch

   1 From b3077fb9ac2668fde05478fa0ef6197fecda87b6 Mon Sep 17 00:00:00 2001
   2 From: Luke Wren <wren6991@gmail.com>
   3 Date: Sat, 5 Sep 2015 01:14:45 +0100
   4 Subject: [PATCH] Add SMI driver
   5
   6 Signed-off-by: Luke Wren <wren6991@gmail.com>
   7
   8 MISC: bcm2835: smi: use clock manager and fix reload issues
   9
  10 Use clock manager instead of self-made clockmanager.
  11
  12 Also fix some error paths that showd up during development
  13 (especially missing release of dma resources on rmmod)
  14
  15 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  16
  17 bcm2835_smi: re-add dereference to fix DMA transfers
  18
  19 bcm2835_smi_dev: Fix handling of word-odd lengths
  20
  21 The read and write functions did not use the correct pointer offset
  22 when dealing with an odd number of bytes after a DMA transfer. Also,
  23 only handle the remaining odd bytes if the DMA transfer completed
  24 successfully.
  25
  26 Submitted-by: @madimario (GitHub)
  27 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  28
  29 misc: bcm2835_smi: Use proper enum types for dma_{,un}map_single()
  30
  31 Clang warns:
  32
  33   drivers/misc/bcm2835_smi.c:692:4: warning: implicit conversion from enumeration type 'enum dma_transfer_direction' to different enumeration type 'enum dma_data_direction' [-Wenum-conversion]
  34                           DMA_MEM_TO_DEV);
  35                           ^~~~~~~~~~~~~~~
  36   ./include/linux/dma-mapping.h:406:66: note: expanded from macro 'dma_map_single'
  37   #define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, 0)
  38                                      ~~~~~~~~~~~~~~~~~~~~          ^
  39   drivers/misc/bcm2835_smi.c:705:35: warning: implicit conversion from enumeration type 'enum dma_transfer_direction' to different enumeration type 'enum dma_data_direction' [-Wenum-conversion]
  40                           (inst->dev, phy_addr, n_bytes, DMA_MEM_TO_DEV);
  41                           ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~
  42   ./include/linux/dma-mapping.h:407:70: note: expanded from macro 'dma_unmap_single'
  43   #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, 0)
  44                                        ~~~~~~~~~~~~~~~~~~~~~~          ^
  45   drivers/misc/bcm2835_smi.c:751:12: warning: implicit conversion from enumeration type 'enum dma_transfer_direction' to different enumeration type 'enum dma_data_direction' [-Wenum-conversion]
  46                                                        DMA_DEV_TO_MEM);
  47                                                        ^~~~~~~~~~~~~~~
  48   ./include/linux/dma-mapping.h:406:66: note: expanded from macro 'dma_map_single'
  49   #define dma_map_single(d, a, s, r) dma_map_single_attrs(d, a, s, r, 0)
  50                                      ~~~~~~~~~~~~~~~~~~~~          ^
  51   drivers/misc/bcm2835_smi.c:761:50: warning: implicit conversion from enumeration type 'enum dma_transfer_direction' to different enumeration type 'enum dma_data_direction' [-Wenum-conversion]
  52                   dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_DEV_TO_MEM);
  53                   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~
  54   ./include/linux/dma-mapping.h:407:70: note: expanded from macro 'dma_unmap_single'
  55   #define dma_unmap_single(d, a, s, r) dma_unmap_single_attrs(d, a, s, r, 0)
  56                                        ~~~~~~~~~~~~~~~~~~~~~~          ^
  57   4 warnings generated.
  58
  59 Use the proper enumerated type to clear up the warning. There is not
  60 actually a bug here because the enumerated types have the same integer
  61 value:
  62
  63 DMA_MEM_TO_DEV = DMA_TO_DEVICE = 1
  64 DMA_DEV_TO_MEM = DMA_FROM_DEVICE = 2
  65
  66 Fixes: 93254d0f7bc8 ("Add SMI driver")
  67 Signed-off-by: Nathan Chancellor <nathan@kernel.org>
  68 ---
  69  .../bindings/misc/brcm,bcm2835-smi-dev.txt    |  17 +
  70  .../bindings/misc/brcm,bcm2835-smi.txt        |  48 +
  71  drivers/char/broadcom/Kconfig                 |   9 +
  72  drivers/char/broadcom/Makefile                |   1 +
  73  drivers/char/broadcom/bcm2835_smi_dev.c       | 409 ++++++++
  74  drivers/misc/Kconfig                          |   8 +
  75  drivers/misc/Makefile                         |   1 +
  76  drivers/misc/bcm2835_smi.c                    | 955 ++++++++++++++++++
  77  include/linux/broadcom/bcm2835_smi.h          | 391 +++++++
  78  9 files changed, 1839 insertions(+)
  79  create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
  80  create mode 100644 Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
  81  create mode 100644 drivers/char/broadcom/bcm2835_smi_dev.c
  82  create mode 100644 drivers/misc/bcm2835_smi.c
  83  create mode 100644 include/linux/broadcom/bcm2835_smi.h
  84
  85 --- /dev/null
  86 +++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi-dev.txt
  87 @@ -0,0 +1,17 @@
  88 +* Broadcom BCM2835 SMI character device driver.
  89 +
  90 +SMI or secondary memory interface is a peripheral specific to certain Broadcom
  91 +SOCs, and is helpful for talking to things like parallel-interface displays
  92 +and NAND flashes (in fact, most things with a parallel register interface).
  93 +
  94 +This driver adds a character device which provides a user-space interface to
  95 +an instance of the SMI driver.
  96 +
  97 +Required properties:
  98 +- compatible: "brcm,bcm2835-smi-dev"
  99 +- smi_handle: a phandle to the smi node.
 100 +
 101 +Optional properties:
 102 +- None.
 103 +
 104 +
 105 --- /dev/null
 106 +++ b/Documentation/devicetree/bindings/misc/brcm,bcm2835-smi.txt
 107 @@ -0,0 +1,48 @@
 108 +* Broadcom BCM2835 SMI driver.
 109 +
 110 +SMI or secondary memory interface is a peripheral specific to certain Broadcom
 111 +SOCs, and is helpful for talking to things like parallel-interface displays
 112 +and NAND flashes (in fact, most things with a parallel register interface).
 113 +
 114 +Required properties:
 115 +- compatible: "brcm,bcm2835-smi"
 116 +- reg: Should contain location and length of SMI registers and SMI clkman regs
 117 +- interrupts: *the* SMI interrupt.
 118 +- pinctrl-names: should be "default".
 119 +- pinctrl-0: the phandle of the gpio pin node.
 120 +- brcm,smi-clock-source: the clock source for clkman
 121 +- brcm,smi-clock-divisor: the integer clock divisor for clkman
 122 +- dmas: the dma controller phandle and the DREQ number (4 on a 2835)
 123 +- dma-names: the name used by the driver to request its channel.
 124 +  Should be "rx-tx".
 125 +
 126 +Optional properties:
 127 +- None.
 128 +
 129 +Examples:
 130 +
 131 +8 data pin configuration:
 132 +
 133 +smi: smi@7e600000 {
 134 +       compatible = "brcm,bcm2835-smi";
 135 +       reg = <0x7e600000 0x44>, <0x7e1010b0 0x8>;
 136 +       interrupts = <2 16>;
 137 +       pinctrl-names = "default";
 138 +       pinctrl-0 = <&smi_pins>;
 139 +       brcm,smi-clock-source = <6>;
 140 +       brcm,smi-clock-divisor = <4>;
 141 +       dmas = <&dma 4>;
 142 +       dma-names = "rx-tx";
 143 +
 144 +       status = "okay";
 145 +};
 146 +
 147 +smi_pins: smi_pins {
 148 +       brcm,pins = <2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
 149 +       /* Alt 1: SMI */
 150 +       brcm,function = <5 5 5 5 5 5 5 5 5 5 5 5 5 5>;
 151 +       /* /CS, /WE and /OE are pulled high, as they are
 152 +          generally active low signals */
 153 +       brcm,pull = <2 2 2 2 2 2 0 0 0 0 0 0 0 0>;
 154 +};
 155 +
 156 --- a/drivers/char/broadcom/Kconfig
 157 +++ b/drivers/char/broadcom/Kconfig
 158 @@ -24,3 +24,12 @@ config BCM2835_DEVGPIOMEM
 159                 Provides users with root-free access to the GPIO registers
 160                 on the 2835. Calling mmap(/dev/gpiomem) will map the GPIO
 161                 register page to the user's pointer.
 162 +
 163 +config BCM2835_SMI_DEV
 164 +       tristate "Character device driver for BCM2835 Secondary Memory Interface"
 165 +       depends on BCM2835_SMI
 166 +       default m
 167 +       help
 168 +               This driver provides a character device interface (ioctl + read/write) to
 169 +               Broadcom's Secondary Memory interface. The low-level functionality is provided
 170 +               by the SMI driver itself.
 171 --- a/drivers/char/broadcom/Makefile
 172 +++ b/drivers/char/broadcom/Makefile
 173 @@ -1,2 +1,3 @@
 174  obj-$(CONFIG_BCM2708_VCMEM)    += vc_mem.o
 175  obj-$(CONFIG_BCM2835_DEVGPIOMEM)+= bcm2835-gpiomem.o
 176 +obj-$(CONFIG_BCM2835_SMI_DEV)  += bcm2835_smi_dev.o
 177 --- /dev/null
 178 +++ b/drivers/char/broadcom/bcm2835_smi_dev.c
 179 @@ -0,0 +1,409 @@
 180 +/**
 181 + * Character device driver for Broadcom Secondary Memory Interface
 182 + *
 183 + * Written by Luke Wren <luke@raspberrypi.org>
 184 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
 185 + *
 186 + * Redistribution and use in source and binary forms, with or without
 187 + * modification, are permitted provided that the following conditions
 188 + * are met:
 189 + * 1. Redistributions of source code must retain the above copyright
 190 + *    notice, this list of conditions, and the following disclaimer,
 191 + *    without modification.
 192 + * 2. Redistributions in binary form must reproduce the above copyright
 193 + *    notice, this list of conditions and the following disclaimer in the
 194 + *    documentation and/or other materials provided with the distribution.
 195 + * 3. The names of the above-listed copyright holders may not be used
 196 + *    to endorse or promote products derived from this software without
 197 + *    specific prior written permission.
 198 + *
 199 + * ALTERNATIVELY, this software may be distributed under the terms of the
 200 + * GNU General Public License ("GPL") version 2, as published by the Free
 201 + * Software Foundation.
 202 + *
 203 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 204 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 205 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 206 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 207 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 208 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 209 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 210 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 211 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 212 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 213 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 214 + */
 215 +
 216 +#include <linux/kernel.h>
 217 +#include <linux/module.h>
 218 +#include <linux/of.h>
 219 +#include <linux/platform_device.h>
 220 +#include <linux/slab.h>
 221 +#include <linux/mm.h>
 222 +#include <linux/pagemap.h>
 223 +#include <linux/fs.h>
 224 +#include <linux/cdev.h>
 225 +#include <linux/fs.h>
 226 +
 227 +#include <linux/broadcom/bcm2835_smi.h>
 228 +
 229 +#define DEVICE_NAME "bcm2835-smi-dev"
 230 +#define DRIVER_NAME "smi-dev-bcm2835"
 231 +#define DEVICE_MINOR 0
 232 +
 233 +static struct cdev bcm2835_smi_cdev;
 234 +static dev_t bcm2835_smi_devid;
 235 +static struct class *bcm2835_smi_class;
 236 +static struct device *bcm2835_smi_dev;
 237 +
 238 +struct bcm2835_smi_dev_instance {
 239 +       struct device *dev;
 240 +};
 241 +
 242 +static struct bcm2835_smi_instance *smi_inst;
 243 +static struct bcm2835_smi_dev_instance *inst;
 244 +
 245 +static const char *const ioctl_names[] = {
 246 +       "READ_SETTINGS",
 247 +       "WRITE_SETTINGS",
 248 +       "ADDRESS"
 249 +};
 250 +
 251 +/****************************************************************************
 252 +*
 253 +*   SMI chardev file ops
 254 +*
 255 +***************************************************************************/
 256 +static long
 257 +bcm2835_smi_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 258 +{
 259 +       long ret = 0;
 260 +
 261 +       dev_info(inst->dev, "serving ioctl...");
 262 +
 263 +       switch (cmd) {
 264 +       case BCM2835_SMI_IOC_GET_SETTINGS:{
 265 +               struct smi_settings *settings;
 266 +
 267 +               dev_info(inst->dev, "Reading SMI settings to user.");
 268 +               settings = bcm2835_smi_get_settings_from_regs(smi_inst);
 269 +               if (copy_to_user((void *)arg, settings,
 270 +                                sizeof(struct smi_settings)))
 271 +                       dev_err(inst->dev, "settings copy failed.");
 272 +               break;
 273 +       }
 274 +       case BCM2835_SMI_IOC_WRITE_SETTINGS:{
 275 +               struct smi_settings *settings;
 276 +
 277 +               dev_info(inst->dev, "Setting user's SMI settings.");
 278 +               settings = bcm2835_smi_get_settings_from_regs(smi_inst);
 279 +               if (copy_from_user(settings, (void *)arg,
 280 +                                  sizeof(struct smi_settings)))
 281 +                       dev_err(inst->dev, "settings copy failed.");
 282 +               else
 283 +                       bcm2835_smi_set_regs_from_settings(smi_inst);
 284 +               break;
 285 +       }
 286 +       case BCM2835_SMI_IOC_ADDRESS:
 287 +               dev_info(inst->dev, "SMI address set: 0x%02x", (int)arg);
 288 +               bcm2835_smi_set_address(smi_inst, arg);
 289 +               break;
 290 +       default:
 291 +               dev_err(inst->dev, "invalid ioctl cmd: %d", cmd);
 292 +               ret = -ENOTTY;
 293 +               break;
 294 +       }
 295 +
 296 +       return ret;
 297 +}
 298 +
 299 +static int bcm2835_smi_open(struct inode *inode, struct file *file)
 300 +{
 301 +       int dev = iminor(inode);
 302 +
 303 +       dev_dbg(inst->dev, "SMI device opened.");
 304 +
 305 +       if (dev != DEVICE_MINOR) {
 306 +               dev_err(inst->dev,
 307 +                       "bcm2835_smi_release: Unknown minor device: %d",
 308 +                       dev);
 309 +               return -ENXIO;
 310 +       }
 311 +
 312 +       return 0;
 313 +}
 314 +
 315 +static int bcm2835_smi_release(struct inode *inode, struct file *file)
 316 +{
 317 +       int dev = iminor(inode);
 318 +
 319 +       if (dev != DEVICE_MINOR) {
 320 +               dev_err(inst->dev,
 321 +                       "bcm2835_smi_release: Unknown minor device %d", dev);
 322 +               return -ENXIO;
 323 +       }
 324 +
 325 +       return 0;
 326 +}
 327 +
 328 +static ssize_t dma_bounce_user(
 329 +       enum dma_transfer_direction dma_dir,
 330 +       char __user *user_ptr,
 331 +       size_t count,
 332 +       struct bcm2835_smi_bounce_info *bounce)
 333 +{
 334 +       int chunk_size;
 335 +       int chunk_no = 0;
 336 +       int count_left = count;
 337 +
 338 +       while (count_left) {
 339 +               int rv;
 340 +               void *buf;
 341 +
 342 +               /* Wait for current chunk to complete: */
 343 +               if (down_timeout(&bounce->callback_sem,
 344 +                       msecs_to_jiffies(1000))) {
 345 +                       dev_err(inst->dev, "DMA bounce timed out");
 346 +                       count -= (count_left);
 347 +                       break;
 348 +               }
 349 +
 350 +               if (bounce->callback_sem.count >= DMA_BOUNCE_BUFFER_COUNT - 1)
 351 +                       dev_err(inst->dev, "WARNING: Ring buffer overflow");
 352 +               chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
 353 +                       DMA_BOUNCE_BUFFER_SIZE : count_left;
 354 +               buf = bounce->buffer[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
 355 +               if (dma_dir == DMA_DEV_TO_MEM)
 356 +                       rv = copy_to_user(user_ptr, buf, chunk_size);
 357 +               else
 358 +                       rv = copy_from_user(buf, user_ptr, chunk_size);
 359 +               if (rv)
 360 +                       dev_err(inst->dev, "copy_*_user() failed!: %d", rv);
 361 +               user_ptr += chunk_size;
 362 +               count_left -= chunk_size;
 363 +               chunk_no++;
 364 +       }
 365 +       return count;
 366 +}
 367 +
 368 +static ssize_t
 369 +bcm2835_read_file(struct file *f, char __user *user_ptr,
 370 +                 size_t count, loff_t *offs)
 371 +{
 372 +       int odd_bytes;
 373 +       size_t count_check;
 374 +
 375 +       dev_dbg(inst->dev, "User reading %zu bytes from SMI.", count);
 376 +       /* We don't want to DMA a number of bytes % 4 != 0 (32 bit FIFO) */
 377 +       if (count > DMA_THRESHOLD_BYTES)
 378 +               odd_bytes = count & 0x3;
 379 +       else
 380 +               odd_bytes = count;
 381 +       count -= odd_bytes;
 382 +       count_check = count;
 383 +       if (count) {
 384 +               struct bcm2835_smi_bounce_info *bounce;
 385 +
 386 +               count = bcm2835_smi_user_dma(smi_inst,
 387 +                       DMA_DEV_TO_MEM, user_ptr, count,
 388 +                       &bounce);
 389 +               if (count)
 390 +                       count = dma_bounce_user(DMA_DEV_TO_MEM, user_ptr,
 391 +                               count, bounce);
 392 +       }
 393 +       if (odd_bytes && (count == count_check)) {
 394 +               /* Read from FIFO directly if not using DMA */
 395 +               uint8_t buf[DMA_THRESHOLD_BYTES];
 396 +               unsigned long bytes_not_transferred;
 397 +
 398 +               bcm2835_smi_read_buf(smi_inst, buf, odd_bytes);
 399 +               bytes_not_transferred = copy_to_user(user_ptr + count, buf, odd_bytes);
 400 +               if (bytes_not_transferred)
 401 +                       dev_err(inst->dev, "copy_to_user() failed.");
 402 +               count += odd_bytes - bytes_not_transferred;
 403 +       }
 404 +       return count;
 405 +}
 406 +
 407 +static ssize_t
 408 +bcm2835_write_file(struct file *f, const char __user *user_ptr,
 409 +                  size_t count, loff_t *offs)
 410 +{
 411 +       int odd_bytes;
 412 +       size_t count_check;
 413 +
 414 +       dev_dbg(inst->dev, "User writing %zu bytes to SMI.", count);
 415 +       if (count > DMA_THRESHOLD_BYTES)
 416 +               odd_bytes = count & 0x3;
 417 +       else
 418 +               odd_bytes = count;
 419 +       count -= odd_bytes;
 420 +       count_check = count;
 421 +       if (count) {
 422 +               struct bcm2835_smi_bounce_info *bounce;
 423 +
 424 +               count = bcm2835_smi_user_dma(smi_inst,
 425 +                       DMA_MEM_TO_DEV, (char __user *)user_ptr, count,
 426 +                       &bounce);
 427 +               if (count)
 428 +                       count = dma_bounce_user(DMA_MEM_TO_DEV,
 429 +                               (char __user *)user_ptr,
 430 +                               count, bounce);
 431 +       }
 432 +       if (odd_bytes && (count == count_check)) {
 433 +               uint8_t buf[DMA_THRESHOLD_BYTES];
 434 +               unsigned long bytes_not_transferred;
 435 +
 436 +               bytes_not_transferred = copy_from_user(buf, user_ptr + count, odd_bytes);
 437 +               if (bytes_not_transferred)
 438 +                       dev_err(inst->dev, "copy_from_user() failed.");
 439 +               else
 440 +                       bcm2835_smi_write_buf(smi_inst, buf, odd_bytes);
 441 +               count += odd_bytes - bytes_not_transferred;
 442 +       }
 443 +       return count;
 444 +}
 445 +
 446 +static const struct file_operations
 447 +bcm2835_smi_fops = {
 448 +       .owner = THIS_MODULE,
 449 +       .unlocked_ioctl = bcm2835_smi_ioctl,
 450 +       .open = bcm2835_smi_open,
 451 +       .release = bcm2835_smi_release,
 452 +       .read = bcm2835_read_file,
 453 +       .write = bcm2835_write_file,
 454 +};
 455 +
 456 +
 457 +/****************************************************************************
 458 +*
 459 +*   bcm2835_smi_probe - called when the driver is loaded.
 460 +*
 461 +***************************************************************************/
 462 +
 463 +static int bcm2835_smi_dev_probe(struct platform_device *pdev)
 464 +{
 465 +       int err;
 466 +       void *ptr_err;
 467 +       struct device *dev = &pdev->dev;
 468 +       struct device_node *node = dev->of_node, *smi_node;
 469 +
 470 +       if (!node) {
 471 +               dev_err(dev, "No device tree node supplied!");
 472 +               return -EINVAL;
 473 +       }
 474 +
 475 +       smi_node = of_parse_phandle(node, "smi_handle", 0);
 476 +
 477 +       if (!smi_node) {
 478 +               dev_err(dev, "No such property: smi_handle");
 479 +               return -ENXIO;
 480 +       }
 481 +
 482 +       smi_inst = bcm2835_smi_get(smi_node);
 483 +
 484 +       if (!smi_inst)
 485 +               return -EPROBE_DEFER;
 486 +
 487 +       /* Allocate buffers and instance data */
 488 +
 489 +       inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
 490 +
 491 +       if (!inst)
 492 +               return -ENOMEM;
 493 +
 494 +       inst->dev = dev;
 495 +
 496 +       /* Create character device entries */
 497 +
 498 +       err = alloc_chrdev_region(&bcm2835_smi_devid,
 499 +                                 DEVICE_MINOR, 1, DEVICE_NAME);
 500 +       if (err != 0) {
 501 +               dev_err(inst->dev, "unable to allocate device number");
 502 +               return -ENOMEM;
 503 +       }
 504 +       cdev_init(&bcm2835_smi_cdev, &bcm2835_smi_fops);
 505 +       bcm2835_smi_cdev.owner = THIS_MODULE;
 506 +       err = cdev_add(&bcm2835_smi_cdev, bcm2835_smi_devid, 1);
 507 +       if (err != 0) {
 508 +               dev_err(inst->dev, "unable to register device");
 509 +               err = -ENOMEM;
 510 +               goto failed_cdev_add;
 511 +       }
 512 +
 513 +       /* Create sysfs entries */
 514 +
 515 +       bcm2835_smi_class = class_create(THIS_MODULE, DEVICE_NAME);
 516 +       ptr_err = bcm2835_smi_class;
 517 +       if (IS_ERR(ptr_err))
 518 +               goto failed_class_create;
 519 +
 520 +       bcm2835_smi_dev = device_create(bcm2835_smi_class, NULL,
 521 +                                       bcm2835_smi_devid, NULL,
 522 +                                       "smi");
 523 +       ptr_err = bcm2835_smi_dev;
 524 +       if (IS_ERR(ptr_err))
 525 +               goto failed_device_create;
 526 +
 527 +       dev_info(inst->dev, "initialised");
 528 +
 529 +       return 0;
 530 +
 531 +failed_device_create:
 532 +       class_destroy(bcm2835_smi_class);
 533 +failed_class_create:
 534 +       cdev_del(&bcm2835_smi_cdev);
 535 +       err = PTR_ERR(ptr_err);
 536 +failed_cdev_add:
 537 +       unregister_chrdev_region(bcm2835_smi_devid, 1);
 538 +       dev_err(dev, "could not load bcm2835_smi_dev");
 539 +       return err;
 540 +}
 541 +
 542 +/****************************************************************************
 543 +*
 544 +*   bcm2835_smi_remove - called when the driver is unloaded.
 545 +*
 546 +***************************************************************************/
 547 +
 548 +static int bcm2835_smi_dev_remove(struct platform_device *pdev)
 549 +{
 550 +       device_destroy(bcm2835_smi_class, bcm2835_smi_devid);
 551 +       class_destroy(bcm2835_smi_class);
 552 +       cdev_del(&bcm2835_smi_cdev);
 553 +       unregister_chrdev_region(bcm2835_smi_devid, 1);
 554 +
 555 +       dev_info(inst->dev, "SMI character dev removed - OK");
 556 +       return 0;
 557 +}
 558 +
 559 +/****************************************************************************
 560 +*
 561 +*   Register the driver with device tree
 562 +*
 563 +***************************************************************************/
 564 +
 565 +static const struct of_device_id bcm2835_smi_dev_of_match[] = {
 566 +       {.compatible = "brcm,bcm2835-smi-dev",},
 567 +       { /* sentinel */ },
 568 +};
 569 +
 570 +MODULE_DEVICE_TABLE(of, bcm2835_smi_dev_of_match);
 571 +
 572 +static struct platform_driver bcm2835_smi_dev_driver = {
 573 +       .probe = bcm2835_smi_dev_probe,
 574 +       .remove = bcm2835_smi_dev_remove,
 575 +       .driver = {
 576 +                  .name = DRIVER_NAME,
 577 +                  .owner = THIS_MODULE,
 578 +                  .of_match_table = bcm2835_smi_dev_of_match,
 579 +                  },
 580 +};
 581 +
 582 +module_platform_driver(bcm2835_smi_dev_driver);
 583 +
 584 +MODULE_ALIAS("platform:smi-dev-bcm2835");
 585 +MODULE_LICENSE("GPL");
 586 +MODULE_DESCRIPTION(
 587 +       "Character device driver for BCM2835's secondary memory interface");
 588 +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
 589 --- a/drivers/misc/Kconfig
 590 +++ b/drivers/misc/Kconfig
 591 @@ -9,6 +9,14 @@ config SENSORS_LIS3LV02D
 592         tristate
 593         depends on INPUT
 594
 595 +config BCM2835_SMI
 596 +       tristate "Broadcom 283x Secondary Memory Interface driver"
 597 +       depends on ARCH_BCM2835
 598 +       default m
 599 +       help
 600 +               Driver for enabling and using Broadcom's Secondary/Slow Memory Interface.
 601 +               Appears as /dev/bcm2835_smi. For ioctl interface see drivers/misc/bcm2835_smi.h
 602 +
 603  config AD525X_DPOT
 604         tristate "Analog Devices Digital Potentiometers"
 605         depends on (I2C || SPI) && SYSFS
 606 --- a/drivers/misc/Makefile
 607 +++ b/drivers/misc/Makefile
 608 @@ -9,6 +9,7 @@ obj-$(CONFIG_AD525X_DPOT)       += ad525x_dpot
 609  obj-$(CONFIG_AD525X_DPOT_I2C)  += ad525x_dpot-i2c.o
 610  obj-$(CONFIG_AD525X_DPOT_SPI)  += ad525x_dpot-spi.o
 611  obj-$(CONFIG_ATMEL_SSC)                += atmel-ssc.o
 612 +obj-$(CONFIG_BCM2835_SMI)      += bcm2835_smi.o
 613  obj-$(CONFIG_DUMMY_IRQ)                += dummy-irq.o
 614  obj-$(CONFIG_ICS932S401)       += ics932s401.o
 615  obj-$(CONFIG_LKDTM)            += lkdtm/
 616 --- /dev/null
 617 +++ b/drivers/misc/bcm2835_smi.c
 618 @@ -0,0 +1,955 @@
 619 +/**
 620 + * Broadcom Secondary Memory Interface driver
 621 + *
 622 + * Written by Luke Wren <luke@raspberrypi.org>
 623 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
 624 + *
 625 + * Redistribution and use in source and binary forms, with or without
 626 + * modification, are permitted provided that the following conditions
 627 + * are met:
 628 + * 1. Redistributions of source code must retain the above copyright
 629 + *    notice, this list of conditions, and the following disclaimer,
 630 + *    without modification.
 631 + * 2. Redistributions in binary form must reproduce the above copyright
 632 + *    notice, this list of conditions and the following disclaimer in the
 633 + *    documentation and/or other materials provided with the distribution.
 634 + * 3. The names of the above-listed copyright holders may not be used
 635 + *    to endorse or promote products derived from this software without
 636 + *    specific prior written permission.
 637 + *
 638 + * ALTERNATIVELY, this software may be distributed under the terms of the
 639 + * GNU General Public License ("GPL") version 2, as published by the Free
 640 + * Software Foundation.
 641 + *
 642 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
 643 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
 644 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 645 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 646 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 647 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 648 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 649 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 650 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 651 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 652 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 653 + */
 654 +
 655 +#include <linux/clk.h>
 656 +#include <linux/kernel.h>
 657 +#include <linux/module.h>
 658 +#include <linux/of.h>
 659 +#include <linux/platform_device.h>
 660 +#include <linux/of_address.h>
 661 +#include <linux/of_platform.h>
 662 +#include <linux/mm.h>
 663 +#include <linux/slab.h>
 664 +#include <linux/pagemap.h>
 665 +#include <linux/dma-mapping.h>
 666 +#include <linux/dmaengine.h>
 667 +#include <linux/semaphore.h>
 668 +#include <linux/spinlock.h>
 669 +#include <linux/io.h>
 670 +
 671 +#define BCM2835_SMI_IMPLEMENTATION
 672 +#include <linux/broadcom/bcm2835_smi.h>
 673 +
 674 +#define DRIVER_NAME "smi-bcm2835"
 675 +
 676 +#define N_PAGES_FROM_BYTES(n) ((n + PAGE_SIZE-1) / PAGE_SIZE)
 677 +
 678 +#define DMA_WRITE_TO_MEM true
 679 +#define DMA_READ_FROM_MEM false
 680 +
 681 +struct bcm2835_smi_instance {
 682 +       struct device *dev;
 683 +       struct smi_settings settings;
 684 +       __iomem void *smi_regs_ptr;
 685 +       dma_addr_t smi_regs_busaddr;
 686 +
 687 +       struct dma_chan *dma_chan;
 688 +       struct dma_slave_config dma_config;
 689 +
 690 +       struct bcm2835_smi_bounce_info bounce;
 691 +
 692 +       struct scatterlist buffer_sgl;
 693 +
 694 +       struct clk *clk;
 695 +
 696 +       /* Sometimes we are called into in an atomic context (e.g. by
 697 +          JFFS2 + MTD) so we can't use a mutex */
 698 +       spinlock_t transaction_lock;
 699 +};
 700 +
 701 +/****************************************************************************
 702 +*
 703 +*   SMI peripheral setup
 704 +*
 705 +***************************************************************************/
 706 +
 707 +static inline void write_smi_reg(struct bcm2835_smi_instance *inst,
 708 +       u32 val, unsigned reg)
 709 +{
 710 +       writel(val, inst->smi_regs_ptr + reg);
 711 +}
 712 +
 713 +static inline u32 read_smi_reg(struct bcm2835_smi_instance *inst, unsigned reg)
 714 +{
 715 +       return readl(inst->smi_regs_ptr + reg);
 716 +}
 717 +
 718 +/* Token-paste macro for e.g SMIDSR_RSTROBE ->  value of SMIDSR_RSTROBE_MASK */
 719 +#define _CONCAT(x, y) x##y
 720 +#define CONCAT(x, y) _CONCAT(x, y)
 721 +
 722 +#define SET_BIT_FIELD(dest, field, bits) ((dest) = \
 723 +       ((dest) & ~CONCAT(field, _MASK)) | (((bits) << CONCAT(field, _OFFS))& \
 724 +        CONCAT(field, _MASK)))
 725 +#define GET_BIT_FIELD(src, field) (((src) & \
 726 +       CONCAT(field, _MASK)) >> CONCAT(field, _OFFS))
 727 +
 728 +static void smi_dump_context_labelled(struct bcm2835_smi_instance *inst,
 729 +       const char *label)
 730 +{
 731 +       dev_err(inst->dev, "SMI context dump: %s", label);
 732 +       dev_err(inst->dev, "SMICS:  0x%08x", read_smi_reg(inst, SMICS));
 733 +       dev_err(inst->dev, "SMIL:   0x%08x", read_smi_reg(inst, SMIL));
 734 +       dev_err(inst->dev, "SMIDSR: 0x%08x", read_smi_reg(inst, SMIDSR0));
 735 +       dev_err(inst->dev, "SMIDSW: 0x%08x", read_smi_reg(inst, SMIDSW0));
 736 +       dev_err(inst->dev, "SMIDC:  0x%08x", read_smi_reg(inst, SMIDC));
 737 +       dev_err(inst->dev, "SMIFD:  0x%08x", read_smi_reg(inst, SMIFD));
 738 +       dev_err(inst->dev, " ");
 739 +}
 740 +
 741 +static inline void smi_dump_context(struct bcm2835_smi_instance *inst)
 742 +{
 743 +       smi_dump_context_labelled(inst, "");
 744 +}
 745 +
 746 +static void smi_get_default_settings(struct bcm2835_smi_instance *inst)
 747 +{
 748 +       struct smi_settings *settings = &inst->settings;
 749 +
 750 +       settings->data_width = SMI_WIDTH_16BIT;
 751 +       settings->pack_data = true;
 752 +
 753 +       settings->read_setup_time = 1;
 754 +       settings->read_hold_time = 1;
 755 +       settings->read_pace_time = 1;
 756 +       settings->read_strobe_time = 3;
 757 +
 758 +       settings->write_setup_time = settings->read_setup_time;
 759 +       settings->write_hold_time = settings->read_hold_time;
 760 +       settings->write_pace_time = settings->read_pace_time;
 761 +       settings->write_strobe_time = settings->read_strobe_time;
 762 +
 763 +       settings->dma_enable = true;
 764 +       settings->dma_passthrough_enable = false;
 765 +       settings->dma_read_thresh = 0x01;
 766 +       settings->dma_write_thresh = 0x3f;
 767 +       settings->dma_panic_read_thresh = 0x20;
 768 +       settings->dma_panic_write_thresh = 0x20;
 769 +}
 770 +
 771 +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *inst)
 772 +{
 773 +       struct smi_settings *settings = &inst->settings;
 774 +       int smidsr_temp = 0, smidsw_temp = 0, smics_temp,
 775 +           smidcs_temp, smidc_temp = 0;
 776 +
 777 +       spin_lock(&inst->transaction_lock);
 778 +
 779 +       /* temporarily disable the peripheral: */
 780 +       smics_temp = read_smi_reg(inst, SMICS);
 781 +       write_smi_reg(inst, 0, SMICS);
 782 +       smidcs_temp = read_smi_reg(inst, SMIDCS);
 783 +       write_smi_reg(inst, 0, SMIDCS);
 784 +
 785 +       if (settings->pack_data)
 786 +               smics_temp |= SMICS_PXLDAT;
 787 +       else
 788 +               smics_temp &= ~SMICS_PXLDAT;
 789 +
 790 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RWIDTH, settings->data_width);
 791 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RSETUP, settings->read_setup_time);
 792 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RHOLD, settings->read_hold_time);
 793 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RPACE, settings->read_pace_time);
 794 +       SET_BIT_FIELD(smidsr_temp, SMIDSR_RSTROBE, settings->read_strobe_time);
 795 +       write_smi_reg(inst, smidsr_temp, SMIDSR0);
 796 +
 797 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WWIDTH, settings->data_width);
 798 +       if (settings->data_width == SMI_WIDTH_8BIT)
 799 +               smidsw_temp |= SMIDSW_WSWAP;
 800 +       else
 801 +               smidsw_temp &= ~SMIDSW_WSWAP;
 802 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WSETUP, settings->write_setup_time);
 803 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WHOLD, settings->write_hold_time);
 804 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WPACE, settings->write_pace_time);
 805 +       SET_BIT_FIELD(smidsw_temp, SMIDSW_WSTROBE,
 806 +                       settings->write_strobe_time);
 807 +       write_smi_reg(inst, smidsw_temp, SMIDSW0);
 808 +
 809 +       SET_BIT_FIELD(smidc_temp, SMIDC_REQR, settings->dma_read_thresh);
 810 +       SET_BIT_FIELD(smidc_temp, SMIDC_REQW, settings->dma_write_thresh);
 811 +       SET_BIT_FIELD(smidc_temp, SMIDC_PANICR,
 812 +                     settings->dma_panic_read_thresh);
 813 +       SET_BIT_FIELD(smidc_temp, SMIDC_PANICW,
 814 +                     settings->dma_panic_write_thresh);
 815 +       if (settings->dma_passthrough_enable) {
 816 +               smidc_temp |= SMIDC_DMAP;
 817 +               smidsr_temp |= SMIDSR_RDREQ;
 818 +               write_smi_reg(inst, smidsr_temp, SMIDSR0);
 819 +               smidsw_temp |= SMIDSW_WDREQ;
 820 +               write_smi_reg(inst, smidsw_temp, SMIDSW0);
 821 +       } else
 822 +               smidc_temp &= ~SMIDC_DMAP;
 823 +       if (settings->dma_enable)
 824 +               smidc_temp |= SMIDC_DMAEN;
 825 +       else
 826 +               smidc_temp &= ~SMIDC_DMAEN;
 827 +
 828 +       write_smi_reg(inst, smidc_temp, SMIDC);
 829 +
 830 +       /* re-enable (if was previously enabled) */
 831 +       write_smi_reg(inst, smics_temp, SMICS);
 832 +       write_smi_reg(inst, smidcs_temp, SMIDCS);
 833 +
 834 +       spin_unlock(&inst->transaction_lock);
 835 +}
 836 +EXPORT_SYMBOL(bcm2835_smi_set_regs_from_settings);
 837 +
 838 +struct smi_settings *bcm2835_smi_get_settings_from_regs
 839 +       (struct bcm2835_smi_instance *inst)
 840 +{
 841 +       struct smi_settings *settings = &inst->settings;
 842 +       int smidsr, smidsw, smidc;
 843 +
 844 +       spin_lock(&inst->transaction_lock);
 845 +
 846 +       smidsr = read_smi_reg(inst, SMIDSR0);
 847 +       smidsw = read_smi_reg(inst, SMIDSW0);
 848 +       smidc = read_smi_reg(inst, SMIDC);
 849 +
 850 +       settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ?
 851 +           true : false;
 852 +
 853 +       settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH);
 854 +       settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP);
 855 +       settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD);
 856 +       settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE);
 857 +       settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE);
 858 +
 859 +       settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP);
 860 +       settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD);
 861 +       settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE);
 862 +       settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE);
 863 +
 864 +       settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR);
 865 +       settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW);
 866 +       settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR);
 867 +       settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW);
 868 +       settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false;
 869 +       settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false;
 870 +
 871 +       spin_unlock(&inst->transaction_lock);
 872 +
 873 +       return settings;
 874 +}
 875 +EXPORT_SYMBOL(bcm2835_smi_get_settings_from_regs);
 876 +
 877 +static inline void smi_set_address(struct bcm2835_smi_instance *inst,
 878 +       unsigned int address)
 879 +{
 880 +       int smia_temp = 0, smida_temp = 0;
 881 +
 882 +       SET_BIT_FIELD(smia_temp, SMIA_ADDR, address);
 883 +       SET_BIT_FIELD(smida_temp, SMIDA_ADDR, address);
 884 +
 885 +       /* Write to both address registers - user doesn't care whether we're
 886 +          doing programmed or direct transfers. */
 887 +       write_smi_reg(inst, smia_temp, SMIA);
 888 +       write_smi_reg(inst, smida_temp, SMIDA);
 889 +}
 890 +
 891 +static void smi_setup_regs(struct bcm2835_smi_instance *inst)
 892 +{
 893 +
 894 +       dev_dbg(inst->dev, "Initialising SMI registers...");
 895 +       /* Disable the peripheral if already enabled */
 896 +       write_smi_reg(inst, 0, SMICS);
 897 +       write_smi_reg(inst, 0, SMIDCS);
 898 +
 899 +       smi_get_default_settings(inst);
 900 +       bcm2835_smi_set_regs_from_settings(inst);
 901 +       smi_set_address(inst, 0);
 902 +
 903 +       write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ENABLE, SMICS);
 904 +       write_smi_reg(inst, read_smi_reg(inst, SMIDCS) | SMIDCS_ENABLE,
 905 +               SMIDCS);
 906 +}
 907 +
 908 +/****************************************************************************
 909 +*
 910 +*   Low-level SMI access functions
 911 +*   Other modules should use the exported higher-level functions e.g.
 912 +*   bcm2835_smi_write_buf() unless they have a good reason to use these
 913 +*
 914 +***************************************************************************/
 915 +
 916 +static inline uint32_t smi_read_single_word(struct bcm2835_smi_instance *inst)
 917 +{
 918 +       int timeout = 0;
 919 +
 920 +       write_smi_reg(inst, SMIDCS_ENABLE, SMIDCS);
 921 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_START, SMIDCS);
 922 +       /* Make sure things happen in the right order...*/
 923 +       mb();
 924 +       while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
 925 +               ++timeout < 10000)
 926 +               ;
 927 +       if (timeout < 10000)
 928 +               return read_smi_reg(inst, SMIDD);
 929 +
 930 +       dev_err(inst->dev,
 931 +               "SMI direct read timed out (is the clock set up correctly?)");
 932 +       return 0;
 933 +}
 934 +
 935 +static inline void smi_write_single_word(struct bcm2835_smi_instance *inst,
 936 +       uint32_t data)
 937 +{
 938 +       int timeout = 0;
 939 +
 940 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE, SMIDCS);
 941 +       write_smi_reg(inst, data, SMIDD);
 942 +       write_smi_reg(inst, SMIDCS_ENABLE | SMIDCS_WRITE | SMIDCS_START,
 943 +               SMIDCS);
 944 +
 945 +       while (!(read_smi_reg(inst, SMIDCS) & SMIDCS_DONE) &&
 946 +               ++timeout < 10000)
 947 +               ;
 948 +       if (timeout >= 10000)
 949 +               dev_err(inst->dev,
 950 +               "SMI direct write timed out (is the clock set up correctly?)");
 951 +}
 952 +
 953 +/* Initiates a programmed read into the read FIFO. It is up to the caller to
 954 + * read data from the FIFO -  either via paced DMA transfer,
 955 + * or polling SMICS_RXD to check whether data is available.
 956 + * SMICS_ACTIVE will go low upon completion. */
 957 +static void smi_init_programmed_read(struct bcm2835_smi_instance *inst,
 958 +       int num_transfers)
 959 +{
 960 +       int smics_temp;
 961 +
 962 +       /* Disable the peripheral: */
 963 +       smics_temp = read_smi_reg(inst, SMICS) & ~(SMICS_ENABLE | SMICS_WRITE);
 964 +       write_smi_reg(inst, smics_temp, SMICS);
 965 +       while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
 966 +               ;
 967 +
 968 +       /* Program the transfer count: */
 969 +       write_smi_reg(inst, num_transfers, SMIL);
 970 +
 971 +       /* re-enable and start: */
 972 +       smics_temp |= SMICS_ENABLE;
 973 +       write_smi_reg(inst, smics_temp, SMICS);
 974 +       smics_temp |= SMICS_CLEAR;
 975 +       /* Just to be certain: */
 976 +       mb();
 977 +       while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
 978 +               ;
 979 +       write_smi_reg(inst, smics_temp, SMICS);
 980 +       smics_temp |= SMICS_START;
 981 +       write_smi_reg(inst, smics_temp, SMICS);
 982 +}
 983 +
 984 +/* Initiates a programmed write sequence, using data from the write FIFO.
 985 + * It is up to the caller to initiate a DMA transfer before calling,
 986 + * or use another method to keep the write FIFO topped up.
 987 + * SMICS_ACTIVE will go low upon completion.
 988 + */
 989 +static void smi_init_programmed_write(struct bcm2835_smi_instance *inst,
 990 +       int num_transfers)
 991 +{
 992 +       int smics_temp;
 993 +
 994 +       /* Disable the peripheral: */
 995 +       smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
 996 +       write_smi_reg(inst, smics_temp, SMICS);
 997 +       while (read_smi_reg(inst, SMICS) & SMICS_ENABLE)
 998 +               ;
 999 +
1000 +       /* Program the transfer count: */
1001 +       write_smi_reg(inst, num_transfers, SMIL);
1002 +
1003 +       /* setup, re-enable and start: */
1004 +       smics_temp |= SMICS_WRITE | SMICS_ENABLE;
1005 +       write_smi_reg(inst, smics_temp, SMICS);
1006 +       smics_temp |= SMICS_START;
1007 +       write_smi_reg(inst, smics_temp, SMICS);
1008 +}
1009 +
1010 +/* Initiate a read and then poll FIFO for data, reading out as it appears. */
1011 +static void smi_read_fifo(struct bcm2835_smi_instance *inst,
1012 +       uint32_t *dest, int n_bytes)
1013 +{
1014 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
1015 +               smi_dump_context_labelled(inst,
1016 +                       "WARNING: read FIFO not empty at start of read call.");
1017 +               while (read_smi_reg(inst, SMICS))
1018 +                       ;
1019 +       }
1020 +
1021 +       /* Dispatch the read: */
1022 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1023 +               smi_init_programmed_read(inst, n_bytes);
1024 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
1025 +               smi_init_programmed_read(inst, n_bytes / 2);
1026 +       else {
1027 +               dev_err(inst->dev, "Unsupported data width for read.");
1028 +               return;
1029 +       }
1030 +
1031 +       /* Poll FIFO to keep it empty */
1032 +       while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
1033 +               if (read_smi_reg(inst, SMICS) & SMICS_RXD)
1034 +                       *dest++ = read_smi_reg(inst, SMID);
1035 +
1036 +       /* Ensure that the FIFO is emptied */
1037 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD) {
1038 +               int fifo_count;
1039 +
1040 +               fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD),
1041 +                       SMIFD_FCNT);
1042 +               while (fifo_count--)
1043 +                       *dest++ = read_smi_reg(inst, SMID);
1044 +       }
1045 +
1046 +       if (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
1047 +               smi_dump_context_labelled(inst,
1048 +                       "WARNING: transaction finished but done bit not set.");
1049 +
1050 +       if (read_smi_reg(inst, SMICS) & SMICS_RXD)
1051 +               smi_dump_context_labelled(inst,
1052 +                       "WARNING: read FIFO not empty at end of read call.");
1053 +
1054 +}
1055 +
1056 +/* Initiate a write, and then keep the FIFO topped up. */
1057 +static void smi_write_fifo(struct bcm2835_smi_instance *inst,
1058 +       uint32_t *src, int n_bytes)
1059 +{
1060 +       int i, timeout = 0;
1061 +
1062 +       /* Empty FIFOs if not already so */
1063 +       if (!(read_smi_reg(inst, SMICS) & SMICS_TXE)) {
1064 +               smi_dump_context_labelled(inst,
1065 +                   "WARNING: write fifo not empty at start of write call.");
1066 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_CLEAR,
1067 +                       SMICS);
1068 +       }
1069 +
1070 +       /* Initiate the transfer */
1071 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1072 +               smi_init_programmed_write(inst, n_bytes);
1073 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
1074 +               smi_init_programmed_write(inst, n_bytes / 2);
1075 +       else {
1076 +               dev_err(inst->dev, "Unsupported data width for write.");
1077 +               return;
1078 +       }
1079 +       /* Fill the FIFO: */
1080 +       for (i = 0; i < (n_bytes - 1) / 4 + 1; ++i) {
1081 +               while (!(read_smi_reg(inst, SMICS) & SMICS_TXD))
1082 +                       ;
1083 +               write_smi_reg(inst, *src++, SMID);
1084 +       }
1085 +       /* Busy wait... */
1086 +       while (!(read_smi_reg(inst, SMICS) & SMICS_DONE) && ++timeout <
1087 +               1000000)
1088 +               ;
1089 +       if (timeout >= 1000000)
1090 +               smi_dump_context_labelled(inst,
1091 +                       "Timed out on write operation!");
1092 +       if (!(read_smi_reg(inst, SMICS) & SMICS_TXE))
1093 +               smi_dump_context_labelled(inst,
1094 +                       "WARNING: FIFO not empty at end of write operation.");
1095 +}
1096 +
1097 +/****************************************************************************
1098 +*
1099 +*   SMI DMA operations
1100 +*
1101 +***************************************************************************/
1102 +
1103 +/* Disable SMI and put it into the correct direction before doing DMA setup.
1104 +   Stops spurious DREQs during setup. Peripheral is re-enabled by init_*() */
1105 +static void smi_disable(struct bcm2835_smi_instance *inst,
1106 +       enum dma_transfer_direction direction)
1107 +{
1108 +       int smics_temp = read_smi_reg(inst, SMICS) & ~SMICS_ENABLE;
1109 +
1110 +       if (direction == DMA_DEV_TO_MEM)
1111 +               smics_temp &= ~SMICS_WRITE;
1112 +       else
1113 +               smics_temp |= SMICS_WRITE;
1114 +       write_smi_reg(inst, smics_temp, SMICS);
1115 +       while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
1116 +               ;
1117 +}
1118 +
1119 +static struct scatterlist *smi_scatterlist_from_buffer(
1120 +       struct bcm2835_smi_instance *inst,
1121 +       dma_addr_t buf,
1122 +       size_t len,
1123 +       struct scatterlist *sg)
1124 +{
1125 +       sg_init_table(sg, 1);
1126 +       sg_dma_address(sg) = buf;
1127 +       sg_dma_len(sg) = len;
1128 +       return sg;
1129 +}
1130 +
1131 +static void smi_dma_callback_user_copy(void *param)
1132 +{
1133 +       /* Notify the bottom half that a chunk is ready for user copy */
1134 +       struct bcm2835_smi_instance *inst =
1135 +               (struct bcm2835_smi_instance *)param;
1136 +
1137 +       up(&inst->bounce.callback_sem);
1138 +}
1139 +
1140 +/* Creates a descriptor, assigns the given callback, and submits the
1141 +   descriptor to dmaengine. Does not block - can queue up multiple
1142 +   descriptors and then wait for them all to complete.
1143 +   sg_len is the number of control blocks, NOT the number of bytes.
1144 +   dir can be DMA_MEM_TO_DEV or DMA_DEV_TO_MEM.
1145 +   callback can be NULL - in this case it is not called. */
1146 +static inline struct dma_async_tx_descriptor *smi_dma_submit_sgl(
1147 +       struct bcm2835_smi_instance *inst,
1148 +       struct scatterlist *sgl,
1149 +       size_t sg_len,
1150 +       enum dma_transfer_direction dir,
1151 +       dma_async_tx_callback callback)
1152 +{
1153 +       struct dma_async_tx_descriptor *desc;
1154 +
1155 +       desc = dmaengine_prep_slave_sg(inst->dma_chan,
1156 +                                      sgl,
1157 +                                      sg_len,
1158 +                                      dir,
1159 +                                      DMA_PREP_INTERRUPT | DMA_CTRL_ACK |
1160 +                                      DMA_PREP_FENCE);
1161 +       if (!desc) {
1162 +               dev_err(inst->dev, "read_sgl: dma slave preparation failed!");
1163 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) & ~SMICS_ACTIVE,
1164 +                       SMICS);
1165 +               while (read_smi_reg(inst, SMICS) & SMICS_ACTIVE)
1166 +                       cpu_relax();
1167 +               write_smi_reg(inst, read_smi_reg(inst, SMICS) | SMICS_ACTIVE,
1168 +                       SMICS);
1169 +               return NULL;
1170 +       }
1171 +       desc->callback = callback;
1172 +       desc->callback_param = inst;
1173 +       if (dmaengine_submit(desc) < 0)
1174 +               return NULL;
1175 +       return desc;
1176 +}
1177 +
1178 +/* NB this function blocks until the transfer is complete */
1179 +static void
1180 +smi_dma_read_sgl(struct bcm2835_smi_instance *inst,
1181 +       struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
1182 +{
1183 +       struct dma_async_tx_descriptor *desc;
1184 +
1185 +       /* Disable SMI and set to read before dispatching DMA - if SMI is in
1186 +        * write mode and TX fifo is empty, it will generate a DREQ which may
1187 +        * cause the read DMA to complete before the SMI read command is even
1188 +        * dispatched! We want to dispatch DMA before SMI read so that reading
1189 +        * is gapless, for logic analyser.
1190 +        */
1191 +
1192 +       smi_disable(inst, DMA_DEV_TO_MEM);
1193 +
1194 +       desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_DEV_TO_MEM, NULL);
1195 +       dma_async_issue_pending(inst->dma_chan);
1196 +
1197 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1198 +               smi_init_programmed_read(inst, n_bytes);
1199 +       else
1200 +               smi_init_programmed_read(inst, n_bytes / 2);
1201 +
1202 +       if (dma_wait_for_async_tx(desc) == DMA_ERROR)
1203 +               smi_dump_context_labelled(inst, "DMA timeout!");
1204 +}
1205 +
1206 +static void
1207 +smi_dma_write_sgl(struct bcm2835_smi_instance *inst,
1208 +       struct scatterlist *sgl, size_t sg_len, size_t n_bytes)
1209 +{
1210 +       struct dma_async_tx_descriptor *desc;
1211 +
1212 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1213 +               smi_init_programmed_write(inst, n_bytes);
1214 +       else
1215 +               smi_init_programmed_write(inst, n_bytes / 2);
1216 +
1217 +       desc = smi_dma_submit_sgl(inst, sgl, sg_len, DMA_MEM_TO_DEV, NULL);
1218 +       dma_async_issue_pending(inst->dma_chan);
1219 +
1220 +       if (dma_wait_for_async_tx(desc) == DMA_ERROR)
1221 +               smi_dump_context_labelled(inst, "DMA timeout!");
1222 +       else
1223 +               /* Wait for SMI to finish our writes */
1224 +               while (!(read_smi_reg(inst, SMICS) & SMICS_DONE))
1225 +                       cpu_relax();
1226 +}
1227 +
1228 +ssize_t bcm2835_smi_user_dma(
1229 +       struct bcm2835_smi_instance *inst,
1230 +       enum dma_transfer_direction dma_dir,
1231 +       char __user *user_ptr, size_t count,
1232 +       struct bcm2835_smi_bounce_info **bounce)
1233 +{
1234 +       int chunk_no = 0, chunk_size, count_left = count;
1235 +       struct scatterlist *sgl;
1236 +       void (*init_trans_func)(struct bcm2835_smi_instance *, int);
1237 +
1238 +       spin_lock(&inst->transaction_lock);
1239 +
1240 +       if (dma_dir == DMA_DEV_TO_MEM)
1241 +               init_trans_func = smi_init_programmed_read;
1242 +       else
1243 +               init_trans_func = smi_init_programmed_write;
1244 +
1245 +       smi_disable(inst, dma_dir);
1246 +
1247 +       sema_init(&inst->bounce.callback_sem, 0);
1248 +       if (bounce)
1249 +               *bounce = &inst->bounce;
1250 +       while (count_left) {
1251 +               chunk_size = count_left > DMA_BOUNCE_BUFFER_SIZE ?
1252 +                       DMA_BOUNCE_BUFFER_SIZE : count_left;
1253 +               if (chunk_size == DMA_BOUNCE_BUFFER_SIZE) {
1254 +                       sgl =
1255 +                       &inst->bounce.sgl[chunk_no % DMA_BOUNCE_BUFFER_COUNT];
1256 +               } else {
1257 +                       sgl = smi_scatterlist_from_buffer(
1258 +                               inst,
1259 +                               inst->bounce.phys[
1260 +                                       chunk_no % DMA_BOUNCE_BUFFER_COUNT],
1261 +                               chunk_size,
1262 +                               &inst->buffer_sgl);
1263 +               }
1264 +
1265 +               if (!smi_dma_submit_sgl(inst, sgl, 1, dma_dir,
1266 +                       smi_dma_callback_user_copy
1267 +               )) {
1268 +                       dev_err(inst->dev, "sgl submit failed");
1269 +                       count = 0;
1270 +                       goto out;
1271 +               }
1272 +               count_left -= chunk_size;
1273 +               chunk_no++;
1274 +       }
1275 +       dma_async_issue_pending(inst->dma_chan);
1276 +
1277 +       if (inst->settings.data_width == SMI_WIDTH_8BIT)
1278 +               init_trans_func(inst, count);
1279 +       else if (inst->settings.data_width == SMI_WIDTH_16BIT)
1280 +               init_trans_func(inst, count / 2);
1281 +out:
1282 +       spin_unlock(&inst->transaction_lock);
1283 +       return count;
1284 +}
1285 +EXPORT_SYMBOL(bcm2835_smi_user_dma);
1286 +
1287 +
1288 +/****************************************************************************
1289 +*
1290 +*   High level buffer transfer functions - for use by other drivers
1291 +*
1292 +***************************************************************************/
1293 +
1294 +/* Buffer must be physically contiguous - i.e. kmalloc, not vmalloc! */
1295 +void bcm2835_smi_write_buf(
1296 +       struct bcm2835_smi_instance *inst,
1297 +       const void *buf, size_t n_bytes)
1298 +{
1299 +       int odd_bytes = n_bytes & 0x3;
1300 +
1301 +       n_bytes -= odd_bytes;
1302 +
1303 +       spin_lock(&inst->transaction_lock);
1304 +
1305 +       if (n_bytes > DMA_THRESHOLD_BYTES) {
1306 +               dma_addr_t phy_addr = dma_map_single(
1307 +                       inst->dev,
1308 +                       (void *)buf,
1309 +                       n_bytes,
1310 +                       DMA_TO_DEVICE);
1311 +               struct scatterlist *sgl =
1312 +                       smi_scatterlist_from_buffer(inst, phy_addr, n_bytes,
1313 +                               &inst->buffer_sgl);
1314 +
1315 +               if (!sgl) {
1316 +                       smi_dump_context_labelled(inst,
1317 +                       "Error: could not create scatterlist for write!");
1318 +                       goto out;
1319 +               }
1320 +               smi_dma_write_sgl(inst, sgl, 1, n_bytes);
1321 +
1322 +               dma_unmap_single
1323 +                       (inst->dev, phy_addr, n_bytes, DMA_TO_DEVICE);
1324 +       } else if (n_bytes) {
1325 +               smi_write_fifo(inst, (uint32_t *) buf, n_bytes);
1326 +       }
1327 +       buf += n_bytes;
1328 +
1329 +       if (inst->settings.data_width == SMI_WIDTH_8BIT) {
1330 +               while (odd_bytes--)
1331 +                       smi_write_single_word(inst, *(uint8_t *) (buf++));
1332 +       } else {
1333 +               while (odd_bytes >= 2) {
1334 +                       smi_write_single_word(inst, *(uint16_t *)buf);
1335 +                       buf += 2;
1336 +                       odd_bytes -= 2;
1337 +               }
1338 +               if (odd_bytes) {
1339 +                       /* Reading an odd number of bytes on a 16 bit bus is
1340 +                          a user bug. It's kinder to fail early and tell them
1341 +                          than to e.g. transparently give them the bottom byte
1342 +                          of a 16 bit transfer. */
1343 +                       dev_err(inst->dev,
1344 +               "WARNING: odd number of bytes specified for wide transfer.");
1345 +                       dev_err(inst->dev,
1346 +               "At least one byte dropped as a result.");
1347 +                       dump_stack();
1348 +               }
1349 +       }
1350 +out:
1351 +       spin_unlock(&inst->transaction_lock);
1352 +}
1353 +EXPORT_SYMBOL(bcm2835_smi_write_buf);
1354 +
1355 +void bcm2835_smi_read_buf(struct bcm2835_smi_instance *inst,
1356 +       void *buf, size_t n_bytes)
1357 +{
1358 +
1359 +       /* SMI is inherently 32-bit, which causes surprising amounts of mess
1360 +          for bytes % 4 != 0. Easiest to avoid this mess altogether
1361 +          by handling remainder separately. */
1362 +       int odd_bytes = n_bytes & 0x3;
1363 +
1364 +       spin_lock(&inst->transaction_lock);
1365 +       n_bytes -= odd_bytes;
1366 +       if (n_bytes > DMA_THRESHOLD_BYTES) {
1367 +               dma_addr_t phy_addr = dma_map_single(inst->dev,
1368 +                                                    buf, n_bytes,
1369 +                                                    DMA_FROM_DEVICE);
1370 +               struct scatterlist *sgl = smi_scatterlist_from_buffer(
1371 +                       inst, phy_addr, n_bytes,
1372 +                       &inst->buffer_sgl);
1373 +               if (!sgl) {
1374 +                       smi_dump_context_labelled(inst,
1375 +                       "Error: could not create scatterlist for read!");
1376 +                       goto out;
1377 +               }
1378 +               smi_dma_read_sgl(inst, sgl, 1, n_bytes);
1379 +               dma_unmap_single(inst->dev, phy_addr, n_bytes, DMA_FROM_DEVICE);
1380 +       } else if (n_bytes) {
1381 +               smi_read_fifo(inst, (uint32_t *)buf, n_bytes);
1382 +       }
1383 +       buf += n_bytes;
1384 +
1385 +       if (inst->settings.data_width == SMI_WIDTH_8BIT) {
1386 +               while (odd_bytes--)
1387 +                       *((uint8_t *) (buf++)) = smi_read_single_word(inst);
1388 +       } else {
1389 +               while (odd_bytes >= 2) {
1390 +                       *(uint16_t *) buf = smi_read_single_word(inst);
1391 +                       buf += 2;
1392 +                       odd_bytes -= 2;
1393 +               }
1394 +               if (odd_bytes) {
1395 +                       dev_err(inst->dev,
1396 +               "WARNING: odd number of bytes specified for wide transfer.");
1397 +                       dev_err(inst->dev,
1398 +               "At least one byte dropped as a result.");
1399 +                       dump_stack();
1400 +               }
1401 +       }
1402 +out:
1403 +       spin_unlock(&inst->transaction_lock);
1404 +}
1405 +EXPORT_SYMBOL(bcm2835_smi_read_buf);
1406 +
1407 +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
1408 +       unsigned int address)
1409 +{
1410 +       spin_lock(&inst->transaction_lock);
1411 +       smi_set_address(inst, address);
1412 +       spin_unlock(&inst->transaction_lock);
1413 +}
1414 +EXPORT_SYMBOL(bcm2835_smi_set_address);
1415 +
1416 +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node)
1417 +{
1418 +       struct platform_device *pdev;
1419 +
1420 +       if (!node)
1421 +               return NULL;
1422 +
1423 +       pdev = of_find_device_by_node(node);
1424 +       if (!pdev)
1425 +               return NULL;
1426 +
1427 +       return platform_get_drvdata(pdev);
1428 +}
1429 +EXPORT_SYMBOL(bcm2835_smi_get);
1430 +
1431 +/****************************************************************************
1432 +*
1433 +*   bcm2835_smi_probe - called when the driver is loaded.
1434 +*
1435 +***************************************************************************/
1436 +
1437 +static int bcm2835_smi_dma_setup(struct bcm2835_smi_instance *inst)
1438 +{
1439 +       int i, rv = 0;
1440 +
1441 +       inst->dma_chan = dma_request_slave_channel(inst->dev, "rx-tx");
1442 +
1443 +       inst->dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1444 +       inst->dma_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1445 +       inst->dma_config.src_addr = inst->smi_regs_busaddr + SMID;
1446 +       inst->dma_config.dst_addr = inst->dma_config.src_addr;
1447 +       /* Direction unimportant - always overridden by prep_slave_sg */
1448 +       inst->dma_config.direction = DMA_DEV_TO_MEM;
1449 +       dmaengine_slave_config(inst->dma_chan, &inst->dma_config);
1450 +       /* Alloc and map bounce buffers */
1451 +       for (i = 0; i < DMA_BOUNCE_BUFFER_COUNT; ++i) {
1452 +               inst->bounce.buffer[i] =
1453 +               dmam_alloc_coherent(inst->dev, DMA_BOUNCE_BUFFER_SIZE,
1454 +                               &inst->bounce.phys[i],
1455 +                               GFP_KERNEL);
1456 +               if (!inst->bounce.buffer[i]) {
1457 +                       dev_err(inst->dev, "Could not allocate buffer!");
1458 +                       rv = -ENOMEM;
1459 +                       break;
1460 +               }
1461 +               smi_scatterlist_from_buffer(
1462 +                       inst,
1463 +                       inst->bounce.phys[i],
1464 +                       DMA_BOUNCE_BUFFER_SIZE,
1465 +                       &inst->bounce.sgl[i]
1466 +               );
1467 +       }
1468 +
1469 +       return rv;
1470 +}
1471 +
1472 +static int bcm2835_smi_probe(struct platform_device *pdev)
1473 +{
1474 +       int err;
1475 +       struct device *dev = &pdev->dev;
1476 +       struct device_node *node = dev->of_node;
1477 +       struct resource *ioresource;
1478 +       struct bcm2835_smi_instance *inst;
1479 +       const __be32 *addr;
1480 +
1481 +       /* We require device tree support */
1482 +       if (!node)
1483 +               return -EINVAL;
1484 +       /* Allocate buffers and instance data */
1485 +       inst = devm_kzalloc(dev, sizeof(struct bcm2835_smi_instance),
1486 +               GFP_KERNEL);
1487 +       if (!inst)
1488 +               return -ENOMEM;
1489 +
1490 +       inst->dev = dev;
1491 +       spin_lock_init(&inst->transaction_lock);
1492 +
1493 +       ioresource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1494 +       inst->smi_regs_ptr = devm_ioremap_resource(dev, ioresource);
1495 +       if (IS_ERR(inst->smi_regs_ptr)) {
1496 +               err = PTR_ERR(inst->smi_regs_ptr);
1497 +               goto err;
1498 +       }
1499 +       addr = of_get_address(node, 0, NULL, NULL);
1500 +       inst->smi_regs_busaddr = be32_to_cpu(*addr);
1501 +
1502 +       err = bcm2835_smi_dma_setup(inst);
1503 +       if (err)
1504 +               goto err;
1505 +
1506 +       /* request clock */
1507 +       inst->clk = devm_clk_get(dev, NULL);
1508 +       if (!inst->clk)
1509 +               goto err;
1510 +       clk_prepare_enable(inst->clk);
1511 +
1512 +       /* Finally, do peripheral setup */
1513 +       smi_setup_regs(inst);
1514 +
1515 +       platform_set_drvdata(pdev, inst);
1516 +
1517 +       dev_info(inst->dev, "initialised");
1518 +
1519 +       return 0;
1520 +err:
1521 +       kfree(inst);
1522 +       return err;
1523 +}
1524 +
1525 +/****************************************************************************
1526 +*
1527 +*   bcm2835_smi_remove - called when the driver is unloaded.
1528 +*
1529 +***************************************************************************/
1530 +
1531 +static int bcm2835_smi_remove(struct platform_device *pdev)
1532 +{
1533 +       struct bcm2835_smi_instance *inst = platform_get_drvdata(pdev);
1534 +       struct device *dev = inst->dev;
1535 +
1536 +       dmaengine_terminate_all(inst->dma_chan);
1537 +       dma_release_channel(inst->dma_chan);
1538 +
1539 +       clk_disable_unprepare(inst->clk);
1540 +
1541 +       dev_info(dev, "SMI device removed - OK");
1542 +       return 0;
1543 +}
1544 +
1545 +/****************************************************************************
1546 +*
1547 +*   Register the driver with device tree
1548 +*
1549 +***************************************************************************/
1550 +
1551 +static const struct of_device_id bcm2835_smi_of_match[] = {
1552 +       {.compatible = "brcm,bcm2835-smi",},
1553 +       { /* sentinel */ },
1554 +};
1555 +
1556 +MODULE_DEVICE_TABLE(of, bcm2835_smi_of_match);
1557 +
1558 +static struct platform_driver bcm2835_smi_driver = {
1559 +       .probe = bcm2835_smi_probe,
1560 +       .remove = bcm2835_smi_remove,
1561 +       .driver = {
1562 +                  .name = DRIVER_NAME,
1563 +                  .owner = THIS_MODULE,
1564 +                  .of_match_table = bcm2835_smi_of_match,
1565 +                  },
1566 +};
1567 +
1568 +module_platform_driver(bcm2835_smi_driver);
1569 +
1570 +MODULE_ALIAS("platform:smi-bcm2835");
1571 +MODULE_LICENSE("GPL");
1572 +MODULE_DESCRIPTION("Device driver for BCM2835's secondary memory interface");
1573 +MODULE_AUTHOR("Luke Wren <luke@raspberrypi.org>");
1574 --- /dev/null
1575 +++ b/include/linux/broadcom/bcm2835_smi.h
1576 @@ -0,0 +1,391 @@
1577 +/**
1578 + * Declarations and definitions for Broadcom's Secondary Memory Interface
1579 + *
1580 + * Written by Luke Wren <luke@raspberrypi.org>
1581 + * Copyright (c) 2015, Raspberry Pi (Trading) Ltd.
1582 + * Copyright (c) 2010-2012 Broadcom. All rights reserved.
1583 + *
1584 + * Redistribution and use in source and binary forms, with or without
1585 + * modification, are permitted provided that the following conditions
1586 + * are met:
1587 + * 1. Redistributions of source code must retain the above copyright
1588 + *    notice, this list of conditions, and the following disclaimer,
1589 + *    without modification.
1590 + * 2. Redistributions in binary form must reproduce the above copyright
1591 + *    notice, this list of conditions and the following disclaimer in the
1592 + *    documentation and/or other materials provided with the distribution.
1593 + * 3. The names of the above-listed copyright holders may not be used
1594 + *    to endorse or promote products derived from this software without
1595 + *    specific prior written permission.
1596 + *
1597 + * ALTERNATIVELY, this software may be distributed under the terms of the
1598 + * GNU General Public License ("GPL") version 2, as published by the Free
1599 + * Software Foundation.
1600 + *
1601 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
1602 + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
1603 + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
1604 + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
1605 + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
1606 + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
1607 + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
1608 + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
1609 + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
1610 + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
1611 + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1612 + */
1613 +
1614 +#ifndef BCM2835_SMI_H
1615 +#define BCM2835_SMI_H
1616 +
1617 +#include <linux/ioctl.h>
1618 +
1619 +#ifndef __KERNEL__
1620 +#include <stdint.h>
1621 +#include <stdbool.h>
1622 +#endif
1623 +
1624 +#define BCM2835_SMI_IOC_MAGIC 0x1
1625 +#define BCM2835_SMI_INVALID_HANDLE (~0)
1626 +
1627 +/* IOCTLs 0x100...0x1ff are not device-specific - we can use them */
1628 +#define BCM2835_SMI_IOC_GET_SETTINGS    _IO(BCM2835_SMI_IOC_MAGIC, 0)
1629 +#define BCM2835_SMI_IOC_WRITE_SETTINGS  _IO(BCM2835_SMI_IOC_MAGIC, 1)
1630 +#define BCM2835_SMI_IOC_ADDRESS         _IO(BCM2835_SMI_IOC_MAGIC, 2)
1631 +#define BCM2835_SMI_IOC_MAX         2
1632 +
1633 +#define SMI_WIDTH_8BIT 0
1634 +#define SMI_WIDTH_16BIT 1
1635 +#define SMI_WIDTH_9BIT 2
1636 +#define SMI_WIDTH_18BIT 3
1637 +
1638 +/* max number of bytes where DMA will not be used */
1639 +#define DMA_THRESHOLD_BYTES 128
1640 +#define DMA_BOUNCE_BUFFER_SIZE (1024 * 1024 / 2)
1641 +#define DMA_BOUNCE_BUFFER_COUNT 3
1642 +
1643 +
1644 +struct smi_settings {
1645 +       int data_width;
1646 +       /* Whether or not to pack multiple SMI transfers into a
1647 +          single 32 bit FIFO word */
1648 +       bool pack_data;
1649 +
1650 +       /* Timing for reads (writes the same but for WE)
1651 +        *
1652 +        * OE ----------+          +--------------------
1653 +        *              |          |
1654 +        *              +----------+
1655 +        * SD -<==============================>-----------
1656 +        * SA -<=========================================>-
1657 +        *    <-setup->  <-strobe ->  <-hold ->  <- pace ->
1658 +        */
1659 +
1660 +       int read_setup_time;
1661 +       int read_hold_time;
1662 +       int read_pace_time;
1663 +       int read_strobe_time;
1664 +
1665 +       int write_setup_time;
1666 +       int write_hold_time;
1667 +       int write_pace_time;
1668 +       int write_strobe_time;
1669 +
1670 +       bool dma_enable;                /* DREQs */
1671 +       bool dma_passthrough_enable;    /* External DREQs */
1672 +       int dma_read_thresh;
1673 +       int dma_write_thresh;
1674 +       int dma_panic_read_thresh;
1675 +       int dma_panic_write_thresh;
1676 +};
1677 +
1678 +/****************************************************************************
1679 +*
1680 +*   Declare exported SMI functions
1681 +*
1682 +***************************************************************************/
1683 +
1684 +#ifdef __KERNEL__
1685 +
1686 +#include <linux/dmaengine.h> /* for enum dma_transfer_direction */
1687 +#include <linux/of.h>
1688 +#include <linux/semaphore.h>
1689 +
1690 +struct bcm2835_smi_instance;
1691 +
1692 +struct bcm2835_smi_bounce_info {
1693 +       struct semaphore callback_sem;
1694 +       void *buffer[DMA_BOUNCE_BUFFER_COUNT];
1695 +       dma_addr_t phys[DMA_BOUNCE_BUFFER_COUNT];
1696 +       struct scatterlist sgl[DMA_BOUNCE_BUFFER_COUNT];
1697 +};
1698 +
1699 +
1700 +void bcm2835_smi_set_regs_from_settings(struct bcm2835_smi_instance *);
1701 +
1702 +struct smi_settings *bcm2835_smi_get_settings_from_regs(
1703 +       struct bcm2835_smi_instance *inst);
1704 +
1705 +void bcm2835_smi_write_buf(
1706 +       struct bcm2835_smi_instance *inst,
1707 +       const void *buf,
1708 +       size_t n_bytes);
1709 +
1710 +void bcm2835_smi_read_buf(
1711 +       struct bcm2835_smi_instance *inst,
1712 +       void *buf,
1713 +       size_t n_bytes);
1714 +
1715 +void bcm2835_smi_set_address(struct bcm2835_smi_instance *inst,
1716 +       unsigned int address);
1717 +
1718 +ssize_t bcm2835_smi_user_dma(
1719 +       struct bcm2835_smi_instance *inst,
1720 +       enum dma_transfer_direction dma_dir,
1721 +       char __user *user_ptr,
1722 +       size_t count,
1723 +       struct bcm2835_smi_bounce_info **bounce);
1724 +
1725 +struct bcm2835_smi_instance *bcm2835_smi_get(struct device_node *node);
1726 +
1727 +#endif /* __KERNEL__ */
1728 +
1729 +/****************************************************************
1730 +*
1731 +*      Implementation-only declarations
1732 +*
1733 +****************************************************************/
1734 +
1735 +#ifdef BCM2835_SMI_IMPLEMENTATION
1736 +
1737 +/* Clock manager registers for SMI clock: */
1738 +#define CM_SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x1010b0)
1739 +/* Clock manager "password" to protect registers from spurious writes */
1740 +#define CM_PWD (0x5a << 24)
1741 +
1742 +#define CM_SMI_CTL     0x00
1743 +#define CM_SMI_DIV     0x04
1744 +
1745 +#define CM_SMI_CTL_FLIP (1 << 8)
1746 +#define CM_SMI_CTL_BUSY (1 << 7)
1747 +#define CM_SMI_CTL_KILL (1 << 5)
1748 +#define CM_SMI_CTL_ENAB (1 << 4)
1749 +#define CM_SMI_CTL_SRC_MASK (0xf)
1750 +#define CM_SMI_CTL_SRC_OFFS (0)
1751 +
1752 +#define CM_SMI_DIV_DIVI_MASK (0xf <<  12)
1753 +#define CM_SMI_DIV_DIVI_OFFS (12)
1754 +#define CM_SMI_DIV_DIVF_MASK (0xff << 4)
1755 +#define CM_SMI_DIV_DIVF_OFFS (4)
1756 +
1757 +/* SMI register mapping:*/
1758 +#define SMI_BASE_ADDRESS ((BCM2708_PERI_BASE) + 0x600000)
1759 +
1760 +#define SMICS  0x00    /* control + status register            */
1761 +#define SMIL   0x04    /* length/count (n external txfers)     */
1762 +#define SMIA   0x08    /* address register                     */
1763 +#define SMID   0x0c    /* data register                        */
1764 +#define SMIDSR0        0x10    /* device 0 read settings               */
1765 +#define SMIDSW0        0x14    /* device 0 write settings              */
1766 +#define SMIDSR1        0x18    /* device 1 read settings               */
1767 +#define SMIDSW1        0x1c    /* device 1 write settings              */
1768 +#define SMIDSR2        0x20    /* device 2 read settings               */
1769 +#define SMIDSW2        0x24    /* device 2 write settings              */
1770 +#define SMIDSR3        0x28    /* device 3 read settings               */
1771 +#define SMIDSW3        0x2c    /* device 3 write settings              */
1772 +#define SMIDC  0x30    /* DMA control registers                */
1773 +#define SMIDCS 0x34    /* direct control/status register       */
1774 +#define SMIDA  0x38    /* direct address register              */
1775 +#define SMIDD  0x3c    /* direct data registers                */
1776 +#define SMIFD  0x40    /* FIFO debug register                  */
1777 +
1778 +
1779 +
1780 +/* Control and Status register bits:
1781 + * SMICS_RXF   : RX fifo full: 1 when RX fifo is full
1782 + * SMICS_TXE   : TX fifo empty: 1 when empty.
1783 + * SMICS_RXD   : RX fifo contains data: 1 when there is data.
1784 + * SMICS_TXD   : TX fifo can accept data: 1 when true.
1785 + * SMICS_RXR   : RX fifo needs reading: 1 when fifo more than 3/4 full, or
1786 + *               when "DONE" and fifo not emptied.
1787 + * SMICS_TXW   : TX fifo needs writing: 1 when less than 1/4 full.
1788 + * SMICS_AFERR : AXI FIFO error: 1 when fifo read when empty or written
1789 + *               when full. Write 1 to clear.
1790 + * SMICS_EDREQ : 1 when external DREQ received.
1791 + * SMICS_PXLDAT        :  Pixel data:  write 1 to enable pixel transfer modes.
1792 + * SMICS_SETERR        : 1 if there was an error writing to setup regs (e.g.
1793 + *               tx was in progress). Write 1 to clear.
1794 + * SMICS_PVMODE        : Set to 1 to enable pixel valve mode.
1795 + * SMICS_INTR  : Set to 1 to enable interrupt on RX.
1796 + * SMICS_INTT  : Set to 1 to enable interrupt on TX.
1797 + * SMICS_INTD  : Set to 1 to enable interrupt on DONE condition.
1798 + * SMICS_TEEN  : Tear effect mode enabled: Programmed transfers will wait
1799 + *               for a TE trigger before writing.
1800 + * SMICS_PAD1  : Padding settings for external transfers. For writes: the
1801 + *               number of bytes initially written to  the TX fifo that
1802 + * SMICS_PAD0  : should be ignored. For reads: the number of bytes that will
1803 + *               be read before the data, and should be dropped.
1804 + * SMICS_WRITE : Transfer direction: 1 = write to external device, 0 = read
1805 + * SMICS_CLEAR : Write 1 to clear the FIFOs.
1806 + * SMICS_START : Write 1 to start the programmed transfer.
1807 + * SMICS_ACTIVE        : Reads as 1 when a programmed transfer is underway.
1808 + * SMICS_DONE  : Reads as 1 when transfer finished. For RX, not set until
1809 + *               FIFO emptied.
1810 + * SMICS_ENABLE        : Set to 1 to enable the SMI peripheral, 0 to disable.
1811 + */
1812 +
1813 +#define SMICS_RXF      (1 << 31)
1814 +#define SMICS_TXE      (1 << 30)
1815 +#define SMICS_RXD      (1 << 29)
1816 +#define SMICS_TXD      (1 << 28)
1817 +#define SMICS_RXR      (1 << 27)
1818 +#define SMICS_TXW      (1 << 26)
1819 +#define SMICS_AFERR    (1 << 25)
1820 +#define SMICS_EDREQ    (1 << 15)
1821 +#define SMICS_PXLDAT   (1 << 14)
1822 +#define SMICS_SETERR   (1 << 13)
1823 +#define SMICS_PVMODE   (1 << 12)
1824 +#define SMICS_INTR     (1 << 11)
1825 +#define SMICS_INTT     (1 << 10)
1826 +#define SMICS_INTD     (1 << 9)
1827 +#define SMICS_TEEN     (1 << 8)
1828 +#define SMICS_PAD1     (1 << 7)
1829 +#define SMICS_PAD0     (1 << 6)
1830 +#define SMICS_WRITE    (1 << 5)
1831 +#define SMICS_CLEAR    (1 << 4)
1832 +#define SMICS_START    (1 << 3)
1833 +#define SMICS_ACTIVE   (1 << 2)
1834 +#define SMICS_DONE     (1 << 1)
1835 +#define SMICS_ENABLE   (1 << 0)
1836 +
1837 +/* Address register bits: */
1838 +
1839 +#define SMIA_DEVICE_MASK ((1 << 9) | (1 << 8))
1840 +#define SMIA_DEVICE_OFFS (8)
1841 +#define SMIA_ADDR_MASK (0x3f)  /* bits 5 -> 0 */
1842 +#define SMIA_ADDR_OFFS (0)
1843 +
1844 +/* DMA control register bits:
1845 + * SMIDC_DMAEN : DMA enable: set 1: DMA requests will be issued.
1846 + * SMIDC_DMAP  : DMA passthrough: when set to 0, top two data pins are used by
1847 + *               SMI as usual. When set to 1, the top two pins are used for
1848 + *               external DREQs: pin 16 read request, 17 write.
1849 + * SMIDC_PANIC*        : Threshold at which DMA will panic during read/write.
1850 + * SMIDC_REQ*  : Threshold at which DMA will generate a DREQ.
1851 + */
1852 +
1853 +#define SMIDC_DMAEN            (1 << 28)
1854 +#define SMIDC_DMAP             (1 << 24)
1855 +#define SMIDC_PANICR_MASK      (0x3f << 18)
1856 +#define SMIDC_PANICR_OFFS      (18)
1857 +#define SMIDC_PANICW_MASK      (0x3f << 12)
1858 +#define SMIDC_PANICW_OFFS      (12)
1859 +#define SMIDC_REQR_MASK                (0x3f << 6)
1860 +#define SMIDC_REQR_OFFS                (6)
1861 +#define SMIDC_REQW_MASK                (0x3f)
1862 +#define SMIDC_REQW_OFFS                (0)
1863 +
1864 +/* Device settings register bits: same for all 4 (or 3?) device register sets.
1865 + * Device read settings:
1866 + * SMIDSR_RWIDTH       : Read transfer width. 00 = 8bit, 01 = 16bit,
1867 + *                       10 = 18bit, 11 = 9bit.
1868 + * SMIDSR_RSETUP       : Read setup time: number of core cycles between chip
1869 + *                       select/address and read strobe. Min 1, max 64.
1870 + * SMIDSR_MODE68       : 1 for System 68 mode (i.e. enable + direction pins,
1871 + *                       rather than OE + WE pin)
1872 + * SMIDSR_FSETUP       : If set to 1, setup time only applies to first
1873 + *                       transfer after address change.
1874 + * SMIDSR_RHOLD                : Number of core cycles between read strobe going
1875 + *                       inactive and CS/address going inactive. Min 1, max 64
1876 + * SMIDSR_RPACEALL     : When set to 1, this device's RPACE value will always
1877 + *                       be used for the next transaction, even if it is not
1878 + *                       to this device.
1879 + * SMIDSR_RPACE                : Number of core cycles spent waiting between CS
1880 + *                       deassert and start of next transfer. Min 1, max 128
1881 + * SMIDSR_RDREQ                : 1 = use external DMA request on SD16 to pace reads
1882 + *                       from device. Must also set DMAP in SMICS.
1883 + * SMIDSR_RSTROBE      : Number of cycles to assert the read strobe.
1884 + *                       min 1, max 128.
1885 + */
1886 +#define SMIDSR_RWIDTH_MASK     ((1<<31)|(1<<30))
1887 +#define SMIDSR_RWIDTH_OFFS     (30)
1888 +#define SMIDSR_RSETUP_MASK     (0x3f << 24)
1889 +#define SMIDSR_RSETUP_OFFS     (24)
1890 +#define SMIDSR_MODE68          (1 << 23)
1891 +#define SMIDSR_FSETUP          (1 << 22)
1892 +#define SMIDSR_RHOLD_MASK      (0x3f << 16)
1893 +#define SMIDSR_RHOLD_OFFS      (16)
1894 +#define SMIDSR_RPACEALL                (1 << 15)
1895 +#define SMIDSR_RPACE_MASK      (0x7f << 8)
1896 +#define SMIDSR_RPACE_OFFS      (8)
1897 +#define SMIDSR_RDREQ           (1 << 7)
1898 +#define SMIDSR_RSTROBE_MASK    (0x7f)
1899 +#define SMIDSR_RSTROBE_OFFS    (0)
1900 +
1901 +/* Device write settings:
1902 + * SMIDSW_WWIDTH       : Write transfer width. 00 = 8bit, 01 = 16bit,
1903 + *                       10= 18bit, 11 = 9bit.
1904 + * SMIDSW_WSETUP       : Number of cycles between CS assert and write strobe.
1905 + *                       Min 1, max 64.
1906 + * SMIDSW_WFORMAT      : Pixel format of input. 0 = 16bit RGB 565,
1907 + *                       1 = 32bit RGBA 8888
1908 + * SMIDSW_WSWAP                : 1 = swap pixel data bits. (Use with SMICS_PXLDAT)
1909 + * SMIDSW_WHOLD                : Time between WE deassert and CS deassert. 1 to 64
1910 + * SMIDSW_WPACEALL     : 1: this device's WPACE will be used for the next
1911 + *                       transfer, regardless of that transfer's device.
1912 + * SMIDSW_WPACE                : Cycles between CS deassert and next CS assert.
1913 + *                       Min 1, max 128
1914 + * SMIDSW_WDREQ                : Use external DREQ on pin 17 to pace writes. DMAP must
1915 + *                       be set in SMICS.
1916 + * SMIDSW_WSTROBE      : Number of cycles to assert the write strobe.
1917 + *                       Min 1, max 128
1918 + */
1919 +#define SMIDSW_WWIDTH_MASK      ((1<<31)|(1<<30))
1920 +#define SMIDSW_WWIDTH_OFFS     (30)
1921 +#define SMIDSW_WSETUP_MASK     (0x3f << 24)
1922 +#define SMIDSW_WSETUP_OFFS     (24)
1923 +#define SMIDSW_WFORMAT         (1 << 23)
1924 +#define SMIDSW_WSWAP           (1 << 22)
1925 +#define SMIDSW_WHOLD_MASK      (0x3f << 16)
1926 +#define SMIDSW_WHOLD_OFFS      (16)
1927 +#define SMIDSW_WPACEALL                (1 << 15)
1928 +#define SMIDSW_WPACE_MASK      (0x7f << 8)
1929 +#define SMIDSW_WPACE_OFFS      (8)
1930 +#define SMIDSW_WDREQ           (1 << 7)
1931 +#define SMIDSW_WSTROBE_MASK     (0x7f)
1932 +#define SMIDSW_WSTROBE_OFFS     (0)
1933 +
1934 +/* Direct transfer control + status register
1935 + * SMIDCS_WRITE        : Direction of transfer: 1 -> write, 0 -> read
1936 + * SMIDCS_DONE : 1 when a transfer has finished. Write 1 to clear.
1937 + * SMIDCS_START        : Write 1 to start a transfer, if one is not already underway.
1938 + * SMIDCE_ENABLE: Write 1 to enable SMI in direct mode.
1939 + */
1940 +
1941 +#define SMIDCS_WRITE           (1 << 3)
1942 +#define SMIDCS_DONE            (1 << 2)
1943 +#define SMIDCS_START           (1 << 1)
1944 +#define SMIDCS_ENABLE          (1 << 0)
1945 +
1946 +/* Direct transfer address register
1947 + * SMIDA_DEVICE        : Indicates which of the device settings banks should be used.
1948 + * SMIDA_ADDR  : The value to be asserted on the address pins.
1949 + */
1950 +
1951 +#define SMIDA_DEVICE_MASK      ((1<<9)|(1<<8))
1952 +#define SMIDA_DEVICE_OFFS      (8)
1953 +#define SMIDA_ADDR_MASK                (0x3f)
1954 +#define SMIDA_ADDR_OFFS                (0)
1955 +
1956 +/* FIFO debug register
1957 + * SMIFD_FLVL  : The high-tide mark of FIFO count during the most recent txfer
1958 + * SMIFD_FCNT  : The current FIFO count.
1959 + */
1960 +#define SMIFD_FLVL_MASK                (0x3f << 8)
1961 +#define SMIFD_FLVL_OFFS                (8)
1962 +#define SMIFD_FCNT_MASK                (0x3f)
1963 +#define SMIFD_FCNT_OFFS                (0)
1964 +
1965 +#endif /* BCM2835_SMI_IMPLEMENTATION */
1966 +
1967 +#endif /* BCM2835_SMI_H */