1 From b627647c4500d39cb026924b608841fdf4d4d7e9 Mon Sep 17 00:00:00 2001
2 From: Ulf Hansson <ulf.hansson@linaro.org>
3 Date: Thu, 29 Oct 2020 09:57:16 +0800
4 Subject: [PATCH] mmc: brcmstb: add support for BCM2712
6 BCM2712 has an SD Express capable SDHCI implementation and uses
7 the SDIO CFG register block present on other STB chips.
9 Add plumbing for SD Express handover and BCM2712-specific functions.
11 Due to the common bus infrastructure between BCM2711 and BCM2712,
12 the driver also needs to implement 32-bit IO accessors.
14 mmc: brcmstb: override card presence if broken-cd is set
16 Not just if the card is declared as nonremovable.
18 sdhci: brcmstb: align SD express switchover with SD spec v8.00
20 Part 1 of the Physical specification, figure 3-24, details the switch
21 sequence for cards initially probed as SD. Add a missing check for DAT2
22 level after switching VDD2 on.
24 sdhci: brcmstb: clean up SD Express probe and error handling
26 Refactor to avoid spurious error messages in dmesg if the requisite SD
27 Express DT nodes aren't present.
29 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
31 mmc: sdhci-brcmstb: only use the delay line PHY for tuneable speeds
33 The MMC core has a 200MHz core clock which allows the use of DDR50 and
34 below without incremental phase tuning. SDR50/SDR104 and the EMMC HS200
35 speeds require tuning.
37 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
39 drivers/mmc/host/Kconfig | 2 +
40 drivers/mmc/host/sdhci-brcmstb.c | 356 +++++++++++++++++++++++++++++++
41 2 files changed, 358 insertions(+)
43 --- a/drivers/mmc/host/Kconfig
44 +++ b/drivers/mmc/host/Kconfig
45 @@ -1082,7 +1082,9 @@ config MMC_SDHCI_BRCMSTB
46 tristate "Broadcom SDIO/SD/MMC support"
47 depends on ARCH_BRCMSTB || BMIPS_GENERIC
48 depends on MMC_SDHCI_PLTFM
49 + select MMC_SDHCI_IO_ACCESSORS
54 This selects support for the SDIO/SD/MMC Host Controller on
55 --- a/drivers/mmc/host/sdhci-brcmstb.c
56 +++ b/drivers/mmc/host/sdhci-brcmstb.c
59 #include <linux/bitops.h>
60 #include <linux/delay.h>
61 +#include <linux/pinctrl/consumer.h>
62 +#include <linux/regulator/consumer.h>
64 #include "sdhci-cqhci.h"
65 #include "sdhci-pltfm.h"
68 #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0)
69 #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1)
70 +#define BRCMSTB_PRIV_FLAGS_HAS_SD_EXPRESS BIT(2)
72 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
74 +#define SDIO_CFG_CTRL 0x0
75 +#define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31)
76 +#define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30)
78 +#define SDIO_CFG_SD_PIN_SEL 0x44
79 +#define SDIO_CFG_SD_PIN_SEL_MASK 0x3
80 +#define SDIO_CFG_SD_PIN_SEL_CARD BIT(1)
82 +#define SDIO_CFG_MAX_50MHZ_MODE 0x1ac
83 +#define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31)
84 +#define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0)
86 struct sdhci_brcmstb_priv {
87 void __iomem *cfg_regs;
93 + bool is_cmd_shadowed;
94 + bool is_blk_shadowed;
95 + struct regulator *sde_1v8;
96 + struct device_node *sde_pcie;
97 + void *__iomem sde_ioaddr;
98 + void *__iomem sde_ioaddr2;
99 + struct pinctrl *pinctrl;
100 + struct pinctrl_state *pins_default;
101 + struct pinctrl_state *pins_sdex;
104 struct brcmstb_match_priv {
105 void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
106 + void (*cfginit)(struct sdhci_host *host);
107 struct sdhci_ops *ops;
108 const unsigned int flags;
110 @@ -94,6 +121,124 @@ static void sdhci_brcmstb_set_clock(stru
111 sdhci_enable_clk(host, clk);
114 +#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
116 +static inline u32 sdhci_brcmstb_32only_readl(struct sdhci_host *host, int reg)
118 + u32 val = readl(host->ioaddr + reg);
120 + pr_debug("%s: readl [0x%02x] 0x%08x\n",
121 + mmc_hostname(host->mmc), reg, val);
125 +static u16 sdhci_brcmstb_32only_readw(struct sdhci_host *host, int reg)
127 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
128 + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
132 + if ((reg == SDHCI_TRANSFER_MODE) && brcmstb_priv->is_cmd_shadowed) {
133 + /* Get the saved transfer mode */
134 + val = brcmstb_priv->shadow_cmd;
135 + } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
136 + brcmstb_priv->is_blk_shadowed) {
137 + /* Get the saved block info */
138 + val = brcmstb_priv->shadow_blk;
140 + val = sdhci_brcmstb_32only_readl(host, (reg & ~3));
142 + word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
146 +static u8 sdhci_brcmstb_32only_readb(struct sdhci_host *host, int reg)
148 + u32 val = sdhci_brcmstb_32only_readl(host, (reg & ~3));
149 + u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
153 +static inline void sdhci_brcmstb_32only_writel(struct sdhci_host *host, u32 val, int reg)
155 + pr_debug("%s: writel [0x%02x] 0x%08x\n",
156 + mmc_hostname(host->mmc), reg, val);
158 + writel(val, host->ioaddr + reg);
162 + * BCM2712 unfortunately carries with it a perennial bug with the SD controller
163 + * register interface present on previous chips (2711/2709/2708). Accesses must
164 + * be dword-sized and a read-modify-write cycle to the 32-bit registers
165 + * containing the COMMAND, TRANSFER_MODE, BLOCK_SIZE and BLOCK_COUNT registers
166 + * tramples the upper/lower 16 bits of data written. BCM2712 does not seem to
167 + * need the extreme delay between each write as on previous chips, just the
168 + * serialisation of writes to these registers in a single 32-bit operation.
170 +static void sdhci_brcmstb_32only_writew(struct sdhci_host *host, u16 val, int reg)
172 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
173 + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
174 + u32 word_shift = REG_OFFSET_IN_BITS(reg);
175 + u32 mask = 0xffff << word_shift;
176 + u32 oldval, newval;
178 + if (reg == SDHCI_COMMAND) {
179 + /* Write the block now as we are issuing a command */
180 + if (brcmstb_priv->is_blk_shadowed) {
181 + sdhci_brcmstb_32only_writel(host, brcmstb_priv->shadow_blk,
183 + brcmstb_priv->is_blk_shadowed = false;
185 + oldval = brcmstb_priv->shadow_cmd;
186 + brcmstb_priv->is_cmd_shadowed = false;
187 + } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
188 + brcmstb_priv->is_blk_shadowed) {
189 + /* Block size and count are stored in shadow reg */
190 + oldval = brcmstb_priv->shadow_blk;
192 + /* Read reg, all other registers are not shadowed */
193 + oldval = sdhci_brcmstb_32only_readl(host, (reg & ~3));
195 + newval = (oldval & ~mask) | (val << word_shift);
197 + if (reg == SDHCI_TRANSFER_MODE) {
198 + /* Save the transfer mode until the command is issued */
199 + brcmstb_priv->shadow_cmd = newval;
200 + brcmstb_priv->is_cmd_shadowed = true;
201 + } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
202 + /* Save the block info until the command is issued */
203 + brcmstb_priv->shadow_blk = newval;
204 + brcmstb_priv->is_blk_shadowed = true;
206 + /* Command or other regular 32-bit write */
207 + sdhci_brcmstb_32only_writel(host, newval, reg & ~3);
211 +static void sdhci_brcmstb_32only_writeb(struct sdhci_host *host, u8 val, int reg)
213 + u32 oldval = sdhci_brcmstb_32only_readl(host, (reg & ~3));
214 + u32 byte_shift = REG_OFFSET_IN_BITS(reg);
215 + u32 mask = 0xff << byte_shift;
216 + u32 newval = (oldval & ~mask) | (val << byte_shift);
218 + sdhci_brcmstb_32only_writel(host, newval, reg & ~3);
221 +static void sdhci_brcmstb_set_power(struct sdhci_host *host, unsigned char mode,
222 + unsigned short vdd)
224 + if (!IS_ERR(host->mmc->supply.vmmc)) {
225 + struct mmc_host *mmc = host->mmc;
227 + mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
229 + sdhci_set_power_noreg(host, mode, vdd);
232 static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,
235 @@ -123,6 +268,146 @@ static void sdhci_brcmstb_set_uhs_signal
236 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
239 +static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host)
241 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
242 + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
243 + bool want_dll = false;
244 + u32 uhs_mask = (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104);
245 + u32 hsemmc_mask = (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS200_1_2V_SDR |
246 + MMC_CAP2_HS400_1_8V | MMC_CAP2_HS400_1_2V);
249 + if (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)) {
250 + if((host->mmc->caps & uhs_mask) || (host->mmc->caps2 & hsemmc_mask))
255 + * If we want a speed that requires tuning,
256 + * then select the delay line PHY as the clock source.
259 + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);
260 + reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE;
261 + reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE;
262 + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);
265 + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
266 + (host->mmc->caps & MMC_CAP_NEEDS_POLL)) {
267 + /* Force presence */
268 + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);
269 + reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV;
270 + reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN;
271 + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);
273 + /* Enable card detection line */
274 + reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL);
275 + reg &= ~SDIO_CFG_SD_PIN_SEL_MASK;
276 + reg |= SDIO_CFG_SD_PIN_SEL_CARD;
277 + writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_SD_PIN_SEL);
281 +static int bcm2712_init_sd_express(struct sdhci_host *host, struct mmc_ios *ios)
283 + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
284 + struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
285 + struct device *dev = host->mmc->parent;
290 + if (!brcmstb_priv->sde_ioaddr || !brcmstb_priv->sde_ioaddr2)
293 + if (!brcmstb_priv->pinctrl)
296 + /* Turn off the SD clock first */
297 + sdhci_set_clock(host, 0);
299 + /* Disable SD DAT0-3 pulls */
300 + pinctrl_select_state(brcmstb_priv->pinctrl, brcmstb_priv->pins_sdex);
302 + ctrl_val = readl(brcmstb_priv->sde_ioaddr);
303 + dev_dbg(dev, "ctrl_val 1 %08x\n", ctrl_val);
305 + /* Tri-state the SD pins */
306 + ctrl_val |= 0x1ff8;
307 + writel(ctrl_val, brcmstb_priv->sde_ioaddr);
308 + dev_dbg(dev, "ctrl_val 1->%08x (%08x)\n", ctrl_val, readl(brcmstb_priv->sde_ioaddr));
309 + /* Let voltages settle */
312 + /* Enable the PCIe sideband pins */
313 + ctrl_val &= ~0x6000;
314 + writel(ctrl_val, brcmstb_priv->sde_ioaddr);
315 + dev_dbg(dev, "ctrl_val 1->%08x (%08x)\n", ctrl_val, readl(brcmstb_priv->sde_ioaddr));
316 + /* Let voltages settle */
319 + /* Turn on the 1v8 VDD2 regulator */
320 + ret = regulator_enable(brcmstb_priv->sde_1v8);
324 + /* Wait for Tpvcrl */
327 + /* Sample DAT2 (CLKREQ#) - if low, card is in PCIe mode */
328 + present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
329 + present_state = (present_state & SDHCI_DATA_LVL_MASK) >> SDHCI_DATA_LVL_SHIFT;
330 + dev_dbg(dev, "state = 0x%08x\n", present_state);
332 + if (present_state & BIT(2)) {
333 + dev_err(dev, "DAT2 still high, abandoning SDex switch\n");
337 + /* Turn on the LCPLL PTEST mux */
338 + ctrl_val = readl(brcmstb_priv->sde_ioaddr2 + 20); // misc5
339 + ctrl_val &= ~(0x7 << 7);
340 + ctrl_val |= 3 << 7;
341 + writel(ctrl_val, brcmstb_priv->sde_ioaddr2 + 20);
342 + dev_dbg(dev, "misc 5->%08x (%08x)\n", ctrl_val, readl(brcmstb_priv->sde_ioaddr2 + 20));
344 + /* PTEST diff driver enable */
345 + ctrl_val = readl(brcmstb_priv->sde_ioaddr2);
346 + ctrl_val |= BIT(21);
347 + writel(ctrl_val, brcmstb_priv->sde_ioaddr2);
349 + dev_dbg(dev, "misc 0->%08x (%08x)\n", ctrl_val, readl(brcmstb_priv->sde_ioaddr2));
351 + /* Wait for more than the minimum Tpvpgl time */
354 + if (brcmstb_priv->sde_pcie) {
355 + struct of_changeset changeset;
356 + static struct property okay_property = {
362 + /* Enable the pcie controller */
363 + of_changeset_init(&changeset);
364 + ret = of_changeset_update_property(&changeset,
365 + brcmstb_priv->sde_pcie,
368 + dev_err(dev, "%s: failed to update property - %d\n", __func__,
372 + ret = of_changeset_apply(&changeset);
375 + dev_dbg(dev, "%s -> %d\n", __func__, ret);
379 static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)
381 sdhci_dumpregs(mmc_priv(mmc));
382 @@ -155,6 +440,21 @@ static struct sdhci_ops sdhci_brcmstb_op
383 .set_uhs_signaling = sdhci_set_uhs_signaling,
386 +static struct sdhci_ops sdhci_brcmstb_ops_2712 = {
387 + .read_l = sdhci_brcmstb_32only_readl,
388 + .read_w = sdhci_brcmstb_32only_readw,
389 + .read_b = sdhci_brcmstb_32only_readb,
390 + .write_l = sdhci_brcmstb_32only_writel,
391 + .write_w = sdhci_brcmstb_32only_writew,
392 + .write_b = sdhci_brcmstb_32only_writeb,
393 + .set_clock = sdhci_set_clock,
394 + .set_power = sdhci_brcmstb_set_power,
395 + .set_bus_width = sdhci_set_bus_width,
396 + .reset = sdhci_reset,
397 + .set_uhs_signaling = sdhci_set_uhs_signaling,
398 + .init_sd_express = bcm2712_init_sd_express,
401 static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
402 .set_clock = sdhci_brcmstb_set_clock,
403 .set_bus_width = sdhci_set_bus_width,
404 @@ -179,10 +479,16 @@ static const struct brcmstb_match_priv m
405 .ops = &sdhci_brcmstb_ops_7216,
408 +static const struct brcmstb_match_priv match_priv_2712 = {
409 + .cfginit = sdhci_brcmstb_cfginit_2712,
410 + .ops = &sdhci_brcmstb_ops_2712,
413 static const struct of_device_id sdhci_brcm_of_match[] = {
414 { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
415 { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
416 { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
417 + { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 },
421 @@ -256,6 +562,7 @@ static int sdhci_brcmstb_probe(struct pl
422 u32 actual_clock_mhz;
423 struct sdhci_host *host;
424 struct resource *iomem;
425 + bool no_pinctrl = false;
427 struct clk *base_clk = NULL;
429 @@ -290,6 +597,11 @@ static int sdhci_brcmstb_probe(struct pl
430 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
433 + priv->sde_pcie = of_parse_phandle(pdev->dev.of_node,
435 + if (priv->sde_pcie)
436 + priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_SD_EXPRESS;
438 /* Map in the non-standard CFG registers */
439 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
440 priv->cfg_regs = devm_ioremap_resource(&pdev->dev, iomem);
441 @@ -303,6 +615,43 @@ static int sdhci_brcmstb_probe(struct pl
445 + priv->sde_1v8 = devm_regulator_get_optional(&pdev->dev, "sde-1v8");
446 + if (IS_ERR(priv->sde_1v8))
447 + priv->flags &= ~BRCMSTB_PRIV_FLAGS_HAS_SD_EXPRESS;
449 + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 2);
451 + priv->sde_ioaddr = devm_ioremap_resource(&pdev->dev, iomem);
452 + if (IS_ERR(priv->sde_ioaddr))
453 + priv->sde_ioaddr = NULL;
456 + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 3);
458 + priv->sde_ioaddr2 = devm_ioremap_resource(&pdev->dev, iomem);
459 + if (IS_ERR(priv->sde_ioaddr2))
460 + priv->sde_ioaddr = NULL;
463 + priv->pinctrl = devm_pinctrl_get(&pdev->dev);
464 + if (IS_ERR(priv->pinctrl)) {
467 + priv->pins_default = pinctrl_lookup_state(priv->pinctrl, "default");
468 + if (IS_ERR(priv->pins_default)) {
469 + dev_dbg(&pdev->dev, "No pinctrl default state\n");
472 + priv->pins_sdex = pinctrl_lookup_state(priv->pinctrl, "sd-express");
473 + if (IS_ERR(priv->pins_sdex)) {
474 + dev_dbg(&pdev->dev, "No pinctrl sd-express state\n");
477 + if (no_pinctrl || !priv->sde_ioaddr || !priv->sde_ioaddr2) {
478 + priv->pinctrl = NULL;
479 + priv->flags &= ~BRCMSTB_PRIV_FLAGS_HAS_SD_EXPRESS;
483 * Automatic clock gating does not work for SD cards that may
484 * voltage switch so only enable it for non-removable devices.
485 @@ -319,6 +668,13 @@ static int sdhci_brcmstb_probe(struct pl
486 (host->mmc->caps2 & MMC_CAP2_HS400_ES))
487 host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;
489 + if (host->ops->init_sd_express &&
490 + (priv->flags & BRCMSTB_PRIV_FLAGS_HAS_SD_EXPRESS))
491 + host->mmc->caps2 |= MMC_CAP2_SD_EXP;
493 + if(match_priv->cfginit)
494 + match_priv->cfginit(host);
497 * Supply the existing CAPS, but clear the UHS modes. This
498 * will allow these modes to be specified by device tree