target/linux/bcm27xx/patches-6.1/950-0862-irqchip-irq-bcm2712-mip-Support-for-2712-s-MIP.patch

   1 From 89b748416358e4e04765b9a4f20e1c3d256b9d9e Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.com>
   3 Date: Wed, 28 Jul 2021 11:13:39 +0100
   4 Subject: [PATCH] irqchip: irq-bcm2712-mip: Support for 2712's MIP
   5
   6 irqchip: irq-bcm2712-mip: specify bitmap search size as ilog2(N) not N
   7
   8 Freeing also has the same interface.
   9
  10 irqchip: irq-bcm2712-mip: Fix build warnings
  11
  12 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  13
  14 irqchip: bcm2712-mip: add a quick hack to optionally shift MSI vectors
  15
  16 There are two MIP peripherals in bcm2712, the first gets a first-class
  17 treatment where 64 consecutive GIC SPIs are assigned to all 64 output
  18 vectors. The second gets an agglomeration of 17 GIC SPIs, but only 8 of
  19 these are consecutive starting at the 8th output vector.
  20
  21 For now, allow the use of this smaller contiguous range within a larger
  22 whole.
  23
  24 Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
  25 ---
  26  drivers/irqchip/Kconfig           |   8 +
  27  drivers/irqchip/Makefile          |   1 +
  28  drivers/irqchip/irq-bcm2712-mip.c | 325 ++++++++++++++++++++++++++++++
  29  3 files changed, 334 insertions(+)
  30  create mode 100644 drivers/irqchip/irq-bcm2712-mip.c
  31
  32 --- a/drivers/irqchip/Kconfig
  33 +++ b/drivers/irqchip/Kconfig
  34 @@ -109,6 +109,14 @@ config I8259
  35         bool
  36         select IRQ_DOMAIN
  37
  38 +config BCM2712_MIP
  39 +       bool "Broadcom 2712 MSI-X Interrupt Peripheral support"
  40 +       depends on ARM_GIC
  41 +       select GENERIC_IRQ_CHIP
  42 +       select IRQ_DOMAIN
  43 +       help
  44 +         Enable support for the Broadcom BCM2712 MSI-X target peripheral.
  45 +
  46  config BCM6345_L1_IRQ
  47         bool
  48         select GENERIC_IRQ_CHIP
  49 --- a/drivers/irqchip/Makefile
  50 +++ b/drivers/irqchip/Makefile
  51 @@ -63,6 +63,7 @@ obj-$(CONFIG_XTENSA_MX)                       += irq-xtensa-
  52  obj-$(CONFIG_XILINX_INTC)              += irq-xilinx-intc.o
  53  obj-$(CONFIG_IRQ_CROSSBAR)             += irq-crossbar.o
  54  obj-$(CONFIG_SOC_VF610)                        += irq-vf610-mscm-ir.o
  55 +obj-$(CONFIG_BCM2712_MIP)              += irq-bcm2712-mip.o
  56  obj-$(CONFIG_BCM6345_L1_IRQ)           += irq-bcm6345-l1.o
  57  obj-$(CONFIG_BCM7038_L1_IRQ)           += irq-bcm7038-l1.o
  58  obj-$(CONFIG_BCM7120_L2_IRQ)           += irq-bcm7120-l2.o
  59 --- /dev/null
  60 +++ b/drivers/irqchip/irq-bcm2712-mip.c
  61 @@ -0,0 +1,325 @@
  62 +// SPDX-License-Identifier: GPL-2.0-only
  63 +/*
  64 + * Copyright (C) 2021 Raspberry Pi Ltd., All Rights Reserved.
  65 + */
  66 +
  67 +#include <linux/pci.h>
  68 +#include <linux/msi.h>
  69 +#include <linux/of.h>
  70 +#include <linux/of_address.h>
  71 +#include <linux/of_irq.h>
  72 +#include <linux/of_pci.h>
  73 +
  74 +#include <linux/irqchip.h>
  75 +
  76 +#define MIP_INT_RAISED         0x00
  77 +#define MIP_INT_CLEARED                0x10
  78 +#define MIP_INT_CFGL_HOST      0x20
  79 +#define MIP_INT_CFGH_HOST      0x30
  80 +#define MIP_INT_MASKL_HOST     0x40
  81 +#define MIP_INT_MASKH_HOST     0x50
  82 +#define MIP_INT_MASKL_VPU      0x60
  83 +#define MIP_INT_MASKH_VPU      0x70
  84 +#define MIP_INT_STATUSL_HOST   0x80
  85 +#define MIP_INT_STATUSH_HOST   0x90
  86 +#define MIP_INT_STATUSL_VPU    0xa0
  87 +#define MIP_INT_STATUSH_VPU    0xb0
  88 +
  89 +struct mip_priv {
  90 +       spinlock_t msi_map_lock;
  91 +       spinlock_t hw_lock;
  92 +       void * __iomem base;
  93 +       phys_addr_t msg_addr;
  94 +       u32 msi_base;           /* The SGI number that MSIs start */
  95 +       u32 num_msis;           /* The number of SGIs for MSIs */
  96 +       u32 msi_offset;         /* Shift the allocated msi up by N */
  97 +       unsigned long *msi_map;
  98 +};
  99 +
 100 +static void mip_mask_msi_irq(struct irq_data *d)
 101 +{
 102 +       pci_msi_mask_irq(d);
 103 +       irq_chip_mask_parent(d);
 104 +}
 105 +
 106 +static void mip_unmask_msi_irq(struct irq_data *d)
 107 +{
 108 +       pci_msi_unmask_irq(d);
 109 +       irq_chip_unmask_parent(d);
 110 +}
 111 +
 112 +static void mip_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
 113 +{
 114 +       struct mip_priv *priv = irq_data_get_irq_chip_data(d);
 115 +
 116 +       msg->address_hi = upper_32_bits(priv->msg_addr);
 117 +       msg->address_lo = lower_32_bits(priv->msg_addr);
 118 +       msg->data = d->hwirq;
 119 +}
 120 +
 121 +// The "bus-specific" irq_chip (the MIP doesn't _have_ to be used with PCIe)
 122 +
 123 +static struct irq_chip mip_msi_irq_chip = {
 124 +       .name                   = "MIP-MSI",
 125 +       .irq_unmask             = mip_unmask_msi_irq,
 126 +       .irq_mask               = mip_mask_msi_irq,
 127 +       .irq_eoi                = irq_chip_eoi_parent,
 128 +       .irq_set_affinity       = irq_chip_set_affinity_parent,
 129 +};
 130 +
 131 +static struct msi_domain_info mip_msi_domain_info = {
 132 +       .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 133 +                  MSI_FLAG_PCI_MSIX),
 134 +       .chip   = &mip_msi_irq_chip,
 135 +};
 136 +
 137 +// The "middle" irq_chip (the hardware control part)
 138 +
 139 +static struct irq_chip mip_irq_chip = {
 140 +       .name                   = "MIP",
 141 +       .irq_mask               = irq_chip_mask_parent,
 142 +       .irq_unmask             = irq_chip_unmask_parent,
 143 +       .irq_eoi                = irq_chip_eoi_parent,
 144 +       .irq_set_affinity       = irq_chip_set_affinity_parent,
 145 +       .irq_set_type           = irq_chip_set_type_parent,
 146 +       .irq_compose_msi_msg    = mip_compose_msi_msg,
 147 +};
 148 +
 149 +
 150 +// And a domain to connect it to its parent (the GIC)
 151 +
 152 +static int mip_irq_domain_alloc(struct irq_domain *domain,
 153 +                               unsigned int virq, unsigned int nr_irqs,
 154 +                               void *args)
 155 +{
 156 +       struct mip_priv *priv = domain->host_data;
 157 +       struct irq_fwspec fwspec;
 158 +       struct irq_data *irqd;
 159 +       int hwirq, ret, i;
 160 +
 161 +       spin_lock(&priv->msi_map_lock);
 162 +
 163 +       hwirq = bitmap_find_free_region(priv->msi_map, priv->num_msis, ilog2(nr_irqs));
 164 +
 165 +       spin_unlock(&priv->msi_map_lock);
 166 +
 167 +       if (hwirq < 0)
 168 +               return -ENOSPC;
 169 +
 170 +       hwirq += priv->msi_offset;
 171 +       fwspec.fwnode = domain->parent->fwnode;
 172 +       fwspec.param_count = 3;
 173 +       fwspec.param[0] = 0;
 174 +       fwspec.param[1] = hwirq + priv->msi_base;
 175 +       fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
 176 +
 177 +       ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &fwspec);
 178 +       if (ret)
 179 +           return ret;
 180 +
 181 +       for (i = 0; i < nr_irqs; i++) {
 182 +               irqd = irq_domain_get_irq_data(domain->parent, virq + i);
 183 +               irqd->chip->irq_set_type(irqd, IRQ_TYPE_EDGE_RISING);
 184 +
 185 +               irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
 186 +                                             &mip_irq_chip, priv);
 187 +               irqd = irq_get_irq_data(virq + i);
 188 +               irqd_set_single_target(irqd);
 189 +               irqd_set_affinity_on_activate(irqd);
 190 +       }
 191 +
 192 +       return 0;
 193 +}
 194 +
 195 +static void mip_irq_domain_free(struct irq_domain *domain,
 196 +                               unsigned int virq, unsigned int nr_irqs)
 197 +{
 198 +       struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 199 +       struct mip_priv *priv = irq_data_get_irq_chip_data(d);
 200 +
 201 +       irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 202 +       d->hwirq -= priv->msi_offset;
 203 +
 204 +       spin_lock(&priv->msi_map_lock);
 205 +
 206 +       bitmap_release_region(priv->msi_map, d->hwirq, ilog2(nr_irqs));
 207 +
 208 +       spin_unlock(&priv->msi_map_lock);
 209 +}
 210 +
 211 +#if 0
 212 +static int mip_irq_domain_activate(struct irq_domain *domain,
 213 +                                  struct irq_data *d, bool reserve)
 214 +{
 215 +       struct mip_priv *priv = irq_data_get_irq_chip_data(d);
 216 +       unsigned long flags;
 217 +       unsigned int irq = d->hwirq;
 218 +       void *__iomem reg = priv->base +
 219 +               ((irq < 32) ? MIP_INT_MASKL_HOST : MIP_INT_MASKH_HOST);
 220 +       u32 val;
 221 +
 222 +       spin_lock_irqsave(&priv->hw_lock, flags);
 223 +       val = readl(reg);
 224 +       val &= ~(1 << (irq % 32)); // Clear the mask
 225 +       writel(val, reg);
 226 +       spin_unlock_irqrestore(&priv->hw_lock, flags);
 227 +       return 0;
 228 +}
 229 +
 230 +static void mip_irq_domain_deactivate(struct irq_domain *domain,
 231 +                                     struct irq_data *d)
 232 +{
 233 +       struct mip_priv *priv = irq_data_get_irq_chip_data(d);
 234 +       unsigned long flags;
 235 +       unsigned int irq = d->hwirq - priv->msi_base;
 236 +       void *__iomem reg = priv->base +
 237 +               ((irq < 32) ? MIP_INT_MASKL_HOST : MIP_INT_MASKH_HOST);
 238 +       u32 val;
 239 +
 240 +       spin_lock_irqsave(&priv->hw_lock, flags);
 241 +       val = readl(reg);
 242 +       val |= (1 << (irq % 32)); // Mask it out
 243 +       writel(val, reg);
 244 +       spin_unlock_irqrestore(&priv->hw_lock, flags);
 245 +}
 246 +#endif
 247 +
 248 +static const struct irq_domain_ops mip_irq_domain_ops = {
 249 +       .alloc          = mip_irq_domain_alloc,
 250 +       .free           = mip_irq_domain_free,
 251 +       //.activate     = mip_irq_domain_activate,
 252 +       //.deactivate   = mip_irq_domain_deactivate,
 253 +};
 254 +
 255 +static int mip_init_domains(struct mip_priv *priv,
 256 +                           struct device_node *node)
 257 +{
 258 +       struct irq_domain *middle_domain, *msi_domain, *gic_domain;
 259 +       struct device_node *gic_node;
 260 +
 261 +       gic_node = of_irq_find_parent(node);
 262 +       if (!gic_node) {
 263 +               pr_err("Failed to find the GIC node\n");
 264 +               return -ENODEV;
 265 +       }
 266 +
 267 +       gic_domain = irq_find_host(gic_node);
 268 +       if (!gic_domain) {
 269 +               pr_err("Failed to find the GIC domain\n");
 270 +               return -ENXIO;
 271 +       }
 272 +
 273 +       middle_domain = irq_domain_add_tree(NULL,
 274 +                                           &mip_irq_domain_ops,
 275 +                                           priv);
 276 +       if (!middle_domain) {
 277 +               pr_err("Failed to create the MIP middle domain\n");
 278 +               return -ENOMEM;
 279 +       }
 280 +
 281 +       middle_domain->parent = gic_domain;
 282 +
 283 +       msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node),
 284 +                                              &mip_msi_domain_info,
 285 +                                              middle_domain);
 286 +       if (!msi_domain) {
 287 +               pr_err("Failed to create MSI domain\n");
 288 +               irq_domain_remove(middle_domain);
 289 +               return -ENOMEM;
 290 +       }
 291 +
 292 +       return 0;
 293 +}
 294 +
 295 +static int __init mip_of_msi_init(struct device_node *node,
 296 +                                 struct device_node *parent)
 297 +{
 298 +       struct mip_priv *priv;
 299 +       struct resource res;
 300 +       int ret;
 301 +
 302 +       priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 303 +       if (!priv)
 304 +               return -ENOMEM;
 305 +
 306 +       spin_lock_init(&priv->msi_map_lock);
 307 +       spin_lock_init(&priv->hw_lock);
 308 +
 309 +       ret = of_address_to_resource(node, 0, &res);
 310 +       if (ret) {
 311 +               pr_err("Failed to allocate resource\n");
 312 +               goto err_priv;
 313 +       }
 314 +
 315 +       if (of_property_read_u32(node, "brcm,msi-base-spi", &priv->msi_base)) {
 316 +               pr_err("Unable to parse MSI base\n");
 317 +               ret = -EINVAL;
 318 +               goto err_priv;
 319 +       }
 320 +
 321 +       if (of_property_read_u32(node, "brcm,msi-num-spis", &priv->num_msis)) {
 322 +               pr_err("Unable to parse MSI numbers\n");
 323 +               ret = -EINVAL;
 324 +               goto err_priv;
 325 +       }
 326 +
 327 +       if (of_property_read_u32(node, "brcm,msi-offset", &priv->msi_offset))
 328 +               priv->msi_offset = 0;
 329 +
 330 +       if (of_property_read_u64(node, "brcm,msi-pci-addr", &priv->msg_addr)) {
 331 +               pr_err("Unable to parse MSI address\n");
 332 +               ret = -EINVAL;
 333 +               goto err_priv;
 334 +       }
 335 +
 336 +       priv->base = ioremap(res.start, resource_size(&res));
 337 +       if (!priv->base) {
 338 +               pr_err("Failed to ioremap regs\n");
 339 +               ret = -ENOMEM;
 340 +               goto err_priv;
 341 +       }
 342 +
 343 +       priv->msi_map = kcalloc(BITS_TO_LONGS(priv->num_msis),
 344 +                               sizeof(*priv->msi_map),
 345 +                               GFP_KERNEL);
 346 +       if (!priv->msi_map) {
 347 +               ret = -ENOMEM;
 348 +               goto err_base;
 349 +       }
 350 +
 351 +       pr_debug("Registering %d msixs, starting at %d\n",
 352 +                priv->num_msis, priv->msi_base);
 353 +
 354 +       /*
 355 +        * Begin with all MSI-Xs masked in for the host, masked out for the
 356 +        * VPU, and edge-triggered.
 357 +        */
 358 +       writel(0, priv->base + MIP_INT_MASKL_HOST);
 359 +       writel(0, priv->base + MIP_INT_MASKH_HOST);
 360 +       writel(~0, priv->base + MIP_INT_MASKL_VPU);
 361 +       writel(~0, priv->base + MIP_INT_MASKH_VPU);
 362 +       writel(~0, priv->base + MIP_INT_CFGL_HOST);
 363 +       writel(~0, priv->base + MIP_INT_CFGH_HOST);
 364 +
 365 +       ret = mip_init_domains(priv, node);
 366 +       if (ret) {
 367 +               pr_err("Failed to allocate msi_map\n");
 368 +               goto err_map;
 369 +       }
 370 +
 371 +       return 0;
 372 +
 373 +err_map:
 374 +       kfree(priv->msi_map);
 375 +
 376 +err_base:
 377 +       iounmap(priv->base);
 378 +
 379 +err_priv:
 380 +       kfree(priv);
 381 +
 382 +       pr_err("%s: failed - err %d\n", __func__, ret);
 383 +
 384 +       return ret;
 385 +}
 386 +IRQCHIP_DECLARE(bcm_mip, "brcm,bcm2712-mip-intc", mip_of_msi_init);