1 From 66517cdfea750b89d86f78af55ef773cbd3e005f Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.com>
3 Date: Mon, 10 Oct 2022 14:25:38 +0100
4 Subject: [PATCH] clk: Add rp1 clock driver
6 RP1 contains various PLLs and clocks for driving the hardware
7 blocks, so add a driver to configure these.
9 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
11 drivers/clk/Kconfig | 7 +
12 drivers/clk/Makefile | 1 +
13 drivers/clk/clk-rp1.c | 2085 +++++++++++++++++++++++++++++++
14 include/dt-bindings/clock/rp1.h | 69 +-
15 4 files changed, 2128 insertions(+), 34 deletions(-)
16 create mode 100644 drivers/clk/clk-rp1.c
18 --- a/drivers/clk/Kconfig
19 +++ b/drivers/clk/Kconfig
20 @@ -89,6 +89,13 @@ config COMMON_CLK_RK808
21 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
22 Clkout1 is always on, Clkout2 can off by control register.
24 +config COMMON_CLK_RP1
25 + tristate "Raspberry Pi RP1-based clock support"
26 + depends on PCI || COMPILE_TEST
27 + depends on COMMON_CLK
29 + Enable common clock framework support for Raspberry Pi RP1
31 config COMMON_CLK_HI655X
32 tristate "Clock driver for Hi655x" if EXPERT
33 depends on (MFD_HI655X_PMIC || COMPILE_TEST)
34 --- a/drivers/clk/Makefile
35 +++ b/drivers/clk/Makefile
36 @@ -58,6 +58,7 @@ obj-$(CONFIG_CLK_LS1028A_PLLDIG) += clk-
37 obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
38 obj-$(CONFIG_CLK_QORIQ) += clk-qoriq.o
39 obj-$(CONFIG_COMMON_CLK_RK808) += clk-rk808.o
40 +obj-$(CONFIG_COMMON_CLK_RP1) += clk-rp1.o
41 obj-$(CONFIG_COMMON_CLK_HI655X) += clk-hi655x.o
42 obj-$(CONFIG_COMMON_CLK_S2MPS11) += clk-s2mps11.o
43 obj-$(CONFIG_COMMON_CLK_SCMI) += clk-scmi.o
45 +++ b/drivers/clk/clk-rp1.c
47 +// SPDX-License-Identifier: GPL-2.0+
49 + * Copyright (C) 2023 Raspberry Pi Ltd.
51 + * Clock driver for RP1 PCIe multifunction chip.
54 +#include <linux/clk-provider.h>
55 +#include <linux/clkdev.h>
56 +#include <linux/clk.h>
57 +#include <linux/debugfs.h>
58 +#include <linux/delay.h>
59 +#include <linux/io.h>
60 +#include <linux/math64.h>
61 +#include <linux/module.h>
62 +#include <linux/of_device.h>
63 +#include <linux/platform_device.h>
64 +#include <linux/rp1_platform.h>
65 +#include <linux/slab.h>
67 +#include <asm/div64.h>
69 +#include <dt-bindings/clock/rp1.h>
71 +#define PLL_SYS_CS 0x08000
72 +#define PLL_SYS_PWR 0x08004
73 +#define PLL_SYS_FBDIV_INT 0x08008
74 +#define PLL_SYS_FBDIV_FRAC 0x0800c
75 +#define PLL_SYS_PRIM 0x08010
76 +#define PLL_SYS_SEC 0x08014
78 +#define PLL_AUDIO_CS 0x0c000
79 +#define PLL_AUDIO_PWR 0x0c004
80 +#define PLL_AUDIO_FBDIV_INT 0x0c008
81 +#define PLL_AUDIO_FBDIV_FRAC 0x0c00c
82 +#define PLL_AUDIO_PRIM 0x0c010
83 +#define PLL_AUDIO_SEC 0x0c014
85 +#define PLL_VIDEO_CS 0x10000
86 +#define PLL_VIDEO_PWR 0x10004
87 +#define PLL_VIDEO_FBDIV_INT 0x10008
88 +#define PLL_VIDEO_FBDIV_FRAC 0x1000c
89 +#define PLL_VIDEO_PRIM 0x10010
90 +#define PLL_VIDEO_SEC 0x10014
92 +#define CLK_SYS_CTRL 0x00014
93 +#define CLK_SYS_DIV_INT 0x00018
94 +#define CLK_SYS_SEL 0x00020
96 +#define CLK_SLOW_SYS_CTRL 0x00024
97 +#define CLK_SLOW_SYS_DIV_INT 0x00028
98 +#define CLK_SLOW_SYS_SEL 0x00030
100 +#define CLK_DMA_CTRL 0x00044
101 +#define CLK_DMA_DIV_INT 0x00048
102 +#define CLK_DMA_SEL 0x00050
104 +#define CLK_UART_CTRL 0x00054
105 +#define CLK_UART_DIV_INT 0x00058
106 +#define CLK_UART_SEL 0x00060
108 +#define CLK_ETH_CTRL 0x00064
109 +#define CLK_ETH_DIV_INT 0x00068
110 +#define CLK_ETH_SEL 0x00070
112 +#define CLK_PWM0_CTRL 0x00074
113 +#define CLK_PWM0_DIV_INT 0x00078
114 +#define CLK_PWM0_DIV_FRAC 0x0007c
115 +#define CLK_PWM0_SEL 0x00080
117 +#define CLK_PWM1_CTRL 0x00084
118 +#define CLK_PWM1_DIV_INT 0x00088
119 +#define CLK_PWM1_DIV_FRAC 0x0008c
120 +#define CLK_PWM1_SEL 0x00090
122 +#define CLK_AUDIO_IN_CTRL 0x00094
123 +#define CLK_AUDIO_IN_DIV_INT 0x00098
124 +#define CLK_AUDIO_IN_SEL 0x000a0
126 +#define CLK_AUDIO_OUT_CTRL 0x000a4
127 +#define CLK_AUDIO_OUT_DIV_INT 0x000a8
128 +#define CLK_AUDIO_OUT_SEL 0x000b0
130 +#define CLK_I2S_CTRL 0x000b4
131 +#define CLK_I2S_DIV_INT 0x000b8
132 +#define CLK_I2S_SEL 0x000c0
134 +#define CLK_MIPI0_CFG_CTRL 0x000c4
135 +#define CLK_MIPI0_CFG_DIV_INT 0x000c8
136 +#define CLK_MIPI0_CFG_SEL 0x000d0
138 +#define CLK_MIPI1_CFG_CTRL 0x000d4
139 +#define CLK_MIPI1_CFG_DIV_INT 0x000d8
140 +#define CLK_MIPI1_CFG_SEL 0x000e0
142 +#define CLK_PCIE_AUX_CTRL 0x000e4
143 +#define CLK_PCIE_AUX_DIV_INT 0x000e8
144 +#define CLK_PCIE_AUX_SEL 0x000f0
146 +#define CLK_USBH0_MICROFRAME_CTRL 0x000f4
147 +#define CLK_USBH0_MICROFRAME_DIV_INT 0x000f8
148 +#define CLK_USBH0_MICROFRAME_SEL 0x00100
150 +#define CLK_USBH1_MICROFRAME_CTRL 0x00104
151 +#define CLK_USBH1_MICROFRAME_DIV_INT 0x00108
152 +#define CLK_USBH1_MICROFRAME_SEL 0x00110
154 +#define CLK_USBH0_SUSPEND_CTRL 0x00114
155 +#define CLK_USBH0_SUSPEND_DIV_INT 0x00118
156 +#define CLK_USBH0_SUSPEND_SEL 0x00120
158 +#define CLK_USBH1_SUSPEND_CTRL 0x00124
159 +#define CLK_USBH1_SUSPEND_DIV_INT 0x00128
160 +#define CLK_USBH1_SUSPEND_SEL 0x00130
162 +#define CLK_ETH_TSU_CTRL 0x00134
163 +#define CLK_ETH_TSU_DIV_INT 0x00138
164 +#define CLK_ETH_TSU_SEL 0x00140
166 +#define CLK_ADC_CTRL 0x00144
167 +#define CLK_ADC_DIV_INT 0x00148
168 +#define CLK_ADC_SEL 0x00150
170 +#define CLK_SDIO_TIMER_CTRL 0x00154
171 +#define CLK_SDIO_TIMER_DIV_INT 0x00158
172 +#define CLK_SDIO_TIMER_SEL 0x00160
174 +#define CLK_SDIO_ALT_SRC_CTRL 0x00164
175 +#define CLK_SDIO_ALT_SRC_DIV_INT 0x00168
176 +#define CLK_SDIO_ALT_SRC_SEL 0x00170
178 +#define CLK_GP0_CTRL 0x00174
179 +#define CLK_GP0_DIV_INT 0x00178
180 +#define CLK_GP0_DIV_FRAC 0x0017c
181 +#define CLK_GP0_SEL 0x00180
183 +#define CLK_GP1_CTRL 0x00184
184 +#define CLK_GP1_DIV_INT 0x00188
185 +#define CLK_GP1_DIV_FRAC 0x0018c
186 +#define CLK_GP1_SEL 0x00190
188 +#define CLK_GP2_CTRL 0x00194
189 +#define CLK_GP2_DIV_INT 0x00198
190 +#define CLK_GP2_DIV_FRAC 0x0019c
191 +#define CLK_GP2_SEL 0x001a0
193 +#define CLK_GP3_CTRL 0x001a4
194 +#define CLK_GP3_DIV_INT 0x001a8
195 +#define CLK_GP3_DIV_FRAC 0x001ac
196 +#define CLK_GP3_SEL 0x001b0
198 +#define CLK_GP4_CTRL 0x001b4
199 +#define CLK_GP4_DIV_INT 0x001b8
200 +#define CLK_GP4_DIV_FRAC 0x001bc
201 +#define CLK_GP4_SEL 0x001c0
203 +#define CLK_GP5_CTRL 0x001c4
204 +#define CLK_GP5_DIV_INT 0x001c8
205 +#define CLK_GP5_DIV_FRAC 0x001cc
206 +#define CLK_GP5_SEL 0x001d0
208 +#define CLK_SYS_RESUS_CTRL 0x0020c
210 +#define CLK_SLOW_SYS_RESUS_CTRL 0x00214
212 +#define FC0_REF_KHZ 0x0021c
213 +#define FC0_MIN_KHZ 0x00220
214 +#define FC0_MAX_KHZ 0x00224
215 +#define FC0_DELAY 0x00228
216 +#define FC0_INTERVAL 0x0022c
217 +#define FC0_SRC 0x00230
218 +#define FC0_STATUS 0x00234
219 +#define FC0_RESULT 0x00238
220 +#define FC_SIZE 0x20
222 +#define FC_NUM(idx, off) ((idx) * 32 + (off))
226 +#define VIDEO_CLOCKS_OFFSET 0x4000
227 +#define VIDEO_CLK_VEC_CTRL (VIDEO_CLOCKS_OFFSET + 0x0000)
228 +#define VIDEO_CLK_VEC_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0004)
229 +#define VIDEO_CLK_VEC_SEL (VIDEO_CLOCKS_OFFSET + 0x000c)
230 +#define VIDEO_CLK_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0010)
231 +#define VIDEO_CLK_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0014)
232 +#define VIDEO_CLK_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x001c)
233 +#define VIDEO_CLK_MIPI0_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0020)
234 +#define VIDEO_CLK_MIPI0_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0024)
235 +#define VIDEO_CLK_MIPI0_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0028)
236 +#define VIDEO_CLK_MIPI0_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x002c)
237 +#define VIDEO_CLK_MIPI1_DPI_CTRL (VIDEO_CLOCKS_OFFSET + 0x0030)
238 +#define VIDEO_CLK_MIPI1_DPI_DIV_INT (VIDEO_CLOCKS_OFFSET + 0x0034)
239 +#define VIDEO_CLK_MIPI1_DPI_DIV_FRAC (VIDEO_CLOCKS_OFFSET + 0x0038)
240 +#define VIDEO_CLK_MIPI1_DPI_SEL (VIDEO_CLOCKS_OFFSET + 0x003c)
242 +#define DIV_INT_8BIT_MAX 0x000000ffu /* max divide for most clocks */
243 +#define DIV_INT_16BIT_MAX 0x0000ffffu /* max divide for GPx, PWM */
244 +#define DIV_INT_24BIT_MAX 0x00ffffffu /* max divide for CLK_SYS */
246 +#define FC0_STATUS_DONE BIT(4)
247 +#define FC0_STATUS_RUNNING BIT(8)
248 +#define FC0_RESULT_FRAC_SHIFT 5
250 +#define PLL_PRIM_DIV1_SHIFT 16
251 +#define PLL_PRIM_DIV1_MASK 0x00070000
252 +#define PLL_PRIM_DIV2_SHIFT 12
253 +#define PLL_PRIM_DIV2_MASK 0x00007000
255 +#define PLL_SEC_DIV_SHIFT 8
256 +#define PLL_SEC_DIV_WIDTH 5
257 +#define PLL_SEC_DIV_MASK 0x00001f00
259 +#define PLL_CS_LOCK BIT(31)
260 +#define PLL_CS_REFDIV_SHIFT 0
262 +#define PLL_PWR_PD BIT(0)
263 +#define PLL_PWR_DACPD BIT(1)
264 +#define PLL_PWR_DSMPD BIT(2)
265 +#define PLL_PWR_POSTDIVPD BIT(3)
266 +#define PLL_PWR_4PHASEPD BIT(4)
267 +#define PLL_PWR_VCOPD BIT(5)
268 +#define PLL_PWR_MASK 0x0000003f
270 +#define PLL_SEC_RST BIT(16)
271 +#define PLL_SEC_IMPL BIT(31)
273 +/* PLL phase output for both PRI and SEC */
274 +#define PLL_PH_EN BIT(4)
275 +#define PLL_PH_PHASE_SHIFT 0
277 +#define RP1_PLL_PHASE_0 0
278 +#define RP1_PLL_PHASE_90 1
279 +#define RP1_PLL_PHASE_180 2
280 +#define RP1_PLL_PHASE_270 3
282 +/* Clock fields for all clocks */
283 +#define CLK_CTRL_ENABLE BIT(11)
284 +#define CLK_CTRL_AUXSRC_MASK 0x000003e0
285 +#define CLK_CTRL_AUXSRC_SHIFT 5
286 +#define CLK_CTRL_SRC_SHIFT 0
287 +#define CLK_DIV_FRAC_BITS 16
290 +#define MHz (KHz * KHz)
291 +#define LOCK_TIMEOUT_NS 100000000
292 +#define FC_TIMEOUT_NS 100000000
294 +#define MAX_CLK_PARENTS 8
296 +#define MEASURE_CLOCK_RATE
297 +const char * const fc0_ref_clk_name = "clk_slow_sys";
299 +#define ABS_DIFF(a, b) ((a) > (b) ? (a) - (b) : (b) - (a))
300 +#define DIV_U64_NEAREST(a, b) div_u64(((a) + ((b) >> 1)), (b))
303 + * Names of the reference clock for the pll cores. This name must match
304 + * the DT reference clock-output-name.
306 +static const char *const ref_clock = "xosc";
309 + * Secondary PLL channel output divider table.
310 + * Divider values range from 8 to 19.
311 + * Invalid values default to 19
313 +static const struct clk_div_table pll_sec_div_table[] = {
349 +struct rp1_clockman {
350 + struct device *dev;
351 + void __iomem *regs;
352 + spinlock_t regs_lock; /* spinlock for all clocks */
355 + struct clk_hw_onecell_data onecell;
358 +struct rp1_pll_core_data {
363 + u32 fbdiv_frac_reg;
364 + unsigned long flags;
368 +struct rp1_pll_data {
370 + const char *source_pll;
372 + unsigned long flags;
376 +struct rp1_pll_ph_data {
378 + const char *source_pll;
379 + unsigned int phase;
380 + unsigned int fixed_divider;
382 + unsigned long flags;
386 +struct rp1_pll_divider_data {
388 + const char *source_pll;
390 + unsigned long flags;
394 +struct rp1_clock_data {
396 + const char *const parents[MAX_CLK_PARENTS];
397 + int num_std_parents;
398 + int num_aux_parents;
399 + unsigned long flags;
409 +struct rp1_pll_core {
411 + struct rp1_clockman *clockman;
412 + const struct rp1_pll_core_data *data;
413 + unsigned long cached_rate;
418 + struct clk_divider div;
419 + struct rp1_clockman *clockman;
420 + const struct rp1_pll_data *data;
421 + unsigned long cached_rate;
426 + struct rp1_clockman *clockman;
427 + const struct rp1_pll_ph_data *data;
432 + struct rp1_clockman *clockman;
433 + const struct rp1_clock_data *data;
434 + unsigned long cached_rate;
437 +static void rp1_debugfs_regset(struct rp1_clockman *clockman, u32 base,
438 + const struct debugfs_reg32 *regs,
439 + size_t nregs, struct dentry *dentry)
441 + struct debugfs_regset32 *regset;
443 + regset = devm_kzalloc(clockman->dev, sizeof(*regset), GFP_KERNEL);
447 + regset->regs = regs;
448 + regset->nregs = nregs;
449 + regset->base = clockman->regs + base;
451 + debugfs_create_regset32("regdump", 0444, dentry, regset);
454 +static inline u32 set_register_field(u32 reg, u32 val, u32 mask, u32 shift)
457 + reg |= (val << shift) & mask;
462 +void clockman_write(struct rp1_clockman *clockman, u32 reg, u32 val)
464 + writel(val, clockman->regs + reg);
467 +static inline u32 clockman_read(struct rp1_clockman *clockman, u32 reg)
469 + return readl(clockman->regs + reg);
472 +#ifdef MEASURE_CLOCK_RATE
473 +static unsigned long clockman_measure_clock(struct rp1_clockman *clockman,
474 + const char *clk_name,
475 + unsigned int fc0_src)
477 + struct clk *ref_clk = __clk_lookup(fc0_ref_clk_name);
478 + unsigned long result;
480 + unsigned int fc_idx, fc_offset, fc_src;
482 + fc_idx = fc0_src / 32;
483 + fc_src = fc0_src % 32;
485 + /* fc_src == 0 is invalid. */
486 + if (!fc_src || fc_idx >= FC_COUNT)
489 + fc_offset = fc_idx * FC_SIZE;
491 + /* Ensure the frequency counter is idle. */
492 + timeout = ktime_add_ns(ktime_get(), FC_TIMEOUT_NS);
493 + while (clockman_read(clockman, fc_offset + FC0_STATUS) & FC0_STATUS_RUNNING) {
494 + if (ktime_after(ktime_get(), timeout)) {
495 + dev_err(clockman->dev, "%s: FC0 busy timeout\n",
502 + spin_lock(&clockman->regs_lock);
503 + clockman_write(clockman, fc_offset + FC0_REF_KHZ,
504 + clk_get_rate(ref_clk) / KHz);
505 + clockman_write(clockman, fc_offset + FC0_MIN_KHZ, 0);
506 + clockman_write(clockman, fc_offset + FC0_MAX_KHZ, 0x1ffffff);
507 + clockman_write(clockman, fc_offset + FC0_INTERVAL, 8);
508 + clockman_write(clockman, fc_offset + FC0_DELAY, 7);
509 + clockman_write(clockman, fc_offset + FC0_SRC, fc_src);
510 + spin_unlock(&clockman->regs_lock);
512 + /* Ensure the frequency counter is idle. */
513 + timeout = ktime_add_ns(ktime_get(), FC_TIMEOUT_NS);
514 + while (!(clockman_read(clockman, fc_offset + FC0_STATUS) & FC0_STATUS_DONE)) {
515 + if (ktime_after(ktime_get(), timeout)) {
516 + dev_err(clockman->dev, "%s: FC0 wait timeout\n",
523 + result = clockman_read(clockman, fc_offset + FC0_RESULT);
526 + spin_lock(&clockman->regs_lock);
527 + clockman_write(clockman, fc_offset + FC0_SRC, 0);
528 + spin_unlock(&clockman->regs_lock);
534 +static int rp1_pll_core_is_on(struct clk_hw *hw)
536 + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);
537 + struct rp1_clockman *clockman = pll_core->clockman;
538 + const struct rp1_pll_core_data *data = pll_core->data;
539 + u32 pwr = clockman_read(clockman, data->pwr_reg);
541 + return (pwr & PLL_PWR_PD) || (pwr & PLL_PWR_POSTDIVPD);
544 +static int rp1_pll_core_on(struct clk_hw *hw)
546 + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);
547 + struct rp1_clockman *clockman = pll_core->clockman;
548 + const struct rp1_pll_core_data *data = pll_core->data;
552 + spin_lock(&clockman->regs_lock);
554 + if (!(clockman_read(clockman, data->cs_reg) & PLL_CS_LOCK)) {
555 + /* Reset to a known state. */
556 + clockman_write(clockman, data->pwr_reg, PLL_PWR_MASK);
557 + clockman_write(clockman, data->fbdiv_int_reg, 20);
558 + clockman_write(clockman, data->fbdiv_frac_reg, 0);
559 + clockman_write(clockman, data->cs_reg, 1 << PLL_CS_REFDIV_SHIFT);
562 + /* Come out of reset. */
563 + fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg);
564 + clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD);
565 + spin_unlock(&clockman->regs_lock);
567 + /* Wait for the PLL to lock. */
568 + timeout = ktime_add_ns(ktime_get(), LOCK_TIMEOUT_NS);
569 + while (!(clockman_read(clockman, data->cs_reg) & PLL_CS_LOCK)) {
570 + if (ktime_after(ktime_get(), timeout)) {
571 + dev_err(clockman->dev, "%s: can't lock PLL\n",
572 + clk_hw_get_name(hw));
581 +static void rp1_pll_core_off(struct clk_hw *hw)
583 + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);
584 + struct rp1_clockman *clockman = pll_core->clockman;
585 + const struct rp1_pll_core_data *data = pll_core->data;
587 + spin_lock(&clockman->regs_lock);
588 + clockman_write(clockman, data->pwr_reg, 0);
589 + spin_unlock(&clockman->regs_lock);
592 +static inline unsigned long get_pll_core_divider(struct clk_hw *hw,
593 + unsigned long rate,
594 + unsigned long parent_rate,
595 + u32 *div_int, u32 *div_frac)
597 + unsigned long calc_rate;
598 + u32 fbdiv_int, fbdiv_frac;
599 + u64 div_fp64; /* 32.32 fixed point fraction. */
601 + /* Factor of reference clock to VCO frequency. */
602 + div_fp64 = (u64)(rate) << 32;
603 + div_fp64 = DIV_U64_NEAREST(div_fp64, parent_rate);
605 + /* Round the fractional component at 24 bits. */
606 + div_fp64 += 1 << (32 - 24 - 1);
608 + fbdiv_int = div_fp64 >> 32;
609 + fbdiv_frac = (div_fp64 >> (32 - 24)) & 0xffffff;
612 + ((u64)parent_rate * (((u64)fbdiv_int << 24) + fbdiv_frac) + (1 << 23)) >> 24;
614 + *div_int = fbdiv_int;
615 + *div_frac = fbdiv_frac;
620 +static int rp1_pll_core_set_rate(struct clk_hw *hw,
621 + unsigned long rate, unsigned long parent_rate)
623 + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);
624 + struct rp1_clockman *clockman = pll_core->clockman;
625 + const struct rp1_pll_core_data *data = pll_core->data;
626 + unsigned long calc_rate;
627 + u32 fbdiv_int, fbdiv_frac;
629 + // todo: is this needed??
632 + /* Disable dividers to start with. */
633 + spin_lock(&clockman->regs_lock);
634 + clockman_write(clockman, data->fbdiv_int_reg, 0);
635 + clockman_write(clockman, data->fbdiv_frac_reg, 0);
636 + spin_unlock(&clockman->regs_lock);
638 + calc_rate = get_pll_core_divider(hw, rate, parent_rate,
639 + &fbdiv_int, &fbdiv_frac);
641 + spin_lock(&clockman->regs_lock);
642 + clockman_write(clockman, data->pwr_reg, fbdiv_frac ? 0 : PLL_PWR_DSMPD);
643 + clockman_write(clockman, data->fbdiv_int_reg, fbdiv_int);
644 + clockman_write(clockman, data->fbdiv_frac_reg, fbdiv_frac);
645 + spin_unlock(&clockman->regs_lock);
647 + /* Check that reference frequency is no greater than VCO / 16. */
648 + BUG_ON(parent_rate > (rate / 16));
650 + pll_core->cached_rate = calc_rate;
652 + spin_lock(&clockman->regs_lock);
653 + /* Don't need to divide ref unless parent_rate > (output freq / 16) */
654 + clockman_write(clockman, data->cs_reg,
655 + clockman_read(clockman, data->cs_reg) |
656 + (1 << PLL_CS_REFDIV_SHIFT));
657 + spin_unlock(&clockman->regs_lock);
662 +static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw,
663 + unsigned long parent_rate)
665 + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);
666 + struct rp1_clockman *clockman = pll_core->clockman;
667 + const struct rp1_pll_core_data *data = pll_core->data;
668 + u32 fbdiv_int, fbdiv_frac;
669 + unsigned long calc_rate;
671 + fbdiv_int = clockman_read(clockman, data->fbdiv_int_reg);
672 + fbdiv_frac = clockman_read(clockman, data->fbdiv_frac_reg);
674 + ((u64)parent_rate * (((u64)fbdiv_int << 24) + fbdiv_frac) + (1 << 23)) >> 24;
679 +static long rp1_pll_core_round_rate(struct clk_hw *hw, unsigned long rate,
680 + unsigned long *parent_rate)
682 + u32 fbdiv_int, fbdiv_frac;
685 + calc_rate = get_pll_core_divider(hw, rate, *parent_rate,
686 + &fbdiv_int, &fbdiv_frac);
690 +static void rp1_pll_core_debug_init(struct clk_hw *hw, struct dentry *dentry)
692 + struct rp1_pll_core *pll_core = container_of(hw, struct rp1_pll_core, hw);
693 + struct rp1_clockman *clockman = pll_core->clockman;
694 + const struct rp1_pll_core_data *data = pll_core->data;
695 + struct debugfs_reg32 *regs;
697 + regs = devm_kcalloc(clockman->dev, 4, sizeof(*regs), GFP_KERNEL);
701 + regs[0].name = "cs";
702 + regs[0].offset = data->cs_reg;
703 + regs[1].name = "pwr";
704 + regs[1].offset = data->pwr_reg;
705 + regs[2].name = "fbdiv_int";
706 + regs[2].offset = data->fbdiv_int_reg;
707 + regs[3].name = "fbdiv_frac";
708 + regs[3].offset = data->fbdiv_frac_reg;
710 + rp1_debugfs_regset(clockman, 0, regs, 4, dentry);
713 +static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate,
714 + u32 *divider1, u32 *divider2)
716 + unsigned int div1, div2;
717 + unsigned int best_div1 = 7, best_div2 = 7;
718 + unsigned long best_rate_diff =
719 + ABS_DIFF(DIV_ROUND_CLOSEST(parent_rate, best_div1 * best_div2), rate);
720 + long rate_diff, calc_rate;
722 + for (div1 = 1; div1 <= 7; div1++) {
723 + for (div2 = 1; div2 <= div1; div2++) {
724 + calc_rate = DIV_ROUND_CLOSEST(parent_rate, div1 * div2);
725 + rate_diff = ABS_DIFF(calc_rate, rate);
727 + if (calc_rate == rate) {
731 + } else if (rate_diff < best_rate_diff) {
734 + best_rate_diff = rate_diff;
740 + *divider1 = best_div1;
741 + *divider2 = best_div2;
744 +static int rp1_pll_set_rate(struct clk_hw *hw,
745 + unsigned long rate, unsigned long parent_rate)
747 + struct rp1_pll *pll = container_of(hw, struct rp1_pll, hw);
748 + struct rp1_clockman *clockman = pll->clockman;
749 + const struct rp1_pll_data *data = pll->data;
750 + u32 prim, prim_div1, prim_div2;
752 + get_pll_prim_dividers(rate, parent_rate, &prim_div1, &prim_div2);
754 + spin_lock(&clockman->regs_lock);
755 + prim = clockman_read(clockman, data->ctrl_reg);
756 + prim = set_register_field(prim, prim_div1, PLL_PRIM_DIV1_MASK,
757 + PLL_PRIM_DIV1_SHIFT);
758 + prim = set_register_field(prim, prim_div2, PLL_PRIM_DIV2_MASK,
759 + PLL_PRIM_DIV2_SHIFT);
760 + clockman_write(clockman, data->ctrl_reg, prim);
761 + spin_unlock(&clockman->regs_lock);
763 +#ifdef MEASURE_CLOCK_RATE
764 + clockman_measure_clock(clockman, data->name, data->fc0_src);
769 +static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw,
770 + unsigned long parent_rate)
772 + struct rp1_pll *pll = container_of(hw, struct rp1_pll, hw);
773 + struct rp1_clockman *clockman = pll->clockman;
774 + const struct rp1_pll_data *data = pll->data;
775 + u32 prim, prim_div1, prim_div2;
777 + prim = clockman_read(clockman, data->ctrl_reg);
778 + prim_div1 = (prim & PLL_PRIM_DIV1_MASK) >> PLL_PRIM_DIV1_SHIFT;
779 + prim_div2 = (prim & PLL_PRIM_DIV2_MASK) >> PLL_PRIM_DIV2_SHIFT;
781 + if (!prim_div1 || !prim_div2) {
782 + dev_err(clockman->dev, "%s: (%s) zero divider value\n",
783 + __func__, data->name);
787 + return DIV_ROUND_CLOSEST(parent_rate, prim_div1 * prim_div2);
790 +static long rp1_pll_round_rate(struct clk_hw *hw, unsigned long rate,
791 + unsigned long *parent_rate)
795 + get_pll_prim_dividers(rate, *parent_rate, &div1, &div2);
797 + return DIV_ROUND_CLOSEST(*parent_rate, div1 * div2);
800 +static void rp1_pll_debug_init(struct clk_hw *hw,
801 + struct dentry *dentry)
803 + struct rp1_pll *pll = container_of(hw, struct rp1_pll, hw);
804 + struct rp1_clockman *clockman = pll->clockman;
805 + const struct rp1_pll_data *data = pll->data;
806 + struct debugfs_reg32 *regs;
808 + regs = devm_kcalloc(clockman->dev, 1, sizeof(*regs), GFP_KERNEL);
812 + regs[0].name = "prim";
813 + regs[0].offset = data->ctrl_reg;
815 + rp1_debugfs_regset(clockman, 0, regs, 1, dentry);
818 +static int rp1_pll_ph_is_on(struct clk_hw *hw)
820 + struct rp1_pll_ph *pll = container_of(hw, struct rp1_pll_ph, hw);
821 + struct rp1_clockman *clockman = pll->clockman;
822 + const struct rp1_pll_ph_data *data = pll->data;
824 + return !!(clockman_read(clockman, data->ph_reg) & PLL_PH_EN);
827 +static int rp1_pll_ph_on(struct clk_hw *hw)
829 + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw);
830 + struct rp1_clockman *clockman = pll_ph->clockman;
831 + const struct rp1_pll_ph_data *data = pll_ph->data;
834 + /* todo: ensure pri/sec is enabled! */
835 + spin_lock(&clockman->regs_lock);
836 + ph_reg = clockman_read(clockman, data->ph_reg);
837 + ph_reg |= data->phase << PLL_PH_PHASE_SHIFT;
838 + ph_reg |= PLL_PH_EN;
839 + clockman_write(clockman, data->ph_reg, ph_reg);
840 + spin_unlock(&clockman->regs_lock);
842 +#ifdef MEASURE_CLOCK_RATE
843 + clockman_measure_clock(clockman, data->name, data->fc0_src);
848 +static void rp1_pll_ph_off(struct clk_hw *hw)
850 + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw);
851 + struct rp1_clockman *clockman = pll_ph->clockman;
852 + const struct rp1_pll_ph_data *data = pll_ph->data;
854 + spin_lock(&clockman->regs_lock);
855 + clockman_write(clockman, data->ph_reg,
856 + clockman_read(clockman, data->ph_reg) & ~PLL_PH_EN);
857 + spin_unlock(&clockman->regs_lock);
860 +static int rp1_pll_ph_set_rate(struct clk_hw *hw,
861 + unsigned long rate, unsigned long parent_rate)
863 + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw);
864 + const struct rp1_pll_ph_data *data = pll_ph->data;
865 + struct rp1_clockman *clockman = pll_ph->clockman;
867 + /* Nothing really to do here! */
868 + WARN_ON(data->fixed_divider != 1 && data->fixed_divider != 2);
869 + WARN_ON(rate != parent_rate / data->fixed_divider);
871 +#ifdef MEASURE_CLOCK_RATE
872 + if (rp1_pll_ph_is_on(hw))
873 + clockman_measure_clock(clockman, data->name, data->fc0_src);
878 +static unsigned long rp1_pll_ph_recalc_rate(struct clk_hw *hw,
879 + unsigned long parent_rate)
881 + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw);
882 + const struct rp1_pll_ph_data *data = pll_ph->data;
884 + return parent_rate / data->fixed_divider;
887 +static long rp1_pll_ph_round_rate(struct clk_hw *hw, unsigned long rate,
888 + unsigned long *parent_rate)
890 + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw);
891 + const struct rp1_pll_ph_data *data = pll_ph->data;
893 + return *parent_rate / data->fixed_divider;
896 +static void rp1_pll_ph_debug_init(struct clk_hw *hw,
897 + struct dentry *dentry)
899 + struct rp1_pll_ph *pll_ph = container_of(hw, struct rp1_pll_ph, hw);
900 + const struct rp1_pll_ph_data *data = pll_ph->data;
901 + struct rp1_clockman *clockman = pll_ph->clockman;
902 + struct debugfs_reg32 *regs;
904 + regs = devm_kcalloc(clockman->dev, 1, sizeof(*regs), GFP_KERNEL);
908 + regs[0].name = "ph_reg";
909 + regs[0].offset = data->ph_reg;
911 + rp1_debugfs_regset(clockman, 0, regs, 1, dentry);
914 +static int rp1_pll_divider_is_on(struct clk_hw *hw)
916 + struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw);
917 + struct rp1_clockman *clockman = divider->clockman;
918 + const struct rp1_pll_data *data = divider->data;
920 + return !(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_RST);
923 +static int rp1_pll_divider_on(struct clk_hw *hw)
925 + struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw);
926 + struct rp1_clockman *clockman = divider->clockman;
927 + const struct rp1_pll_data *data = divider->data;
929 + spin_lock(&clockman->regs_lock);
930 + /* Check the implementation bit is set! */
931 + WARN_ON(!(clockman_read(clockman, data->ctrl_reg) & PLL_SEC_IMPL));
932 + clockman_write(clockman, data->ctrl_reg,
933 + clockman_read(clockman, data->ctrl_reg) & ~PLL_SEC_RST);
934 + spin_unlock(&clockman->regs_lock);
936 +#ifdef MEASURE_CLOCK_RATE
937 + clockman_measure_clock(clockman, data->name, data->fc0_src);
942 +static void rp1_pll_divider_off(struct clk_hw *hw)
944 + struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw);
945 + struct rp1_clockman *clockman = divider->clockman;
946 + const struct rp1_pll_data *data = divider->data;
948 + spin_lock(&clockman->regs_lock);
949 + clockman_write(clockman, data->ctrl_reg, PLL_SEC_RST);
950 + spin_unlock(&clockman->regs_lock);
953 +static int rp1_pll_divider_set_rate(struct clk_hw *hw,
954 + unsigned long rate,
955 + unsigned long parent_rate)
957 + struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw);
958 + struct rp1_clockman *clockman = divider->clockman;
959 + const struct rp1_pll_data *data = divider->data;
962 + div = DIV_ROUND_UP_ULL(parent_rate, rate);
963 + div = clamp(div, 8u, 19u);
965 + spin_lock(&clockman->regs_lock);
966 + sec = clockman_read(clockman, data->ctrl_reg);
967 + sec = set_register_field(sec, div, PLL_SEC_DIV_MASK, PLL_SEC_DIV_SHIFT);
969 + /* Must keep the divider in reset to change the value. */
970 + sec |= PLL_SEC_RST;
971 + clockman_write(clockman, data->ctrl_reg, sec);
973 + // todo: must sleep 10 pll vco cycles
974 + sec &= ~PLL_SEC_RST;
975 + clockman_write(clockman, data->ctrl_reg, sec);
976 + spin_unlock(&clockman->regs_lock);
978 +#ifdef MEASURE_CLOCK_RATE
979 + if (rp1_pll_divider_is_on(hw))
980 + clockman_measure_clock(clockman, data->name, data->fc0_src);
985 +static unsigned long rp1_pll_divider_recalc_rate(struct clk_hw *hw,
986 + unsigned long parent_rate)
988 + return clk_divider_ops.recalc_rate(hw, parent_rate);
991 +static long rp1_pll_divider_round_rate(struct clk_hw *hw,
992 + unsigned long rate,
993 + unsigned long *parent_rate)
995 + return clk_divider_ops.round_rate(hw, rate, parent_rate);
998 +static void rp1_pll_divider_debug_init(struct clk_hw *hw, struct dentry *dentry)
1000 + struct rp1_pll *divider = container_of(hw, struct rp1_pll, div.hw);
1001 + struct rp1_clockman *clockman = divider->clockman;
1002 + const struct rp1_pll_data *data = divider->data;
1003 + struct debugfs_reg32 *regs;
1005 + regs = devm_kcalloc(clockman->dev, 1, sizeof(*regs), GFP_KERNEL);
1009 + regs[0].name = "sec";
1010 + regs[0].offset = data->ctrl_reg;
1012 + rp1_debugfs_regset(clockman, 0, regs, 1, dentry);
1015 +static int rp1_clock_is_on(struct clk_hw *hw)
1017 + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw);
1018 + struct rp1_clockman *clockman = clock->clockman;
1019 + const struct rp1_clock_data *data = clock->data;
1021 + return !!(clockman_read(clockman, data->ctrl_reg) & CLK_CTRL_ENABLE);
1024 +static unsigned long rp1_clock_recalc_rate(struct clk_hw *hw,
1025 + unsigned long parent_rate)
1027 + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw);
1028 + struct rp1_clockman *clockman = clock->clockman;
1029 + const struct rp1_clock_data *data = clock->data;
1035 + div = clockman_read(clockman, data->div_int_reg);
1036 + frac = (data->div_frac_reg != 0) ?
1037 + clockman_read(clockman, data->div_frac_reg) : 0;
1039 + /* If the integer portion of the divider is 0, treat it as 2^16 */
1043 + div = (div << CLK_DIV_FRAC_BITS) | (frac >> (32 - CLK_DIV_FRAC_BITS));
1045 + calc_rate = (u64)parent_rate << CLK_DIV_FRAC_BITS;
1046 + calc_rate = div64_u64(calc_rate, div);
1051 +static int rp1_clock_on(struct clk_hw *hw)
1053 + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw);
1054 + struct rp1_clockman *clockman = clock->clockman;
1055 + const struct rp1_clock_data *data = clock->data;
1057 + spin_lock(&clockman->regs_lock);
1058 + clockman_write(clockman, data->ctrl_reg,
1059 + clockman_read(clockman, data->ctrl_reg) | CLK_CTRL_ENABLE);
1060 + spin_unlock(&clockman->regs_lock);
1062 +#ifdef MEASURE_CLOCK_RATE
1063 + clockman_measure_clock(clockman, data->name, data->fc0_src);
1068 +static void rp1_clock_off(struct clk_hw *hw)
1070 + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw);
1071 + struct rp1_clockman *clockman = clock->clockman;
1072 + const struct rp1_clock_data *data = clock->data;
1074 + spin_lock(&clockman->regs_lock);
1075 + clockman_write(clockman, data->ctrl_reg,
1076 + clockman_read(clockman, data->ctrl_reg) & ~CLK_CTRL_ENABLE);
1077 + spin_unlock(&clockman->regs_lock);
1080 +static u32 rp1_clock_choose_div(unsigned long rate, unsigned long parent_rate,
1081 + const struct rp1_clock_data *data)
1086 + * Due to earlier rounding, calculated parent_rate may differ from
1087 + * expected value. Don't fail on a small discrepancy near unity divide.
1089 + if (!rate || rate > parent_rate + (parent_rate >> CLK_DIV_FRAC_BITS))
1093 + * Always express div in fixed-point format for fractional division;
1094 + * If no fractional divider is present, the fraction part will be zero.
1096 + if (data->div_frac_reg) {
1097 + div = (u64)parent_rate << CLK_DIV_FRAC_BITS;
1098 + div = DIV_U64_NEAREST(div, rate);
1100 + div = DIV_U64_NEAREST(parent_rate, rate);
1101 + div <<= CLK_DIV_FRAC_BITS;
1105 + 1ull << CLK_DIV_FRAC_BITS,
1106 + (u64)data->div_int_max << CLK_DIV_FRAC_BITS);
1111 +static u8 rp1_clock_get_parent(struct clk_hw *hw)
1113 + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw);
1114 + struct rp1_clockman *clockman = clock->clockman;
1115 + const struct rp1_clock_data *data = clock->data;
1119 + /* Sel is one-hot, so find the first bit set */
1120 + sel = clockman_read(clockman, data->sel_reg);
1121 + parent = ffs(sel) - 1;
1123 + /* sel == 0 implies the parent clock is not enabled yet. */
1125 + /* Read the clock src from the CTRL register instead */
1126 + ctrl = clockman_read(clockman, data->ctrl_reg);
1127 + parent = (ctrl & data->clk_src_mask) >> CLK_CTRL_SRC_SHIFT;
1130 + if (parent >= data->num_std_parents)
1133 + if (parent == AUX_SEL) {
1135 + * Clock parent is an auxiliary source, so get the parent from
1136 + * the AUXSRC register field.
1138 + ctrl = clockman_read(clockman, data->ctrl_reg);
1139 + parent = (ctrl & CLK_CTRL_AUXSRC_MASK) >> CLK_CTRL_AUXSRC_SHIFT;
1140 + parent += data->num_std_parents;
1146 +static int rp1_clock_set_parent(struct clk_hw *hw, u8 index)
1148 + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw);
1149 + struct rp1_clockman *clockman = clock->clockman;
1150 + const struct rp1_clock_data *data = clock->data;
1153 + spin_lock(&clockman->regs_lock);
1154 + ctrl = clockman_read(clockman, data->ctrl_reg);
1156 + if (index >= data->num_std_parents) {
1157 + /* This is an aux source request */
1158 + if (index >= data->num_std_parents + data->num_aux_parents)
1161 + /* Select parent from aux list */
1162 + ctrl = set_register_field(ctrl, index - data->num_std_parents,
1163 + CLK_CTRL_AUXSRC_MASK,
1164 + CLK_CTRL_AUXSRC_SHIFT);
1165 + /* Set src to aux list */
1166 + ctrl = set_register_field(ctrl, AUX_SEL, data->clk_src_mask,
1167 + CLK_CTRL_SRC_SHIFT);
1169 + ctrl = set_register_field(ctrl, index, data->clk_src_mask,
1170 + CLK_CTRL_SRC_SHIFT);
1173 + clockman_write(clockman, data->ctrl_reg, ctrl);
1174 + spin_unlock(&clockman->regs_lock);
1176 + sel = rp1_clock_get_parent(hw);
1177 + WARN(sel != index, "(%s): Parent index req %u returned back %u\n",
1178 + data->name, index, sel);
1183 +static int rp1_clock_set_rate_and_parent(struct clk_hw *hw,
1184 + unsigned long rate,
1185 + unsigned long parent_rate,
1188 + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw);
1189 + struct rp1_clockman *clockman = clock->clockman;
1190 + const struct rp1_clock_data *data = clock->data;
1191 + u32 div = rp1_clock_choose_div(rate, parent_rate, data);
1193 + WARN(rate > 4000000000ll, "rate is -ve (%d)\n", (int)rate);
1196 + "clk divider calculated as 0! (%s, rate %ld, parent rate %ld)\n",
1197 + data->name, rate, parent_rate))
1198 + div = 1 << CLK_DIV_FRAC_BITS;
1200 + spin_lock(&clockman->regs_lock);
1202 + clockman_write(clockman, data->div_int_reg, div >> CLK_DIV_FRAC_BITS);
1203 + if (data->div_frac_reg)
1204 + clockman_write(clockman, data->div_frac_reg, div << (32 - CLK_DIV_FRAC_BITS));
1206 + spin_unlock(&clockman->regs_lock);
1208 + if (parent != 0xff)
1209 + rp1_clock_set_parent(hw, parent);
1211 +#ifdef MEASURE_CLOCK_RATE
1212 + if (rp1_clock_is_on(hw))
1213 + clockman_measure_clock(clockman, data->name, data->fc0_src);
1218 +static int rp1_clock_set_rate(struct clk_hw *hw, unsigned long rate,
1219 + unsigned long parent_rate)
1221 + return rp1_clock_set_rate_and_parent(hw, rate, parent_rate, 0xff);
1224 +static void rp1_clock_choose_div_and_prate(struct clk_hw *hw,
1226 + unsigned long rate,
1227 + unsigned long *prate,
1228 + unsigned long *calc_rate)
1230 + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw);
1231 + const struct rp1_clock_data *data = clock->data;
1232 + struct clk_hw *parent;
1236 + parent = clk_hw_get_parent_by_index(hw, parent_idx);
1237 + *prate = clk_hw_get_rate(parent);
1238 + div = rp1_clock_choose_div(rate, *prate, data);
1245 + /* Recalculate to account for rounding errors */
1246 + tmp = (u64)*prate << CLK_DIV_FRAC_BITS;
1247 + tmp = div_u64(tmp, div);
1251 +static int rp1_clock_determine_rate(struct clk_hw *hw,
1252 + struct clk_rate_request *req)
1254 + struct clk_hw *parent, *best_parent = NULL;
1255 + unsigned long best_rate = 0;
1256 + unsigned long best_prate = 0;
1257 + unsigned long best_rate_diff = ULONG_MAX;
1258 + unsigned long prate, calc_rate;
1262 + * If the NO_REPARENT flag is set, try to use existing parent.
1264 + if ((clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT)) {
1265 + i = rp1_clock_get_parent(hw);
1266 + parent = clk_hw_get_parent_by_index(hw, i);
1268 + rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate,
1270 + if (calc_rate > 0) {
1271 + req->best_parent_hw = parent;
1272 + req->best_parent_rate = prate;
1273 + req->rate = calc_rate;
1280 + * Select parent clock that results in the closest rate (lower or
1283 + for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
1284 + parent = clk_hw_get_parent_by_index(hw, i);
1288 + rp1_clock_choose_div_and_prate(hw, i, req->rate, &prate,
1291 + if (ABS_DIFF(calc_rate, req->rate) < best_rate_diff) {
1292 + best_parent = parent;
1293 + best_prate = prate;
1294 + best_rate = calc_rate;
1295 + best_rate_diff = ABS_DIFF(calc_rate, req->rate);
1297 + if (best_rate_diff == 0)
1302 + if (best_rate == 0)
1305 + req->best_parent_hw = best_parent;
1306 + req->best_parent_rate = best_prate;
1307 + req->rate = best_rate;
1312 +static void rp1_clk_debug_init(struct clk_hw *hw, struct dentry *dentry)
1314 + struct rp1_clock *clock = container_of(hw, struct rp1_clock, hw);
1315 + struct rp1_clockman *clockman = clock->clockman;
1316 + const struct rp1_clock_data *data = clock->data;
1317 + struct debugfs_reg32 *regs;
1320 + regs = devm_kcalloc(clockman->dev, 4, sizeof(*regs), GFP_KERNEL);
1325 + regs[i].name = "ctrl";
1326 + regs[i++].offset = data->ctrl_reg;
1327 + regs[i].name = "div_int";
1328 + regs[i++].offset = data->div_int_reg;
1329 + regs[i].name = "div_frac";
1330 + regs[i++].offset = data->div_frac_reg;
1331 + regs[i].name = "sel";
1332 + regs[i++].offset = data->sel_reg;
1334 + rp1_debugfs_regset(clockman, 0, regs, i, dentry);
1337 +static const struct clk_ops rp1_pll_core_ops = {
1338 + .is_prepared = rp1_pll_core_is_on,
1339 + .prepare = rp1_pll_core_on,
1340 + .unprepare = rp1_pll_core_off,
1341 + .set_rate = rp1_pll_core_set_rate,
1342 + .recalc_rate = rp1_pll_core_recalc_rate,
1343 + .round_rate = rp1_pll_core_round_rate,
1344 + .debug_init = rp1_pll_core_debug_init,
1347 +static const struct clk_ops rp1_pll_ops = {
1348 + .set_rate = rp1_pll_set_rate,
1349 + .recalc_rate = rp1_pll_recalc_rate,
1350 + .round_rate = rp1_pll_round_rate,
1351 + .debug_init = rp1_pll_debug_init,
1354 +static const struct clk_ops rp1_pll_ph_ops = {
1355 + .is_prepared = rp1_pll_ph_is_on,
1356 + .prepare = rp1_pll_ph_on,
1357 + .unprepare = rp1_pll_ph_off,
1358 + .set_rate = rp1_pll_ph_set_rate,
1359 + .recalc_rate = rp1_pll_ph_recalc_rate,
1360 + .round_rate = rp1_pll_ph_round_rate,
1361 + .debug_init = rp1_pll_ph_debug_init,
1364 +static const struct clk_ops rp1_pll_divider_ops = {
1365 + .is_prepared = rp1_pll_divider_is_on,
1366 + .prepare = rp1_pll_divider_on,
1367 + .unprepare = rp1_pll_divider_off,
1368 + .set_rate = rp1_pll_divider_set_rate,
1369 + .recalc_rate = rp1_pll_divider_recalc_rate,
1370 + .round_rate = rp1_pll_divider_round_rate,
1371 + .debug_init = rp1_pll_divider_debug_init,
1374 +static const struct clk_ops rp1_clk_ops = {
1375 + .is_prepared = rp1_clock_is_on,
1376 + .prepare = rp1_clock_on,
1377 + .unprepare = rp1_clock_off,
1378 + .recalc_rate = rp1_clock_recalc_rate,
1379 + .get_parent = rp1_clock_get_parent,
1380 + .set_parent = rp1_clock_set_parent,
1381 + .set_rate_and_parent = rp1_clock_set_rate_and_parent,
1382 + .set_rate = rp1_clock_set_rate,
1383 + .determine_rate = rp1_clock_determine_rate,
1384 + .debug_init = rp1_clk_debug_init,
1387 +static bool rp1_clk_is_claimed(const char *name);
1389 +static struct clk_hw *rp1_register_pll_core(struct rp1_clockman *clockman,
1392 + const struct rp1_pll_core_data *pll_core_data = data;
1393 + struct rp1_pll_core *pll_core;
1394 + struct clk_init_data init;
1397 + memset(&init, 0, sizeof(init));
1399 + /* All of the PLL cores derive from the external oscillator. */
1400 + init.parent_names = &ref_clock;
1401 + init.num_parents = 1;
1402 + init.name = pll_core_data->name;
1403 + init.ops = &rp1_pll_core_ops;
1404 + init.flags = pll_core_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL;
1406 + pll_core = kzalloc(sizeof(*pll_core), GFP_KERNEL);
1410 + pll_core->clockman = clockman;
1411 + pll_core->data = pll_core_data;
1412 + pll_core->hw.init = &init;
1414 + ret = devm_clk_hw_register(clockman->dev, &pll_core->hw);
1420 + return &pll_core->hw;
1423 +static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman,
1426 + const struct rp1_pll_data *pll_data = data;
1427 + struct rp1_pll *pll;
1428 + struct clk_init_data init;
1431 + memset(&init, 0, sizeof(init));
1433 + init.parent_names = &pll_data->source_pll;
1434 + init.num_parents = 1;
1435 + init.name = pll_data->name;
1436 + init.ops = &rp1_pll_ops;
1437 + init.flags = pll_data->flags | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL;
1439 + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
1443 + pll->clockman = clockman;
1444 + pll->data = pll_data;
1445 + pll->hw.init = &init;
1447 + ret = devm_clk_hw_register(clockman->dev, &pll->hw);
1456 +static struct clk_hw *rp1_register_pll_ph(struct rp1_clockman *clockman,
1459 + const struct rp1_pll_ph_data *ph_data = data;
1460 + struct rp1_pll_ph *ph;
1461 + struct clk_init_data init;
1464 + memset(&init, 0, sizeof(init));
1466 + /* All of the PLLs derive from the external oscillator. */
1467 + init.parent_names = &ph_data->source_pll;
1468 + init.num_parents = 1;
1469 + init.name = ph_data->name;
1470 + init.ops = &rp1_pll_ph_ops;
1471 + init.flags = ph_data->flags | CLK_IGNORE_UNUSED;
1473 + ph = kzalloc(sizeof(*ph), GFP_KERNEL);
1477 + ph->clockman = clockman;
1478 + ph->data = ph_data;
1479 + ph->hw.init = &init;
1481 + ret = devm_clk_hw_register(clockman->dev, &ph->hw);
1490 +static struct clk_hw *rp1_register_pll_divider(struct rp1_clockman *clockman,
1493 + const struct rp1_pll_data *divider_data = data;
1494 + struct rp1_pll *divider;
1495 + struct clk_init_data init;
1498 + memset(&init, 0, sizeof(init));
1500 + init.parent_names = ÷r_data->source_pll;
1501 + init.num_parents = 1;
1502 + init.name = divider_data->name;
1503 + init.ops = &rp1_pll_divider_ops;
1504 + init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
1506 + divider = devm_kzalloc(clockman->dev, sizeof(*divider), GFP_KERNEL);
1510 + divider->div.reg = clockman->regs + divider_data->ctrl_reg;
1511 + divider->div.shift = PLL_SEC_DIV_SHIFT;
1512 + divider->div.width = PLL_SEC_DIV_WIDTH;
1513 + divider->div.flags = CLK_DIVIDER_ROUND_CLOSEST;
1514 + divider->div.lock = &clockman->regs_lock;
1515 + divider->div.hw.init = &init;
1516 + divider->div.table = pll_sec_div_table;
1518 + if (!rp1_clk_is_claimed(divider_data->source_pll))
1519 + init.flags |= CLK_IS_CRITICAL;
1520 + if (!rp1_clk_is_claimed(divider_data->name))
1521 + divider->div.flags |= CLK_IS_CRITICAL;
1523 + divider->clockman = clockman;
1524 + divider->data = divider_data;
1526 + ret = devm_clk_hw_register(clockman->dev, ÷r->div.hw);
1528 + return ERR_PTR(ret);
1530 + return ÷r->div.hw;
1533 +static struct clk_hw *rp1_register_clock(struct rp1_clockman *clockman,
1536 + const struct rp1_clock_data *clock_data = data;
1537 + struct rp1_clock *clock;
1538 + struct clk_init_data init;
1541 + BUG_ON(MAX_CLK_PARENTS <
1542 + clock_data->num_std_parents + clock_data->num_aux_parents);
1543 + /* There must be a gap for the AUX selector */
1544 + BUG_ON((clock_data->num_std_parents > AUX_SEL) &&
1545 + strcmp("-", clock_data->parents[AUX_SEL]));
1547 + memset(&init, 0, sizeof(init));
1548 + init.parent_names = clock_data->parents;
1549 + init.num_parents =
1550 + clock_data->num_std_parents + clock_data->num_aux_parents;
1551 + init.name = clock_data->name;
1552 + init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
1553 + init.ops = &rp1_clk_ops;
1555 + clock = devm_kzalloc(clockman->dev, sizeof(*clock), GFP_KERNEL);
1559 + clock->clockman = clockman;
1560 + clock->data = clock_data;
1561 + clock->hw.init = &init;
1563 + ret = devm_clk_hw_register(clockman->dev, &clock->hw);
1565 + return ERR_PTR(ret);
1567 + return &clock->hw;
1570 +struct rp1_clk_desc {
1571 + struct clk_hw *(*clk_register)(struct rp1_clockman *clockman,
1572 + const void *data);
1576 +/* Assignment helper macros for different clock types. */
1577 +#define _REGISTER(f, ...) { .clk_register = f, .data = __VA_ARGS__ }
1579 +#define REGISTER_PLL_CORE(...) _REGISTER(&rp1_register_pll_core, \
1580 + &(struct rp1_pll_core_data) \
1583 +#define REGISTER_PLL(...) _REGISTER(&rp1_register_pll, \
1584 + &(struct rp1_pll_data) \
1587 +#define REGISTER_PLL_PH(...) _REGISTER(&rp1_register_pll_ph, \
1588 + &(struct rp1_pll_ph_data) \
1591 +#define REGISTER_PLL_DIV(...) _REGISTER(&rp1_register_pll_divider, \
1592 + &(struct rp1_pll_data) \
1595 +#define REGISTER_CLK(...) _REGISTER(&rp1_register_clock, \
1596 + &(struct rp1_clock_data) \
1599 +static const struct rp1_clk_desc clk_desc_array[] = {
1600 + [RP1_PLL_SYS_CORE] = REGISTER_PLL_CORE(
1601 + .name = "pll_sys_core",
1602 + .cs_reg = PLL_SYS_CS,
1603 + .pwr_reg = PLL_SYS_PWR,
1604 + .fbdiv_int_reg = PLL_SYS_FBDIV_INT,
1605 + .fbdiv_frac_reg = PLL_SYS_FBDIV_FRAC,
1608 + [RP1_PLL_AUDIO_CORE] = REGISTER_PLL_CORE(
1609 + .name = "pll_audio_core",
1610 + .cs_reg = PLL_AUDIO_CS,
1611 + .pwr_reg = PLL_AUDIO_PWR,
1612 + .fbdiv_int_reg = PLL_AUDIO_FBDIV_INT,
1613 + .fbdiv_frac_reg = PLL_AUDIO_FBDIV_FRAC,
1616 + [RP1_PLL_VIDEO_CORE] = REGISTER_PLL_CORE(
1617 + .name = "pll_video_core",
1618 + .cs_reg = PLL_VIDEO_CS,
1619 + .pwr_reg = PLL_VIDEO_PWR,
1620 + .fbdiv_int_reg = PLL_VIDEO_FBDIV_INT,
1621 + .fbdiv_frac_reg = PLL_VIDEO_FBDIV_FRAC,
1624 + [RP1_PLL_SYS] = REGISTER_PLL(
1625 + .name = "pll_sys",
1626 + .source_pll = "pll_sys_core",
1627 + .ctrl_reg = PLL_SYS_PRIM,
1628 + .fc0_src = FC_NUM(0, 2),
1631 + [RP1_PLL_AUDIO] = REGISTER_PLL(
1632 + .name = "pll_audio",
1633 + .source_pll = "pll_audio_core",
1634 + .ctrl_reg = PLL_AUDIO_PRIM,
1635 + .fc0_src = FC_NUM(4, 2),
1638 + [RP1_PLL_VIDEO] = REGISTER_PLL(
1639 + .name = "pll_video",
1640 + .source_pll = "pll_video_core",
1641 + .ctrl_reg = PLL_VIDEO_PRIM,
1642 + .fc0_src = FC_NUM(3, 2),
1645 + [RP1_PLL_SYS_PRI_PH] = REGISTER_PLL_PH(
1646 + .name = "pll_sys_pri_ph",
1647 + .source_pll = "pll_sys",
1648 + .ph_reg = PLL_SYS_PRIM,
1649 + .fixed_divider = 2,
1650 + .phase = RP1_PLL_PHASE_0,
1651 + .fc0_src = FC_NUM(1, 2),
1654 + [RP1_PLL_AUDIO_PRI_PH] = REGISTER_PLL_PH(
1655 + .name = "pll_audio_pri_ph",
1656 + .source_pll = "pll_audio",
1657 + .ph_reg = PLL_AUDIO_PRIM,
1658 + .fixed_divider = 2,
1659 + .phase = RP1_PLL_PHASE_0,
1660 + .fc0_src = FC_NUM(5, 1),
1663 + [RP1_PLL_SYS_SEC] = REGISTER_PLL_DIV(
1664 + .name = "pll_sys_sec",
1665 + .source_pll = "pll_sys_core",
1666 + .ctrl_reg = PLL_SYS_SEC,
1667 + .fc0_src = FC_NUM(2, 2),
1670 + [RP1_PLL_AUDIO_SEC] = REGISTER_PLL_DIV(
1671 + .name = "pll_audio_sec",
1672 + .source_pll = "pll_audio_core",
1673 + .ctrl_reg = PLL_AUDIO_SEC,
1674 + .fc0_src = FC_NUM(6, 2),
1677 + [RP1_PLL_VIDEO_SEC] = REGISTER_PLL_DIV(
1678 + .name = "pll_video_sec",
1679 + .source_pll = "pll_video_core",
1680 + .ctrl_reg = PLL_VIDEO_SEC,
1681 + .fc0_src = FC_NUM(5, 3),
1684 + [RP1_CLK_SYS] = REGISTER_CLK(
1685 + .name = "clk_sys",
1686 + .parents = {"xosc", "-", "pll_sys"},
1687 + .num_std_parents = 3,
1688 + .num_aux_parents = 0,
1689 + .ctrl_reg = CLK_SYS_CTRL,
1690 + .div_int_reg = CLK_SYS_DIV_INT,
1691 + .sel_reg = CLK_SYS_SEL,
1692 + .div_int_max = DIV_INT_24BIT_MAX,
1693 + .fc0_src = FC_NUM(0, 4),
1694 + .clk_src_mask = 0x3,
1697 + [RP1_CLK_SLOW_SYS] = REGISTER_CLK(
1698 + .name = "clk_slow_sys",
1699 + .parents = {"xosc"},
1700 + .num_std_parents = 1,
1701 + .num_aux_parents = 0,
1702 + .ctrl_reg = CLK_SLOW_SYS_CTRL,
1703 + .div_int_reg = CLK_SLOW_SYS_DIV_INT,
1704 + .sel_reg = CLK_SLOW_SYS_SEL,
1705 + .div_int_max = DIV_INT_8BIT_MAX,
1706 + .fc0_src = FC_NUM(1, 4),
1707 + .clk_src_mask = 0x1,
1710 + [RP1_CLK_UART] = REGISTER_CLK(
1711 + .name = "clk_uart",
1712 + .parents = {"pll_sys_pri_ph",
1715 + .num_std_parents = 0,
1716 + .num_aux_parents = 3,
1717 + .ctrl_reg = CLK_UART_CTRL,
1718 + .div_int_reg = CLK_UART_DIV_INT,
1719 + .sel_reg = CLK_UART_SEL,
1720 + .div_int_max = DIV_INT_8BIT_MAX,
1721 + .fc0_src = FC_NUM(6, 7),
1724 + [RP1_CLK_ETH] = REGISTER_CLK(
1725 + .name = "clk_eth",
1727 + .num_std_parents = 1,
1728 + .num_aux_parents = 0,
1729 + .ctrl_reg = CLK_ETH_CTRL,
1730 + .div_int_reg = CLK_ETH_DIV_INT,
1731 + .sel_reg = CLK_ETH_SEL,
1732 + .div_int_max = DIV_INT_8BIT_MAX,
1733 + .fc0_src = FC_NUM(4, 6),
1736 + [RP1_CLK_PWM0] = REGISTER_CLK(
1737 + .name = "clk_pwm0",
1738 + .parents = {"pll_audio_pri_ph",
1741 + .num_std_parents = 0,
1742 + .num_aux_parents = 3,
1743 + .ctrl_reg = CLK_PWM0_CTRL,
1744 + .div_int_reg = CLK_PWM0_DIV_INT,
1745 + .div_frac_reg = CLK_PWM0_DIV_FRAC,
1746 + .sel_reg = CLK_PWM0_SEL,
1747 + .div_int_max = DIV_INT_16BIT_MAX,
1748 + .fc0_src = FC_NUM(0, 5),
1751 + [RP1_CLK_PWM1] = REGISTER_CLK(
1752 + .name = "clk_pwm1",
1753 + .parents = {"pll_audio_pri_ph",
1756 + .num_std_parents = 0,
1757 + .num_aux_parents = 3,
1758 + .ctrl_reg = CLK_PWM1_CTRL,
1759 + .div_int_reg = CLK_PWM1_DIV_INT,
1760 + .div_frac_reg = CLK_PWM1_DIV_FRAC,
1761 + .sel_reg = CLK_PWM1_SEL,
1762 + .div_int_max = DIV_INT_16BIT_MAX,
1763 + .fc0_src = FC_NUM(1, 5),
1766 + [RP1_CLK_AUDIO_IN] = REGISTER_CLK(
1767 + .name = "clk_audio_in",
1769 + .num_std_parents = 1,
1770 + .num_aux_parents = 0,
1771 + .ctrl_reg = CLK_AUDIO_IN_CTRL,
1772 + .div_int_reg = CLK_AUDIO_IN_DIV_INT,
1773 + .sel_reg = CLK_AUDIO_IN_SEL,
1774 + .div_int_max = DIV_INT_8BIT_MAX,
1775 + .fc0_src = FC_NUM(2, 5),
1778 + [RP1_CLK_AUDIO_OUT] = REGISTER_CLK(
1779 + .name = "clk_audio_out",
1781 + .num_std_parents = 1,
1782 + .num_aux_parents = 0,
1783 + .ctrl_reg = CLK_AUDIO_OUT_CTRL,
1784 + .div_int_reg = CLK_AUDIO_OUT_DIV_INT,
1785 + .sel_reg = CLK_AUDIO_OUT_SEL,
1786 + .div_int_max = DIV_INT_8BIT_MAX,
1787 + .fc0_src = FC_NUM(3, 5),
1790 + [RP1_CLK_I2S] = REGISTER_CLK(
1791 + .name = "clk_i2s",
1792 + .parents = {"xosc",
1795 + .num_std_parents = 0,
1796 + .num_aux_parents = 3,
1797 + .ctrl_reg = CLK_I2S_CTRL,
1798 + .div_int_reg = CLK_I2S_DIV_INT,
1799 + .sel_reg = CLK_I2S_SEL,
1800 + .div_int_max = DIV_INT_8BIT_MAX,
1801 + .fc0_src = FC_NUM(4, 4),
1804 + [RP1_CLK_MIPI0_CFG] = REGISTER_CLK(
1805 + .name = "clk_mipi0_cfg",
1806 + .parents = {"xosc"},
1807 + .num_std_parents = 0,
1808 + .num_aux_parents = 1,
1809 + .ctrl_reg = CLK_MIPI0_CFG_CTRL,
1810 + .div_int_reg = CLK_MIPI0_CFG_DIV_INT,
1811 + .sel_reg = CLK_MIPI0_CFG_SEL,
1812 + .div_int_max = DIV_INT_8BIT_MAX,
1813 + .fc0_src = FC_NUM(4, 5),
1816 + [RP1_CLK_MIPI1_CFG] = REGISTER_CLK(
1817 + .name = "clk_mipi1_cfg",
1818 + .parents = {"xosc"},
1819 + .num_std_parents = 0,
1820 + .num_aux_parents = 1,
1821 + .ctrl_reg = CLK_MIPI1_CFG_CTRL,
1822 + .div_int_reg = CLK_MIPI1_CFG_DIV_INT,
1823 + .sel_reg = CLK_MIPI1_CFG_SEL,
1824 + .clk_src_mask = 1,
1825 + .div_int_max = DIV_INT_8BIT_MAX,
1826 + .fc0_src = FC_NUM(5, 6),
1829 + [RP1_CLK_ETH_TSU] = REGISTER_CLK(
1830 + .name = "clk_eth_tsu",
1831 + .parents = {"xosc"},
1832 + .num_std_parents = 0,
1833 + .num_aux_parents = 1,
1834 + .ctrl_reg = CLK_ETH_TSU_CTRL,
1835 + .div_int_reg = CLK_ETH_TSU_DIV_INT,
1836 + .sel_reg = CLK_ETH_TSU_SEL,
1837 + .div_int_max = DIV_INT_8BIT_MAX,
1838 + .fc0_src = FC_NUM(5, 7),
1841 + [RP1_CLK_ADC] = REGISTER_CLK(
1842 + .name = "clk_adc",
1843 + .parents = {"xosc"},
1844 + .num_std_parents = 0,
1845 + .num_aux_parents = 1,
1846 + .ctrl_reg = CLK_ADC_CTRL,
1847 + .div_int_reg = CLK_ADC_DIV_INT,
1848 + .sel_reg = CLK_ADC_SEL,
1849 + .div_int_max = DIV_INT_8BIT_MAX,
1850 + .fc0_src = FC_NUM(5, 5),
1853 + [RP1_CLK_SDIO_TIMER] = REGISTER_CLK(
1854 + .name = "clk_sdio_timer",
1855 + .parents = {"xosc"},
1856 + .num_std_parents = 0,
1857 + .num_aux_parents = 1,
1858 + .ctrl_reg = CLK_SDIO_TIMER_CTRL,
1859 + .div_int_reg = CLK_SDIO_TIMER_DIV_INT,
1860 + .sel_reg = CLK_SDIO_TIMER_SEL,
1861 + .div_int_max = DIV_INT_8BIT_MAX,
1862 + .fc0_src = FC_NUM(3, 4),
1865 + [RP1_CLK_SDIO_ALT_SRC] = REGISTER_CLK(
1866 + .name = "clk_sdio_alt_src",
1867 + .parents = {"pll_sys"},
1868 + .num_std_parents = 0,
1869 + .num_aux_parents = 1,
1870 + .ctrl_reg = CLK_SDIO_ALT_SRC_CTRL,
1871 + .div_int_reg = CLK_SDIO_ALT_SRC_DIV_INT,
1872 + .sel_reg = CLK_SDIO_ALT_SRC_SEL,
1873 + .div_int_max = DIV_INT_8BIT_MAX,
1874 + .fc0_src = FC_NUM(5, 4),
1877 + [RP1_CLK_GP0] = REGISTER_CLK(
1878 + .name = "clk_gp0",
1879 + .parents = {"xosc"},
1880 + .num_std_parents = 0,
1881 + .num_aux_parents = 1,
1882 + .ctrl_reg = CLK_GP0_CTRL,
1883 + .div_int_reg = CLK_GP0_DIV_INT,
1884 + .div_frac_reg = CLK_GP0_DIV_FRAC,
1885 + .sel_reg = CLK_GP0_SEL,
1886 + .div_int_max = DIV_INT_16BIT_MAX,
1887 + .fc0_src = FC_NUM(0, 1),
1890 + [RP1_CLK_GP1] = REGISTER_CLK(
1891 + .name = "clk_gp1",
1892 + .parents = {"xosc"},
1893 + .num_std_parents = 0,
1894 + .num_aux_parents = 1,
1895 + .ctrl_reg = CLK_GP1_CTRL,
1896 + .div_int_reg = CLK_GP1_DIV_INT,
1897 + .div_frac_reg = CLK_GP1_DIV_FRAC,
1898 + .sel_reg = CLK_GP1_SEL,
1899 + .div_int_max = DIV_INT_16BIT_MAX,
1900 + .fc0_src = FC_NUM(1, 1),
1903 + [RP1_CLK_GP2] = REGISTER_CLK(
1904 + .name = "clk_gp2",
1905 + .parents = {"xosc"},
1906 + .num_std_parents = 0,
1907 + .num_aux_parents = 1,
1908 + .ctrl_reg = CLK_GP2_CTRL,
1909 + .div_int_reg = CLK_GP2_DIV_INT,
1910 + .div_frac_reg = CLK_GP2_DIV_FRAC,
1911 + .sel_reg = CLK_GP2_SEL,
1912 + .div_int_max = DIV_INT_16BIT_MAX,
1913 + .fc0_src = FC_NUM(2, 1),
1916 + [RP1_CLK_GP3] = REGISTER_CLK(
1917 + .name = "clk_gp3",
1918 + .parents = {"xosc"},
1919 + .num_std_parents = 0,
1920 + .num_aux_parents = 1,
1921 + .ctrl_reg = CLK_GP3_CTRL,
1922 + .div_int_reg = CLK_GP3_DIV_INT,
1923 + .div_frac_reg = CLK_GP3_DIV_FRAC,
1924 + .sel_reg = CLK_GP3_SEL,
1925 + .div_int_max = DIV_INT_16BIT_MAX,
1926 + .fc0_src = FC_NUM(3, 1),
1929 + [RP1_CLK_GP4] = REGISTER_CLK(
1930 + .name = "clk_gp4",
1931 + .parents = {"xosc"},
1932 + .num_std_parents = 0,
1933 + .num_aux_parents = 1,
1934 + .ctrl_reg = CLK_GP4_CTRL,
1935 + .div_int_reg = CLK_GP4_DIV_INT,
1936 + .div_frac_reg = CLK_GP4_DIV_FRAC,
1937 + .sel_reg = CLK_GP4_SEL,
1938 + .div_int_max = DIV_INT_16BIT_MAX,
1939 + .fc0_src = FC_NUM(4, 1),
1942 + [RP1_CLK_GP5] = REGISTER_CLK(
1943 + .name = "clk_gp5",
1944 + .parents = {"xosc"},
1945 + .num_std_parents = 0,
1946 + .num_aux_parents = 1,
1947 + .ctrl_reg = CLK_GP5_CTRL,
1948 + .div_int_reg = CLK_GP5_DIV_INT,
1949 + .div_frac_reg = CLK_GP5_DIV_FRAC,
1950 + .sel_reg = CLK_GP5_SEL,
1951 + .div_int_max = DIV_INT_16BIT_MAX,
1952 + .fc0_src = FC_NUM(5, 1),
1955 + [RP1_CLK_VEC] = REGISTER_CLK(
1956 + .name = "clk_vec",
1957 + .parents = {"pll_sys_pri_ph",
1965 + .num_std_parents = 0,
1966 + .num_aux_parents = 8, /* XXX in fact there are more than 8 */
1967 + .ctrl_reg = VIDEO_CLK_VEC_CTRL,
1968 + .div_int_reg = VIDEO_CLK_VEC_DIV_INT,
1969 + .sel_reg = VIDEO_CLK_VEC_SEL,
1970 + .flags = CLK_SET_RATE_NO_REPARENT, /* Let VEC driver set parent */
1971 + .div_int_max = DIV_INT_8BIT_MAX,
1972 + .fc0_src = FC_NUM(0, 6),
1975 + [RP1_CLK_DPI] = REGISTER_CLK(
1976 + .name = "clk_dpi",
1977 + .parents = {"pll_sys",
1985 + .num_std_parents = 0,
1986 + .num_aux_parents = 8, /* XXX in fact there are more than 8 */
1987 + .ctrl_reg = VIDEO_CLK_DPI_CTRL,
1988 + .div_int_reg = VIDEO_CLK_DPI_DIV_INT,
1989 + .sel_reg = VIDEO_CLK_DPI_SEL,
1990 + .flags = CLK_SET_RATE_NO_REPARENT, /* Let DPI driver set parent */
1991 + .div_int_max = DIV_INT_8BIT_MAX,
1992 + .fc0_src = FC_NUM(1, 6),
1995 + [RP1_CLK_MIPI0_DPI] = REGISTER_CLK(
1996 + .name = "clk_mipi0_dpi",
1997 + .parents = {"pll_sys",
2000 + "clksrc_mipi0_dsi_byteclk",
2005 + .num_std_parents = 0,
2006 + .num_aux_parents = 8, /* XXX in fact there are more than 8 */
2007 + .ctrl_reg = VIDEO_CLK_MIPI0_DPI_CTRL,
2008 + .div_int_reg = VIDEO_CLK_MIPI0_DPI_DIV_INT,
2009 + .div_frac_reg = VIDEO_CLK_MIPI0_DPI_DIV_FRAC,
2010 + .sel_reg = VIDEO_CLK_MIPI0_DPI_SEL,
2011 + .flags = CLK_SET_RATE_NO_REPARENT, /* Let DSI driver set parent */
2012 + .div_int_max = DIV_INT_8BIT_MAX,
2013 + .fc0_src = FC_NUM(2, 6),
2016 + [RP1_CLK_MIPI1_DPI] = REGISTER_CLK(
2017 + .name = "clk_mipi1_dpi",
2018 + .parents = {"pll_sys",
2021 + "clksrc_mipi1_dsi_byteclk",
2026 + .num_std_parents = 0,
2027 + .num_aux_parents = 8, /* XXX in fact there are more than 8 */
2028 + .ctrl_reg = VIDEO_CLK_MIPI1_DPI_CTRL,
2029 + .div_int_reg = VIDEO_CLK_MIPI1_DPI_DIV_INT,
2030 + .div_frac_reg = VIDEO_CLK_MIPI1_DPI_DIV_FRAC,
2031 + .sel_reg = VIDEO_CLK_MIPI1_DPI_SEL,
2032 + .flags = CLK_SET_RATE_NO_REPARENT, /* Let DSI driver set parent */
2033 + .div_int_max = DIV_INT_8BIT_MAX,
2034 + .fc0_src = FC_NUM(3, 6),
2038 +static bool rp1_clk_claimed[ARRAY_SIZE(clk_desc_array)];
2040 +static bool rp1_clk_is_claimed(const char *name)
2044 + for (i = 0; i < ARRAY_SIZE(clk_desc_array); i++) {
2045 + if (clk_desc_array[i].data) {
2046 + const char *clk_name = *(const char **)(clk_desc_array[i].data);
2048 + if (!strcmp(name, clk_name))
2049 + return rp1_clk_claimed[i];
2056 +static int rp1_clk_probe(struct platform_device *pdev)
2058 + const struct rp1_clk_desc *desc;
2059 + struct device *dev = &pdev->dev;
2060 + struct rp1_clockman *clockman;
2061 + struct resource *res;
2062 + struct clk_hw **hws;
2063 + const size_t asize = ARRAY_SIZE(clk_desc_array);
2064 + u32 chip_id, platform;
2069 + clockman = devm_kzalloc(dev, struct_size(clockman, onecell.hws, asize),
2074 + rp1_get_platform(&chip_id, &platform);
2076 + spin_lock_init(&clockman->regs_lock);
2077 + clockman->dev = dev;
2078 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2079 + clockman->regs = devm_ioremap_resource(&pdev->dev, res);
2080 + if (IS_ERR(clockman->regs))
2081 + return PTR_ERR(clockman->regs);
2083 + memset(rp1_clk_claimed, 0, sizeof(rp1_clk_claimed));
2085 + !of_property_read_u32_index(pdev->dev.of_node, "claim-clocks",
2088 + rp1_clk_claimed[clk_id] = true;
2090 + platform_set_drvdata(pdev, clockman);
2092 + clockman->onecell.num = asize;
2093 + hws = clockman->onecell.hws;
2095 + for (i = 0; i < asize; i++) {
2096 + desc = &clk_desc_array[i];
2097 + if (desc->clk_register && desc->data)
2098 + hws[i] = desc->clk_register(clockman, desc->data);
2101 + ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2102 + &clockman->onecell);
2109 +static const struct of_device_id rp1_clk_of_match[] = {
2110 + { .compatible = "raspberrypi,rp1-clocks" },
2113 +MODULE_DEVICE_TABLE(of, rp1_clk_of_match);
2115 +static struct platform_driver rp1_clk_driver = {
2117 + .name = "rp1-clk",
2118 + .of_match_table = rp1_clk_of_match,
2120 + .probe = rp1_clk_probe,
2123 +static int __init __rp1_clk_driver_init(void)
2125 + return platform_driver_register(&rp1_clk_driver);
2127 +postcore_initcall(__rp1_clk_driver_init);
2129 +MODULE_AUTHOR("Naushir Patuck <naush@raspberrypi.com>");
2130 +MODULE_DESCRIPTION("RP1 clock driver");
2131 +MODULE_LICENSE("GPL");
2132 --- a/include/dt-bindings/clock/rp1.h
2133 +++ b/include/dt-bindings/clock/rp1.h
2136 #define RP1_PLL_SYS_PRI_PH 6
2137 #define RP1_PLL_SYS_SEC_PH 7
2138 +#define RP1_PLL_AUDIO_PRI_PH 8
2140 -#define RP1_PLL_SYS_SEC 8
2141 -#define RP1_PLL_AUDIO_SEC 9
2142 -#define RP1_PLL_VIDEO_SEC 10
2143 +#define RP1_PLL_SYS_SEC 9
2144 +#define RP1_PLL_AUDIO_SEC 10
2145 +#define RP1_PLL_VIDEO_SEC 11
2147 -#define RP1_CLK_SYS 11
2148 -#define RP1_CLK_SLOW_SYS 12
2149 -#define RP1_CLK_DMA 13
2150 -#define RP1_CLK_UART 14
2151 -#define RP1_CLK_ETH 15
2152 -#define RP1_CLK_PWM0 16
2153 -#define RP1_CLK_PWM1 17
2154 -#define RP1_CLK_AUDIO_IN 18
2155 -#define RP1_CLK_AUDIO_OUT 19
2156 -#define RP1_CLK_I2S 20
2157 -#define RP1_CLK_MIPI0_CFG 21
2158 -#define RP1_CLK_MIPI1_CFG 22
2159 -#define RP1_CLK_PCIE_AUX 23
2160 -#define RP1_CLK_USBH0_MICROFRAME 24
2161 -#define RP1_CLK_USBH1_MICROFRAME 25
2162 -#define RP1_CLK_USBH0_SUSPEND 26
2163 -#define RP1_CLK_USBH1_SUSPEND 27
2164 -#define RP1_CLK_ETH_TSU 28
2165 -#define RP1_CLK_ADC 29
2166 -#define RP1_CLK_SDIO_TIMER 30
2167 -#define RP1_CLK_SDIO_ALT_SRC 31
2168 -#define RP1_CLK_GP0 32
2169 -#define RP1_CLK_GP1 33
2170 -#define RP1_CLK_GP2 34
2171 -#define RP1_CLK_GP3 35
2172 -#define RP1_CLK_GP4 36
2173 -#define RP1_CLK_GP5 37
2174 -#define RP1_CLK_VEC 38
2175 -#define RP1_CLK_DPI 39
2176 -#define RP1_CLK_MIPI0_DPI 40
2177 -#define RP1_CLK_MIPI1_DPI 41
2178 +#define RP1_CLK_SYS 12
2179 +#define RP1_CLK_SLOW_SYS 13
2180 +#define RP1_CLK_DMA 14
2181 +#define RP1_CLK_UART 15
2182 +#define RP1_CLK_ETH 16
2183 +#define RP1_CLK_PWM0 17
2184 +#define RP1_CLK_PWM1 18
2185 +#define RP1_CLK_AUDIO_IN 19
2186 +#define RP1_CLK_AUDIO_OUT 20
2187 +#define RP1_CLK_I2S 21
2188 +#define RP1_CLK_MIPI0_CFG 22
2189 +#define RP1_CLK_MIPI1_CFG 23
2190 +#define RP1_CLK_PCIE_AUX 24
2191 +#define RP1_CLK_USBH0_MICROFRAME 25
2192 +#define RP1_CLK_USBH1_MICROFRAME 26
2193 +#define RP1_CLK_USBH0_SUSPEND 27
2194 +#define RP1_CLK_USBH1_SUSPEND 28
2195 +#define RP1_CLK_ETH_TSU 29
2196 +#define RP1_CLK_ADC 30
2197 +#define RP1_CLK_SDIO_TIMER 31
2198 +#define RP1_CLK_SDIO_ALT_SRC 32
2199 +#define RP1_CLK_GP0 33
2200 +#define RP1_CLK_GP1 34
2201 +#define RP1_CLK_GP2 35
2202 +#define RP1_CLK_GP3 36
2203 +#define RP1_CLK_GP4 37
2204 +#define RP1_CLK_GP5 38
2205 +#define RP1_CLK_VEC 39
2206 +#define RP1_CLK_DPI 40
2207 +#define RP1_CLK_MIPI0_DPI 41
2208 +#define RP1_CLK_MIPI1_DPI 42