1 From 4d4cc5be473a7767052122a87393a83d10f9ed41 Mon Sep 17 00:00:00 2001
2 From: Phil Elwell <phil@raspberrypi.com>
3 Date: Mon, 10 Oct 2022 14:21:11 +0100
4 Subject: [PATCH] pinctrl: Add rp1 driver
6 RP1 exposes GPIOs. Add a pinctrl driver to allow control of those.
8 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
10 drivers/pinctrl/Kconfig | 7 +
11 drivers/pinctrl/Makefile | 1 +
12 drivers/pinctrl/pinctrl-rp1.c | 1571 +++++++++++++++++++++++++++++
13 include/dt-bindings/pinctrl/rp1.h | 46 -
14 4 files changed, 1579 insertions(+), 46 deletions(-)
15 create mode 100644 drivers/pinctrl/pinctrl-rp1.c
16 delete mode 100644 include/dt-bindings/pinctrl/rp1.h
18 --- a/drivers/pinctrl/Kconfig
19 +++ b/drivers/pinctrl/Kconfig
20 @@ -512,6 +512,13 @@ config PINCTRL_ZYNQMP
21 This driver can also be built as a module. If so, the module
22 will be called pinctrl-zynqmp.
25 + bool "Pinctrl driver for RP1"
28 + select GENERIC_PINCONF
29 + select GPIOLIB_IRQCHIP
31 source "drivers/pinctrl/actions/Kconfig"
32 source "drivers/pinctrl/aspeed/Kconfig"
33 source "drivers/pinctrl/bcm/Kconfig"
34 --- a/drivers/pinctrl/Makefile
35 +++ b/drivers/pinctrl/Makefile
36 @@ -42,6 +42,7 @@ obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-p
37 obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o
38 obj-$(CONFIG_PINCTRL_RK805) += pinctrl-rk805.o
39 obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o
40 +obj-$(CONFIG_PINCTRL_RP1) += pinctrl-rp1.o
41 obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
42 obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
43 obj-$(CONFIG_PINCTRL_STMFX) += pinctrl-stmfx.o
45 +++ b/drivers/pinctrl/pinctrl-rp1.c
47 +// SPDX-License-Identifier: GPL-2.0
49 + * Driver for Raspberry Pi RP1 GPIO unit (pinctrl + GPIO)
51 + * Copyright (C) 2023 Raspberry Pi Ltd.
53 + * This driver is inspired by:
54 + * pinctrl-bcm2835.c, please see original file for copyright information
57 +#include <linux/bitmap.h>
58 +#include <linux/bitops.h>
59 +#include <linux/bug.h>
60 +#include <linux/delay.h>
61 +#include <linux/device.h>
62 +#include <linux/err.h>
63 +#include <linux/gpio/driver.h>
64 +#include <linux/io.h>
65 +#include <linux/irq.h>
66 +#include <linux/irqdesc.h>
67 +#include <linux/init.h>
68 +#include <linux/of_address.h>
69 +#include <linux/of.h>
70 +#include <linux/of_irq.h>
71 +#include <linux/pinctrl/consumer.h>
72 +#include <linux/pinctrl/machine.h>
73 +#include <linux/pinctrl/pinconf.h>
74 +#include <linux/pinctrl/pinctrl.h>
75 +#include <linux/pinctrl/pinmux.h>
76 +#include <linux/pinctrl/pinconf-generic.h>
77 +#include <linux/platform_device.h>
78 +#include <linux/seq_file.h>
79 +#include <linux/spinlock.h>
80 +#include <linux/types.h>
83 +#include "pinctrl-utils.h"
85 +#define MODULE_NAME "pinctrl-rp1"
86 +#define RP1_NUM_GPIOS 54
87 +#define RP1_NUM_BANKS 3
89 +#define RP1_RW_OFFSET 0x0000
90 +#define RP1_XOR_OFFSET 0x1000
91 +#define RP1_SET_OFFSET 0x2000
92 +#define RP1_CLR_OFFSET 0x3000
94 +#define RP1_GPIO_STATUS 0x0000
95 +#define RP1_GPIO_CTRL 0x0004
97 +#define RP1_GPIO_PCIE_INTE 0x011c
98 +#define RP1_GPIO_PCIE_INTS 0x0124
100 +#define RP1_GPIO_EVENTS_SHIFT_RAW 20
101 +#define RP1_GPIO_STATUS_FALLING BIT(20)
102 +#define RP1_GPIO_STATUS_RISING BIT(21)
103 +#define RP1_GPIO_STATUS_LOW BIT(22)
104 +#define RP1_GPIO_STATUS_HIGH BIT(23)
106 +#define RP1_GPIO_EVENTS_SHIFT_FILTERED 24
107 +#define RP1_GPIO_STATUS_F_FALLING BIT(24)
108 +#define RP1_GPIO_STATUS_F_RISING BIT(25)
109 +#define RP1_GPIO_STATUS_F_LOW BIT(26)
110 +#define RP1_GPIO_STATUS_F_HIGH BIT(27)
112 +#define RP1_GPIO_CTRL_FUNCSEL_LSB 0
113 +#define RP1_GPIO_CTRL_FUNCSEL_MASK 0x0000001f
114 +#define RP1_GPIO_CTRL_OUTOVER_LSB 12
115 +#define RP1_GPIO_CTRL_OUTOVER_MASK 0x00003000
116 +#define RP1_GPIO_CTRL_OEOVER_LSB 14
117 +#define RP1_GPIO_CTRL_OEOVER_MASK 0x0000c000
118 +#define RP1_GPIO_CTRL_INOVER_LSB 16
119 +#define RP1_GPIO_CTRL_INOVER_MASK 0x00030000
120 +#define RP1_GPIO_CTRL_IRQEN_FALLING BIT(20)
121 +#define RP1_GPIO_CTRL_IRQEN_RISING BIT(21)
122 +#define RP1_GPIO_CTRL_IRQEN_LOW BIT(22)
123 +#define RP1_GPIO_CTRL_IRQEN_HIGH BIT(23)
124 +#define RP1_GPIO_CTRL_IRQEN_F_FALLING BIT(24)
125 +#define RP1_GPIO_CTRL_IRQEN_F_RISING BIT(25)
126 +#define RP1_GPIO_CTRL_IRQEN_F_LOW BIT(26)
127 +#define RP1_GPIO_CTRL_IRQEN_F_HIGH BIT(27)
128 +#define RP1_GPIO_CTRL_IRQRESET BIT(28)
129 +#define RP1_GPIO_CTRL_IRQOVER_LSB 30
130 +#define RP1_GPIO_CTRL_IRQOVER_MASK 0xc0000000
132 +#define RP1_INT_EDGE_FALLING BIT(0)
133 +#define RP1_INT_EDGE_RISING BIT(1)
134 +#define RP1_INT_LEVEL_LOW BIT(2)
135 +#define RP1_INT_LEVEL_HIGH BIT(3)
136 +#define RP1_INT_MASK 0xf
138 +#define RP1_INT_EDGE_BOTH (RP1_INT_EDGE_FALLING | \
139 + RP1_INT_EDGE_RISING)
140 +#define RP1_PUD_OFF 0
141 +#define RP1_PUD_DOWN 1
142 +#define RP1_PUD_UP 2
144 +#define RP1_FSEL_COUNT 9
146 +#define RP1_FSEL_ALT0 0x00
147 +#define RP1_FSEL_GPIO 0x05
148 +#define RP1_FSEL_NONE 0x09
149 +#define RP1_FSEL_NONE_HW 0x1f
151 +#define RP1_DIR_OUTPUT 0
152 +#define RP1_DIR_INPUT 1
154 +#define RP1_OUTOVER_PERI 0
155 +#define RP1_OUTOVER_INVPERI 1
156 +#define RP1_OUTOVER_LOW 2
157 +#define RP1_OUTOVER_HIGH 3
159 +#define RP1_OEOVER_PERI 0
160 +#define RP1_OEOVER_INVPERI 1
161 +#define RP1_OEOVER_DISABLE 2
162 +#define RP1_OEOVER_ENABLE 3
164 +#define RP1_INOVER_PERI 0
165 +#define RP1_INOVER_INVPERI 1
166 +#define RP1_INOVER_LOW 2
167 +#define RP1_INOVER_HIGH 3
169 +#define RP1_RIO_OUT 0x00
170 +#define RP1_RIO_OE 0x04
171 +#define RP1_RIO_IN 0x08
173 +#define RP1_PAD_SLEWFAST_MASK 0x00000001
174 +#define RP1_PAD_SLEWFAST_LSB 0
175 +#define RP1_PAD_SCHMITT_MASK 0x00000002
176 +#define RP1_PAD_SCHMITT_LSB 1
177 +#define RP1_PAD_PULL_MASK 0x0000000c
178 +#define RP1_PAD_PULL_LSB 2
179 +#define RP1_PAD_DRIVE_MASK 0x00000030
180 +#define RP1_PAD_DRIVE_LSB 4
181 +#define RP1_PAD_IN_ENABLE_MASK 0x00000040
182 +#define RP1_PAD_IN_ENABLE_LSB 6
183 +#define RP1_PAD_OUT_DISABLE_MASK 0x00000080
184 +#define RP1_PAD_OUT_DISABLE_LSB 7
186 +#define RP1_PAD_DRIVE_2MA 0x00000000
187 +#define RP1_PAD_DRIVE_4MA 0x00000010
188 +#define RP1_PAD_DRIVE_8MA 0x00000020
189 +#define RP1_PAD_DRIVE_12MA 0x00000030
191 +#define FLD_GET(r, f) (((r) & (f ## _MASK)) >> (f ## _LSB))
192 +#define FLD_SET(r, f, v) r = (((r) & ~(f ## _MASK)) | ((v) << (f ## _LSB)))
196 +#define RP1_MAX_FSEL 8
197 +#define PIN(i, f0, f1, f2, f3, f4, f5, f6, f7, f8) \
212 +#define LEGACY_MAP(n, f0, f1, f2, f3, f4, f5) \
224 +struct rp1_iobank_desc {
234 +struct rp1_pin_info {
241 + void __iomem *gpio;
243 + void __iomem *inte;
244 + void __iomem *ints;
284 + func_pcie_clkreq_n,
312 + func_count = func__,
313 + func_invalid = func__,
316 +struct rp1_pin_funcs {
317 + u8 funcs[RP1_FSEL_COUNT];
320 +struct rp1_pinctrl {
321 + struct device *dev;
322 + void __iomem *gpio_base;
323 + void __iomem *rio_base;
324 + void __iomem *pads_base;
325 + int irq[RP1_NUM_BANKS];
326 + struct rp1_pin_info pins[RP1_NUM_GPIOS];
328 + struct pinctrl_dev *pctl_dev;
329 + struct gpio_chip gpio_chip;
330 + struct pinctrl_gpio_range gpio_range;
332 + raw_spinlock_t irq_lock[RP1_NUM_BANKS];
335 +const struct rp1_iobank_desc rp1_iobanks[RP1_NUM_BANKS] = {
336 + /* gpio inte ints rio pads */
337 + { 0, 28, 0x0000, 0x011c, 0x0124, 0x0000, 0x0004 },
338 + { 28, 6, 0x4000, 0x411c, 0x4124, 0x4000, 0x4004 },
339 + { 34, 20, 0x8000, 0x811c, 0x8124, 0x8000, 0x8004 },
342 +/* pins are just named GPIO0..GPIO53 */
343 +#define RP1_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
344 +static struct pinctrl_pin_desc rp1_gpio_pins[] = {
401 +/* one pin per group */
402 +static const char * const rp1_gpio_groups[] = {
459 +static const char * const rp1_func_names[] = {
495 + FUNC(pcie_clkreq_n),
522 + [func_invalid] = "?"
525 +static const struct rp1_pin_funcs rp1_gpio_pin_funcs[] = {
526 + PIN(0, spi0, dpi, uart1, i2c0, _, gpio, proc_rio, pio, spi2),
527 + PIN(1, spi0, dpi, uart1, i2c0, _, gpio, proc_rio, pio, spi2),
528 + PIN(2, spi0, dpi, uart1, i2c1, ir, gpio, proc_rio, pio, spi2),
529 + PIN(3, spi0, dpi, uart1, i2c1, ir, gpio, proc_rio, pio, spi2),
530 + PIN(4, gpclk0, dpi, uart2, i2c2, ri0, gpio, proc_rio, pio, spi3),
531 + PIN(5, gpclk1, dpi, uart2, i2c2, dtr0, gpio, proc_rio, pio, spi3),
532 + PIN(6, gpclk2, dpi, uart2, i2c3, dcd0, gpio, proc_rio, pio, spi3),
533 + PIN(7, spi0, dpi, uart2, i2c3, dsr0, gpio, proc_rio, pio, spi3),
534 + PIN(8, spi0, dpi, uart3, i2c0, _, gpio, proc_rio, pio, spi4),
535 + PIN(9, spi0, dpi, uart3, i2c0, _, gpio, proc_rio, pio, spi4),
536 + PIN(10, spi0, dpi, uart3, i2c1, _, gpio, proc_rio, pio, spi4),
537 + PIN(11, spi0, dpi, uart3, i2c1, _, gpio, proc_rio, pio, spi4),
538 + PIN(12, pwm0, dpi, uart4, i2c2, aaud, gpio, proc_rio, pio, spi5),
539 + PIN(13, pwm0, dpi, uart4, i2c2, aaud, gpio, proc_rio, pio, spi5),
540 + PIN(14, pwm0, dpi, uart4, i2c3, uart0, gpio, proc_rio, pio, spi5),
541 + PIN(15, pwm0, dpi, uart4, i2c3, uart0, gpio, proc_rio, pio, spi5),
542 + PIN(16, spi1, dpi, dsi0_te_ext, _, uart0, gpio, proc_rio, pio, _),
543 + PIN(17, spi1, dpi, dsi1_te_ext, _, uart0, gpio, proc_rio, pio, _),
544 + PIN(18, spi1, dpi, i2s0, pwm0, i2s1, gpio, proc_rio, pio, gpclk1),
545 + PIN(19, spi1, dpi, i2s0, pwm0, i2s1, gpio, proc_rio, pio, _),
546 + PIN(20, spi1, dpi, i2s0, gpclk0, i2s1, gpio, proc_rio, pio, _),
547 + PIN(21, spi1, dpi, i2s0, gpclk1, i2s1, gpio, proc_rio, pio, _),
548 + PIN(22, sd0, dpi, i2s0, i2c3, i2s1, gpio, proc_rio, pio, _),
549 + PIN(23, sd0, dpi, i2s0, i2c3, i2s1, gpio, proc_rio, pio, _),
550 + PIN(24, sd0, dpi, i2s0, _, i2s1, gpio, proc_rio, pio, spi2),
551 + PIN(25, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi3),
552 + PIN(26, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi5),
553 + PIN(27, sd0, dpi, i2s0, mic, i2s1, gpio, proc_rio, pio, spi1),
554 + PIN(28, sd1, i2c4, i2s2, spi6, vbus0, gpio, proc_rio, _, _),
555 + PIN(29, sd1, i2c4, i2s2, spi6, vbus0, gpio, proc_rio, _, _),
556 + PIN(30, sd1, i2c5, i2s2, spi6, uart5, gpio, proc_rio, _, _),
557 + PIN(31, sd1, i2c5, i2s2, spi6, uart5, gpio, proc_rio, _, _),
558 + PIN(32, sd1, gpclk3, i2s2, spi6, uart5, gpio, proc_rio, _, _),
559 + PIN(33, sd1, gpclk4, i2s2, spi6, uart5, gpio, proc_rio, _, _),
560 + PIN(34, pwm1, gpclk3, vbus0, i2c4, mic, gpio, proc_rio, _, _),
561 + PIN(35, spi8, pwm1, vbus0, i2c4, mic, gpio, proc_rio, _, _),
562 + PIN(36, spi8, uart5, pcie_clkreq_n, i2c5, mic, gpio, proc_rio, _, _),
563 + PIN(37, spi8, uart5, mic, i2c5, pcie_clkreq_n, gpio, proc_rio, _, _),
564 + PIN(38, spi8, uart5, mic, i2c6, aaud, gpio, proc_rio, dsi0_te_ext, _),
565 + PIN(39, spi8, uart5, mic, i2c6, aaud, gpio, proc_rio, dsi1_te_ext, _),
566 + PIN(40, pwm1, uart5, i2c4, spi6, aaud, gpio, proc_rio, _, _),
567 + PIN(41, pwm1, uart5, i2c4, spi6, aaud, gpio, proc_rio, _, _),
568 + PIN(42, gpclk5, uart5, vbus1, spi6, i2s2, gpio, proc_rio, _, _),
569 + PIN(43, gpclk4, uart5, vbus1, spi6, i2s2, gpio, proc_rio, _, _),
570 + PIN(44, gpclk5, i2c5, pwm1, spi6, i2s2, gpio, proc_rio, _, _),
571 + PIN(45, pwm1, i2c5, spi7, spi6, i2s2, gpio, proc_rio, _, _),
572 + PIN(46, gpclk3, i2c4, spi7, mic, i2s2, gpio, proc_rio, dsi0_te_ext, _),
573 + PIN(47, gpclk5, i2c4, spi7, mic, i2s2, gpio, proc_rio, dsi1_te_ext, _),
574 + PIN(48, pwm1, pcie_clkreq_n, spi7, mic, uart5, gpio, proc_rio, _, _),
575 + PIN(49, spi8, spi7, i2c5, aaud, uart5, gpio, proc_rio, _, _),
576 + PIN(50, spi8, spi7, i2c5, aaud, vbus2, gpio, proc_rio, _, _),
577 + PIN(51, spi8, spi7, i2c6, aaud, vbus2, gpio, proc_rio, _, _),
578 + PIN(52, spi8, _, i2c6, aaud, vbus3, gpio, proc_rio, _, _),
579 + PIN(53, spi8, spi7, _, pcie_clkreq_n, vbus3, gpio, proc_rio, _, _),
582 +static const u8 legacy_fsel_map[][8] = {
583 + LEGACY_MAP(0, i2c0, _, dpi, spi2, uart1, _),
584 + LEGACY_MAP(1, i2c0, _, dpi, spi2, uart1, _),
585 + LEGACY_MAP(2, i2c1, _, dpi, spi2, uart1, _),
586 + LEGACY_MAP(3, i2c1, _, dpi, spi2, uart1, _),
587 + LEGACY_MAP(4, gpclk0, _, dpi, spi3, uart2, i2c2),
588 + LEGACY_MAP(5, gpclk1, _, dpi, spi3, uart2, i2c2),
589 + LEGACY_MAP(6, gpclk2, _, dpi, spi3, uart2, i2c3),
590 + LEGACY_MAP(7, spi0, _, dpi, spi3, uart2, i2c3),
591 + LEGACY_MAP(8, spi0, _, dpi, _, uart3, i2c0),
592 + LEGACY_MAP(9, spi0, _, dpi, _, uart3, i2c0),
593 + LEGACY_MAP(10, spi0, _, dpi, _, uart3, i2c1),
594 + LEGACY_MAP(11, spi0, _, dpi, _, uart3, i2c1),
595 + LEGACY_MAP(12, pwm0, _, dpi, spi5, uart4, i2c2),
596 + LEGACY_MAP(13, pwm0, _, dpi, spi5, uart4, i2c2),
597 + LEGACY_MAP(14, uart0, _, dpi, spi5, uart4, _),
598 + LEGACY_MAP(15, uart0, _, dpi, spi5, uart4, _),
599 + LEGACY_MAP(16, _, _, dpi, uart0, spi1, _),
600 + LEGACY_MAP(17, _, _, dpi, uart0, spi1, _),
601 + LEGACY_MAP(18, i2s0, _, dpi, _, spi1, pwm0),
602 + LEGACY_MAP(19, i2s0, _, dpi, _, spi1, pwm0),
603 + LEGACY_MAP(20, i2s0, _, dpi, _, spi1, gpclk0),
604 + LEGACY_MAP(21, i2s0, _, dpi, _, spi1, gpclk1),
605 + LEGACY_MAP(22, sd0, _, dpi, _, _, i2c3),
606 + LEGACY_MAP(23, sd0, _, dpi, _, _, i2c3),
607 + LEGACY_MAP(24, sd0, _, dpi, _, _, spi2),
608 + LEGACY_MAP(25, sd0, _, dpi, _, _, spi3),
609 + LEGACY_MAP(26, sd0, _, dpi, _, _, spi5),
610 + LEGACY_MAP(27, sd0, _, dpi, _, _, _),
613 +static const char * const irq_type_names[] = {
614 + [IRQ_TYPE_NONE] = "none",
615 + [IRQ_TYPE_EDGE_RISING] = "edge-rising",
616 + [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
617 + [IRQ_TYPE_EDGE_BOTH] = "edge-both",
618 + [IRQ_TYPE_LEVEL_HIGH] = "level-high",
619 + [IRQ_TYPE_LEVEL_LOW] = "level-low",
622 +static int rp1_pinconf_set(struct pinctrl_dev *pctldev,
623 + unsigned int offset, unsigned long *configs,
624 + unsigned int num_configs);
626 +static struct rp1_pin_info *rp1_get_pin(struct gpio_chip *chip,
627 + unsigned int offset)
629 + struct rp1_pinctrl *pc = gpiochip_get_data(chip);
631 + if (pc && offset < RP1_NUM_GPIOS)
632 + return &pc->pins[offset];
636 +static struct rp1_pin_info *rp1_get_pin_pctl(struct pinctrl_dev *pctldev,
637 + unsigned int offset)
639 + struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
641 + if (pc && offset < RP1_NUM_GPIOS)
642 + return &pc->pins[offset];
646 +static void rp1_pad_update(struct rp1_pin_info *pin, u32 clr, u32 set)
648 + u32 padctrl = readl(pin->pad);
653 + writel(padctrl, pin->pad);
656 +static void rp1_input_enable(struct rp1_pin_info *pin, int value)
658 + rp1_pad_update(pin, RP1_PAD_IN_ENABLE_MASK,
659 + value ? RP1_PAD_IN_ENABLE_MASK : 0);
662 +static void rp1_output_enable(struct rp1_pin_info *pin, int value)
664 + rp1_pad_update(pin, RP1_PAD_OUT_DISABLE_MASK,
665 + value ? 0 : RP1_PAD_OUT_DISABLE_MASK);
668 +static u32 rp1_get_fsel(struct rp1_pin_info *pin)
670 + u32 ctrl = readl(pin->gpio + RP1_GPIO_CTRL);
671 + u32 oeover = FLD_GET(ctrl, RP1_GPIO_CTRL_OEOVER);
672 + u32 fsel = FLD_GET(ctrl, RP1_GPIO_CTRL_FUNCSEL);
674 + if (oeover != RP1_OEOVER_PERI || fsel >= RP1_FSEL_COUNT)
675 + fsel = RP1_FSEL_NONE;
680 +static void rp1_set_fsel(struct rp1_pin_info *pin, u32 fsel)
682 + u32 ctrl = readl(pin->gpio + RP1_GPIO_CTRL);
684 + if (fsel >= RP1_FSEL_COUNT)
685 + fsel = RP1_FSEL_NONE_HW;
687 + rp1_input_enable(pin, 1);
688 + rp1_output_enable(pin, 1);
690 + if (fsel == RP1_FSEL_NONE) {
691 + FLD_SET(ctrl, RP1_GPIO_CTRL_OEOVER, RP1_OEOVER_DISABLE);
693 + FLD_SET(ctrl, RP1_GPIO_CTRL_OUTOVER, RP1_OUTOVER_PERI);
694 + FLD_SET(ctrl, RP1_GPIO_CTRL_OEOVER, RP1_OEOVER_PERI);
696 + FLD_SET(ctrl, RP1_GPIO_CTRL_FUNCSEL, fsel);
697 + writel(ctrl, pin->gpio + RP1_GPIO_CTRL);
700 +static int rp1_get_dir(struct rp1_pin_info *pin)
702 + return !(readl(pin->rio + RP1_RIO_OE) & (1 << pin->offset)) ?
703 + RP1_DIR_INPUT : RP1_DIR_OUTPUT;
706 +static void rp1_set_dir(struct rp1_pin_info *pin, bool is_input)
708 + int offset = is_input ? RP1_CLR_OFFSET : RP1_SET_OFFSET;
710 + writel(1 << pin->offset, pin->rio + RP1_RIO_OE + offset);
713 +static int rp1_get_value(struct rp1_pin_info *pin)
715 + return !!(readl(pin->rio + RP1_RIO_IN) & (1 << pin->offset));
718 +static void rp1_set_value(struct rp1_pin_info *pin, int value)
720 + /* Assume the pin is already an output */
721 + writel(1 << pin->offset,
722 + pin->rio + RP1_RIO_OUT + (value ? RP1_SET_OFFSET : RP1_CLR_OFFSET));
725 +static int rp1_gpio_get(struct gpio_chip *chip, unsigned offset)
727 + struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
732 + ret = rp1_get_value(pin);
736 +static void rp1_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
738 + struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
741 + rp1_set_value(pin, value);
744 +static int rp1_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
746 + struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
751 + fsel = rp1_get_fsel(pin);
752 + if (fsel != RP1_FSEL_GPIO)
754 + return (rp1_get_dir(pin) == RP1_DIR_OUTPUT) ?
755 + GPIO_LINE_DIRECTION_OUT :
756 + GPIO_LINE_DIRECTION_IN;
759 +static int rp1_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
761 + struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
765 + rp1_set_dir(pin, RP1_DIR_INPUT);
766 + rp1_set_fsel(pin, RP1_FSEL_GPIO);
770 +static int rp1_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
773 + struct rp1_pin_info *pin = rp1_get_pin(chip, offset);
777 + rp1_set_value(pin, value);
778 + rp1_set_dir(pin, RP1_DIR_OUTPUT);
779 + rp1_set_fsel(pin, RP1_FSEL_GPIO);
783 +static int rp1_gpio_set_config(struct gpio_chip *gc, unsigned offset,
784 + unsigned long config)
786 + struct rp1_pinctrl *pc = gpiochip_get_data(gc);
787 + unsigned long configs[] = { config };
789 + return rp1_pinconf_set(pc->pctl_dev, offset, configs,
790 + ARRAY_SIZE(configs));
793 +static const struct gpio_chip rp1_gpio_chip = {
794 + .label = MODULE_NAME,
795 + .owner = THIS_MODULE,
796 + .request = gpiochip_generic_request,
797 + .free = gpiochip_generic_free,
798 + .direction_input = rp1_gpio_direction_input,
799 + .direction_output = rp1_gpio_direction_output,
800 + .get_direction = rp1_gpio_get_direction,
801 + .get = rp1_gpio_get,
802 + .set = rp1_gpio_set,
804 + .set_config = rp1_gpio_set_config,
805 + .ngpio = RP1_NUM_GPIOS,
806 + .can_sleep = false,
809 +static void rp1_gpio_irq_handler(struct irq_desc *desc)
811 + struct gpio_chip *chip = irq_desc_get_handler_data(desc);
812 + struct rp1_pinctrl *pc = gpiochip_get_data(chip);
813 + struct irq_chip *host_chip = irq_desc_get_chip(desc);
814 + const struct rp1_iobank_desc *bank;
815 + int irq = irq_desc_get_irq(desc);
816 + unsigned long ints;
819 + if (pc->irq[0] == irq)
820 + bank = &rp1_iobanks[0];
821 + else if (pc->irq[1] == irq)
822 + bank = &rp1_iobanks[1];
824 + bank = &rp1_iobanks[2];
826 + chained_irq_enter(host_chip, desc);
828 + ints = readl(pc->gpio_base + bank->ints_offset);
829 + for_each_set_bit(b, &ints, 32) {
830 + struct rp1_pin_info *pin = rp1_get_pin(chip, b);
832 + writel(RP1_GPIO_CTRL_IRQRESET,
833 + pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
834 + generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
835 + bank->gpio_offset + b));
838 + chained_irq_exit(host_chip, desc);
841 +static void rp1_gpio_irq_config(struct rp1_pin_info *pin, bool enable)
843 + writel(1 << pin->offset,
844 + pin->inte + (enable ? RP1_SET_OFFSET : RP1_CLR_OFFSET));
846 + /* Clear any latched events */
847 + writel(RP1_GPIO_CTRL_IRQRESET,
848 + pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
851 +static void rp1_gpio_irq_enable(struct irq_data *data)
853 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
854 + unsigned gpio = irqd_to_hwirq(data);
855 + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
857 + rp1_gpio_irq_config(pin, true);
860 +static void rp1_gpio_irq_disable(struct irq_data *data)
862 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
863 + unsigned gpio = irqd_to_hwirq(data);
864 + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
866 + rp1_gpio_irq_config(pin, false);
869 +static int rp1_irq_set_type(struct rp1_pin_info *pin, unsigned int type)
874 + case IRQ_TYPE_NONE:
877 + case IRQ_TYPE_EDGE_RISING:
878 + irq_flags = RP1_INT_EDGE_RISING;
880 + case IRQ_TYPE_EDGE_FALLING:
881 + irq_flags = RP1_INT_EDGE_FALLING;
883 + case IRQ_TYPE_EDGE_BOTH:
884 + irq_flags = RP1_INT_EDGE_RISING | RP1_INT_EDGE_FALLING;
886 + case IRQ_TYPE_LEVEL_HIGH:
887 + irq_flags = RP1_INT_LEVEL_HIGH;
889 + case IRQ_TYPE_LEVEL_LOW:
890 + irq_flags = RP1_INT_LEVEL_LOW;
897 + /* Clear them all */
898 + writel(RP1_INT_MASK << RP1_GPIO_EVENTS_SHIFT_RAW,
899 + pin->gpio + RP1_CLR_OFFSET + RP1_GPIO_CTRL);
900 + /* Set those that are needed */
901 + writel(irq_flags << RP1_GPIO_EVENTS_SHIFT_RAW,
902 + pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
903 + pin->irq_type = type;
908 +static int rp1_gpio_irq_set_type(struct irq_data *data, unsigned int type)
910 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
911 + struct rp1_pinctrl *pc = gpiochip_get_data(chip);
912 + unsigned gpio = irqd_to_hwirq(data);
913 + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
914 + int bank = pin->bank;
915 + unsigned long flags;
918 + raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
920 + ret = rp1_irq_set_type(pin, type);
922 + if (type & IRQ_TYPE_EDGE_BOTH)
923 + irq_set_handler_locked(data, handle_edge_irq);
925 + irq_set_handler_locked(data, handle_level_irq);
928 + raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
933 +static void rp1_gpio_irq_ack(struct irq_data *data)
935 + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
936 + unsigned gpio = irqd_to_hwirq(data);
937 + struct rp1_pin_info *pin = rp1_get_pin(chip, gpio);
939 + /* Clear any latched events */
940 + writel(RP1_GPIO_CTRL_IRQRESET, pin->gpio + RP1_SET_OFFSET + RP1_GPIO_CTRL);
943 +static struct irq_chip rp1_gpio_irq_chip = {
944 + .name = MODULE_NAME,
945 + .irq_enable = rp1_gpio_irq_enable,
946 + .irq_disable = rp1_gpio_irq_disable,
947 + .irq_set_type = rp1_gpio_irq_set_type,
948 + .irq_ack = rp1_gpio_irq_ack,
949 + .irq_mask = rp1_gpio_irq_disable,
950 + .irq_unmask = rp1_gpio_irq_enable,
951 + .flags = IRQCHIP_IMMUTABLE,
954 +static int rp1_pctl_get_groups_count(struct pinctrl_dev *pctldev)
956 + return ARRAY_SIZE(rp1_gpio_groups);
959 +static const char *rp1_pctl_get_group_name(struct pinctrl_dev *pctldev,
962 + return rp1_gpio_groups[selector];
965 +static enum funcs rp1_get_fsel_func(unsigned pin, unsigned fsel)
967 + if (pin < RP1_NUM_GPIOS) {
968 + if (fsel < RP1_FSEL_COUNT)
969 + return rp1_gpio_pin_funcs[pin].funcs[fsel];
970 + else if (fsel == RP1_FSEL_NONE)
973 + return func_invalid;
976 +static int rp1_pctl_get_group_pins(struct pinctrl_dev *pctldev,
978 + const unsigned **pins,
979 + unsigned *num_pins)
981 + *pins = &rp1_gpio_pins[selector].number;
987 +static void rp1_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
988 + struct seq_file *s,
991 + struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
992 + struct gpio_chip *chip = &pc->gpio_chip;
993 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
994 + u32 fsel = rp1_get_fsel(pin);
995 + enum funcs func = rp1_get_fsel_func(offset, fsel);
996 + int value = rp1_get_value(pin);
997 + int irq = irq_find_mapping(chip->irq.domain, offset);
999 + seq_printf(s, "function %s (%s) in %s; irq %d (%s)",
1000 + rp1_func_names[fsel], rp1_func_names[func],
1001 + value ? "hi" : "lo",
1002 + irq, irq_type_names[pin->irq_type]);
1005 +static void rp1_pctl_dt_free_map(struct pinctrl_dev *pctldev,
1006 + struct pinctrl_map *maps, unsigned num_maps)
1010 + for (i = 0; i < num_maps; i++)
1011 + if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
1012 + kfree(maps[i].data.configs.configs);
1017 +static int rp1_pctl_legacy_map_func(struct rp1_pinctrl *pc,
1018 + struct device_node *np, u32 pin, u32 fnum,
1019 + struct pinctrl_map *maps,
1020 + unsigned int *num_maps)
1022 + struct pinctrl_map *map = &maps[*num_maps];
1025 + if (fnum >= ARRAY_SIZE(legacy_fsel_map[0])) {
1026 + dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
1030 + func = legacy_fsel_map[pin][fnum];
1031 + if (func == func_invalid) {
1032 + dev_err(pc->dev, "%pOF: brcm,function %d not supported on pin %d\n",
1036 + map->type = PIN_MAP_TYPE_MUX_GROUP;
1037 + map->data.mux.group = rp1_gpio_groups[pin];
1038 + map->data.mux.function = rp1_func_names[func];
1044 +static int rp1_pctl_legacy_map_pull(struct rp1_pinctrl *pc,
1045 + struct device_node *np, u32 pin, u32 pull,
1046 + struct pinctrl_map *maps,
1047 + unsigned int *num_maps)
1049 + struct pinctrl_map *map = &maps[*num_maps];
1050 + enum pin_config_param param;
1051 + unsigned long *configs;
1055 + param = PIN_CONFIG_BIAS_DISABLE;
1057 + case RP1_PUD_DOWN:
1058 + param = PIN_CONFIG_BIAS_PULL_DOWN;
1061 + param = PIN_CONFIG_BIAS_PULL_UP;
1064 + dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
1068 + configs = kzalloc(sizeof(*configs), GFP_KERNEL);
1072 + configs[0] = pinconf_to_config_packed(param, 0);
1073 + map->type = PIN_MAP_TYPE_CONFIGS_PIN;
1074 + map->data.configs.group_or_pin = rp1_gpio_pins[pin].name;
1075 + map->data.configs.configs = configs;
1076 + map->data.configs.num_configs = 1;
1082 +static int rp1_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
1083 + struct device_node *np,
1084 + struct pinctrl_map **map,
1085 + unsigned int *num_maps)
1087 + struct rp1_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1088 + struct property *pins, *funcs, *pulls;
1089 + int num_pins, num_funcs, num_pulls, maps_per_pin;
1090 + struct pinctrl_map *maps;
1091 + unsigned long *configs = NULL;
1092 + const char *function = NULL;
1093 + unsigned int reserved_maps;
1094 + int num_configs = 0;
1096 + u32 pin, func, pull;
1098 + /* Check for legacy pin declaration */
1099 + pins = of_find_property(np, "brcm,pins", NULL);
1101 + if (!pins) /* Assume generic bindings in this node */
1102 + return pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
1104 + funcs = of_find_property(np, "brcm,function", NULL);
1106 + of_property_read_string(np, "function", &function);
1108 + pulls = of_find_property(np, "brcm,pull", NULL);
1110 + pinconf_generic_parse_dt_config(np, pctldev, &configs, &num_configs);
1112 + if (!function && !funcs && !num_configs && !pulls) {
1114 + "%pOF: no function, brcm,function, brcm,pull, etc.\n",
1119 + num_pins = pins->length / 4;
1120 + num_funcs = funcs ? (funcs->length / 4) : 0;
1121 + num_pulls = pulls ? (pulls->length / 4) : 0;
1123 + if (num_funcs > 1 && num_funcs != num_pins) {
1125 + "%pOF: brcm,function must have 1 or %d entries\n",
1130 + if (num_pulls > 1 && num_pulls != num_pins) {
1132 + "%pOF: brcm,pull must have 1 or %d entries\n",
1138 + if (function || num_funcs)
1140 + if (num_configs || num_pulls)
1142 + reserved_maps = num_pins * maps_per_pin;
1143 + maps = kcalloc(reserved_maps, sizeof(*maps), GFP_KERNEL);
1149 + for (i = 0; i < num_pins; i++) {
1150 + err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
1153 + if (pin >= ARRAY_SIZE(legacy_fsel_map)) {
1154 + dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
1161 + err = of_property_read_u32_index(np, "brcm,function",
1162 + (num_funcs > 1) ? i : 0,
1166 + err = rp1_pctl_legacy_map_func(pc, np, pin, func,
1168 + } else if (function) {
1169 + err = pinctrl_utils_add_map_mux(pctldev, &maps,
1170 + &reserved_maps, num_maps,
1171 + rp1_gpio_groups[pin],
1179 + err = of_property_read_u32_index(np, "brcm,pull",
1180 + (num_pulls > 1) ? i : 0,
1184 + err = rp1_pctl_legacy_map_pull(pc, np, pin, pull,
1186 + } else if (num_configs) {
1187 + err = pinctrl_utils_add_map_configs(pctldev, &maps,
1188 + &reserved_maps, num_maps,
1189 + rp1_gpio_groups[pin],
1190 + configs, num_configs,
1191 + PIN_MAP_TYPE_CONFIGS_PIN);
1203 + rp1_pctl_dt_free_map(pctldev, maps, reserved_maps);
1207 +static const struct pinctrl_ops rp1_pctl_ops = {
1208 + .get_groups_count = rp1_pctl_get_groups_count,
1209 + .get_group_name = rp1_pctl_get_group_name,
1210 + .get_group_pins = rp1_pctl_get_group_pins,
1211 + .pin_dbg_show = rp1_pctl_pin_dbg_show,
1212 + .dt_node_to_map = rp1_pctl_dt_node_to_map,
1213 + .dt_free_map = rp1_pctl_dt_free_map,
1216 +static int rp1_pmx_free(struct pinctrl_dev *pctldev, unsigned offset)
1218 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1219 + u32 fsel = rp1_get_fsel(pin);
1221 + /* Return non-GPIOs to GPIO_IN */
1222 + if (fsel != RP1_FSEL_GPIO) {
1223 + rp1_set_dir(pin, RP1_DIR_INPUT);
1224 + rp1_set_fsel(pin, RP1_FSEL_GPIO);
1230 +static int rp1_pmx_get_functions_count(struct pinctrl_dev *pctldev)
1232 + return func_count;
1235 +static const char *rp1_pmx_get_function_name(struct pinctrl_dev *pctldev,
1236 + unsigned selector)
1238 + return (selector < func_count) ? rp1_func_names[selector] : NULL;
1241 +static int rp1_pmx_get_function_groups(struct pinctrl_dev *pctldev,
1242 + unsigned selector,
1243 + const char * const **groups,
1244 + unsigned * const num_groups)
1246 + /* every pin can do every function */
1247 + *groups = rp1_gpio_groups;
1248 + *num_groups = ARRAY_SIZE(rp1_gpio_groups);
1253 +static int rp1_pmx_set(struct pinctrl_dev *pctldev, unsigned func_selector,
1254 + unsigned group_selector)
1256 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, group_selector);
1257 + const u8 *pin_funcs;
1260 + /* func_selector is an enum funcs, so needs translation */
1262 + if (func_selector >= RP1_FSEL_COUNT) {
1263 + /* Convert to an fsel number */
1264 + pin_funcs = rp1_gpio_pin_funcs[pin->num].funcs;
1265 + for (fsel = 0; fsel < RP1_FSEL_COUNT; fsel++) {
1266 + if (pin_funcs[fsel] == func_selector)
1270 + fsel = (int)func_selector;
1273 + if (fsel >= RP1_FSEL_COUNT && fsel != RP1_FSEL_NONE)
1276 + rp1_set_fsel(pin, fsel);
1281 +static void rp1_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
1282 + struct pinctrl_gpio_range *range,
1285 + (void)rp1_pmx_free(pctldev, offset);
1288 +static int rp1_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1289 + struct pinctrl_gpio_range *range,
1293 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1295 + rp1_set_dir(pin, input);
1296 + rp1_set_fsel(pin, RP1_FSEL_GPIO);
1301 +static const struct pinmux_ops rp1_pmx_ops = {
1302 + .free = rp1_pmx_free,
1303 + .get_functions_count = rp1_pmx_get_functions_count,
1304 + .get_function_name = rp1_pmx_get_function_name,
1305 + .get_function_groups = rp1_pmx_get_function_groups,
1306 + .set_mux = rp1_pmx_set,
1307 + .gpio_disable_free = rp1_pmx_gpio_disable_free,
1308 + .gpio_set_direction = rp1_pmx_gpio_set_direction,
1311 +static void rp1_pull_config_set(struct rp1_pin_info *pin, unsigned int arg)
1313 + u32 padctrl = readl(pin->pad);
1315 + FLD_SET(padctrl, RP1_PAD_PULL, arg & 0x3);
1317 + writel(padctrl, pin->pad);
1320 +/* Generic pinconf methods */
1322 +static int rp1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int offset,
1323 + unsigned long *configs, unsigned int num_configs)
1325 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1332 + for (i = 0; i < num_configs; i++) {
1333 + param = pinconf_to_config_param(configs[i]);
1334 + arg = pinconf_to_config_argument(configs[i]);
1337 + case PIN_CONFIG_BIAS_DISABLE:
1338 + rp1_pull_config_set(pin, RP1_PUD_OFF);
1341 + case PIN_CONFIG_BIAS_PULL_DOWN:
1342 + rp1_pull_config_set(pin, RP1_PUD_DOWN);
1345 + case PIN_CONFIG_BIAS_PULL_UP:
1346 + rp1_pull_config_set(pin, RP1_PUD_UP);
1349 + case PIN_CONFIG_INPUT_ENABLE:
1350 + rp1_input_enable(pin, arg);
1353 + case PIN_CONFIG_OUTPUT_ENABLE:
1354 + rp1_output_enable(pin, arg);
1357 + case PIN_CONFIG_OUTPUT:
1358 + rp1_set_value(pin, arg);
1359 + rp1_set_dir(pin, RP1_DIR_OUTPUT);
1360 + rp1_set_fsel(pin, RP1_FSEL_GPIO);
1363 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1364 + rp1_pad_update(pin, RP1_PAD_SCHMITT_MASK,
1365 + arg ? RP1_PAD_SCHMITT_MASK : 0);
1368 + case PIN_CONFIG_SLEW_RATE:
1369 + rp1_pad_update(pin, RP1_PAD_SLEWFAST_MASK,
1370 + arg ? RP1_PAD_SLEWFAST_MASK : 0);
1373 + case PIN_CONFIG_DRIVE_STRENGTH:
1376 + arg = RP1_PAD_DRIVE_2MA;
1379 + arg = RP1_PAD_DRIVE_4MA;
1382 + arg = RP1_PAD_DRIVE_8MA;
1385 + arg = RP1_PAD_DRIVE_12MA;
1390 + rp1_pad_update(pin, RP1_PAD_DRIVE_MASK, arg);
1396 + } /* switch param type */
1397 + } /* for each config */
1402 +static int rp1_pinconf_get(struct pinctrl_dev *pctldev, unsigned offset,
1403 + unsigned long *config)
1405 + struct rp1_pin_info *pin = rp1_get_pin_pctl(pctldev, offset);
1406 + enum pin_config_param param = pinconf_to_config_param(*config);
1413 + padctrl = readl(pin->pad);
1416 + case PIN_CONFIG_INPUT_ENABLE:
1417 + arg = !!(padctrl & RP1_PAD_IN_ENABLE_MASK);
1419 + case PIN_CONFIG_OUTPUT_ENABLE:
1420 + arg = !(padctrl & RP1_PAD_OUT_DISABLE_MASK);
1422 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1423 + arg = !!(padctrl & RP1_PAD_SCHMITT_MASK);
1425 + case PIN_CONFIG_SLEW_RATE:
1426 + arg = !!(padctrl & RP1_PAD_SLEWFAST_MASK);
1428 + case PIN_CONFIG_DRIVE_STRENGTH:
1429 + switch (padctrl & RP1_PAD_DRIVE_MASK) {
1430 + case RP1_PAD_DRIVE_2MA:
1433 + case RP1_PAD_DRIVE_4MA:
1436 + case RP1_PAD_DRIVE_8MA:
1439 + case RP1_PAD_DRIVE_12MA:
1444 + case PIN_CONFIG_BIAS_DISABLE:
1445 + arg = ((padctrl & RP1_PAD_PULL_MASK) == (RP1_PUD_OFF << RP1_PAD_PULL_LSB));
1447 + case PIN_CONFIG_BIAS_PULL_DOWN:
1448 + arg = ((padctrl & RP1_PAD_PULL_MASK) == (RP1_PUD_DOWN << RP1_PAD_PULL_LSB));
1451 + case PIN_CONFIG_BIAS_PULL_UP:
1452 + arg = ((padctrl & RP1_PAD_PULL_MASK) == (RP1_PUD_UP << RP1_PAD_PULL_LSB));
1458 + *config = pinconf_to_config_packed(param, arg);
1463 +static const struct pinconf_ops rp1_pinconf_ops = {
1464 + .is_generic = true,
1465 + .pin_config_get = rp1_pinconf_get,
1466 + .pin_config_set = rp1_pinconf_set,
1469 +static struct pinctrl_desc rp1_pinctrl_desc = {
1470 + .name = MODULE_NAME,
1471 + .pins = rp1_gpio_pins,
1472 + .npins = ARRAY_SIZE(rp1_gpio_pins),
1473 + .pctlops = &rp1_pctl_ops,
1474 + .pmxops = &rp1_pmx_ops,
1475 + .confops = &rp1_pinconf_ops,
1476 + .owner = THIS_MODULE,
1479 +static struct pinctrl_gpio_range rp1_pinctrl_gpio_range = {
1480 + .name = MODULE_NAME,
1481 + .npins = RP1_NUM_GPIOS,
1484 +static const struct of_device_id rp1_pinctrl_match[] = {
1486 + .compatible = "raspberrypi,rp1-gpio",
1487 + .data = &rp1_pinconf_ops,
1492 +static inline void __iomem *devm_auto_iomap(struct platform_device *pdev,
1493 + unsigned int index)
1495 + struct device *dev = &pdev->dev;
1496 + struct device_node *np = dev->of_node;
1499 + return devm_of_iomap(dev, np, (int)index, NULL);
1501 + return devm_platform_ioremap_resource(pdev, index);
1504 +static int rp1_pinctrl_probe(struct platform_device *pdev)
1506 + struct device *dev = &pdev->dev;
1507 + struct device_node *np = dev->of_node;
1508 + struct rp1_pinctrl *pc;
1509 + struct gpio_irq_chip *girq;
1512 + BUILD_BUG_ON(ARRAY_SIZE(rp1_gpio_pins) != RP1_NUM_GPIOS);
1513 + BUILD_BUG_ON(ARRAY_SIZE(rp1_gpio_groups) != RP1_NUM_GPIOS);
1515 + pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1519 + platform_set_drvdata(pdev, pc);
1522 + pc->gpio_base = devm_auto_iomap(pdev, 0);
1523 + if (IS_ERR(pc->gpio_base)) {
1524 + dev_err(dev, "could not get GPIO IO memory\n");
1525 + return PTR_ERR(pc->gpio_base);
1528 + pc->rio_base = devm_auto_iomap(pdev, 1);
1529 + if (IS_ERR(pc->rio_base)) {
1530 + dev_err(dev, "could not get RIO IO memory\n");
1531 + return PTR_ERR(pc->rio_base);
1534 + pc->pads_base = devm_auto_iomap(pdev, 2);
1535 + if (IS_ERR(pc->pads_base)) {
1536 + dev_err(dev, "could not get PADS IO memory\n");
1537 + return PTR_ERR(pc->pads_base);
1540 + pc->gpio_chip = rp1_gpio_chip;
1541 + pc->gpio_chip.parent = dev;
1543 + for (i = 0; i < RP1_NUM_BANKS; i++) {
1544 + const struct rp1_iobank_desc *bank = &rp1_iobanks[i];
1547 + for (j = 0; j < bank->num_gpios; j++) {
1548 + struct rp1_pin_info *pin =
1549 + &pc->pins[bank->min_gpio + j];
1551 + pin->num = bank->min_gpio + j;
1555 + pin->gpio = pc->gpio_base + bank->gpio_offset +
1556 + j * sizeof(u32) * 2;
1557 + pin->inte = pc->gpio_base + bank->inte_offset;
1558 + pin->ints = pc->gpio_base + bank->ints_offset;
1559 + pin->rio = pc->rio_base + bank->rio_offset;
1560 + pin->pad = pc->pads_base + bank->pads_offset +
1564 + raw_spin_lock_init(&pc->irq_lock[i]);
1567 + pc->pctl_dev = devm_pinctrl_register(dev, &rp1_pinctrl_desc, pc);
1568 + if (IS_ERR(pc->pctl_dev))
1569 + return PTR_ERR(pc->pctl_dev);
1571 + girq = &pc->gpio_chip.irq;
1572 + girq->chip = &rp1_gpio_irq_chip;
1573 + girq->parent_handler = rp1_gpio_irq_handler;
1574 + girq->num_parents = RP1_NUM_BANKS;
1575 + girq->parents = pc->irq;
1578 + * Use the same handler for all groups: this is necessary
1579 + * since we use one gpiochip to cover all lines - the
1580 + * irq handler then needs to figure out which group and
1581 + * bank that was firing the IRQ and look up the per-group
1584 + for (i = 0; i < RP1_NUM_BANKS; i++) {
1585 + pc->irq[i] = irq_of_parse_and_map(np, i);
1586 + if (!pc->irq[i]) {
1587 + girq->num_parents = i;
1592 + girq->default_type = IRQ_TYPE_NONE;
1593 + girq->handler = handle_level_irq;
1595 + err = devm_gpiochip_add_data(dev, &pc->gpio_chip, pc);
1597 + dev_err(dev, "could not add GPIO chip\n");
1601 + pc->gpio_range = rp1_pinctrl_gpio_range;
1602 + pc->gpio_range.base = pc->gpio_chip.base;
1603 + pc->gpio_range.gc = &pc->gpio_chip;
1604 + pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1609 +static struct platform_driver rp1_pinctrl_driver = {
1610 + .probe = rp1_pinctrl_probe,
1612 + .name = MODULE_NAME,
1613 + .of_match_table = rp1_pinctrl_match,
1614 + .suppress_bind_attrs = true,
1617 +builtin_platform_driver(rp1_pinctrl_driver);
1618 --- a/include/dt-bindings/pinctrl/rp1.h
1621 -/* SPDX-License-Identifier: GPL-2.0 */
1623 - * Header providing constants for RP1 pinctrl bindings.
1625 - * Copyright (C) 2019-2022 Raspberry Pi Ltd.
1628 -#ifndef __DT_BINDINGS_PINCTRL_RP1_H__
1629 -#define __DT_BINDINGS_PINCTRL_RP1_H__
1631 -/* brcm,function property */
1632 -#define RP1_FSEL_GPIO_IN 0
1633 -#define RP1_FSEL_GPIO_OUT 1
1634 -#define RP1_FSEL_ALT0_LEGACY 4
1635 -#define RP1_FSEL_ALT1_LEGACY 5
1636 -#define RP1_FSEL_ALT2_LEGACY 6
1637 -#define RP1_FSEL_ALT3_LEGACY 7
1638 -#define RP1_FSEL_ALT4_LEGACY 3
1639 -#define RP1_FSEL_ALT5_LEGACY 2
1640 -#define RP1_FSEL_ALT0 0x08
1641 -#define RP1_FSEL_ALT0INV 0x09
1642 -#define RP1_FSEL_ALT1 0x0a
1643 -#define RP1_FSEL_ALT1INV 0x0b
1644 -#define RP1_FSEL_ALT2 0x0c
1645 -#define RP1_FSEL_ALT2INV 0x0d
1646 -#define RP1_FSEL_ALT3 0x0e
1647 -#define RP1_FSEL_ALT3INV 0x0f
1648 -#define RP1_FSEL_ALT4 0x10
1649 -#define RP1_FSEL_ALT4INV 0x11
1650 -#define RP1_FSEL_ALT5 0x12
1651 -#define RP1_FSEL_ALT5INV 0x13
1652 -#define RP1_FSEL_ALT6 0x14
1653 -#define RP1_FSEL_ALT6INV 0x15
1654 -#define RP1_FSEL_ALT7 0x16
1655 -#define RP1_FSEL_ALT7INV 0x17
1656 -#define RP1_FSEL_ALT8 0x18
1657 -#define RP1_FSEL_ALT8INV 0x19
1658 -#define RP1_FSEL_NONE 0x1a
1660 -/* brcm,pull property */
1661 -#define RP1_PUD_OFF 0
1662 -#define RP1_PUD_DOWN 1
1663 -#define RP1_PUD_UP 2
1664 -#define RP1_PUD_KEEP 3
1666 -#endif /* __DT_BINDINGS_PINCTRL_RP1_H__ */