1 From fa2571d625bb53b642cd9f29a7cfc3434e1cf576 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime@cerno.tech>
3 Date: Fri, 17 Feb 2023 13:07:36 +0100
4 Subject: [PATCH] drm/vc4: Introduce generation number enum
6 With the introduction of the BCM2712 support, we will get yet another
7 generation of display engine to support.
9 The binary check of whether it's VC5 or not thus doesn't work anymore,
10 especially since some parts of the driver will have changed with BCM2711,
11 and some others with BCM2712.
13 Let's introduce an enum to store the generation the driver is running
14 on, which should provide more flexibility.
16 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
18 drivers/gpu/drm/vc4/tests/vc4_mock.c | 12 +++---
19 drivers/gpu/drm/vc4/vc4_bo.c | 28 ++++++------
20 drivers/gpu/drm/vc4/vc4_crtc.c | 14 +++---
21 drivers/gpu/drm/vc4/vc4_drv.c | 22 ++++++----
22 drivers/gpu/drm/vc4/vc4_drv.h | 7 ++-
23 drivers/gpu/drm/vc4/vc4_gem.c | 24 +++++------
24 drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +-
25 drivers/gpu/drm/vc4/vc4_hvs.c | 50 ++++++++++++----------
26 drivers/gpu/drm/vc4/vc4_irq.c | 10 ++---
27 drivers/gpu/drm/vc4/vc4_kms.c | 14 +++---
28 drivers/gpu/drm/vc4/vc4_perfmon.c | 20 ++++-----
29 drivers/gpu/drm/vc4/vc4_plane.c | 12 +++---
30 drivers/gpu/drm/vc4/vc4_render_cl.c | 2 +-
31 drivers/gpu/drm/vc4/vc4_v3d.c | 10 ++---
32 drivers/gpu/drm/vc4/vc4_validate.c | 8 ++--
33 drivers/gpu/drm/vc4/vc4_validate_shaders.c | 2 +-
34 16 files changed, 126 insertions(+), 111 deletions(-)
36 --- a/drivers/gpu/drm/vc4/tests/vc4_mock.c
37 +++ b/drivers/gpu/drm/vc4/tests/vc4_mock.c
38 @@ -153,11 +153,11 @@ static int __build_mock(struct kunit *te
42 -static struct vc4_dev *__mock_device(struct kunit *test, bool is_vc5)
43 +static struct vc4_dev *__mock_device(struct kunit *test, enum vc4_gen gen)
45 struct drm_device *drm;
46 - const struct drm_driver *drv = is_vc5 ? &vc5_drm_driver : &vc4_drm_driver;
47 - const struct vc4_mock_desc *desc = is_vc5 ? &vc5_mock : &vc4_mock;
48 + const struct drm_driver *drv = (gen == VC4_GEN_5) ? &vc5_drm_driver : &vc4_drm_driver;
49 + const struct vc4_mock_desc *desc = (gen == VC4_GEN_5) ? &vc5_mock : &vc4_mock;
53 @@ -171,7 +171,7 @@ static struct vc4_dev *__mock_device(str
54 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, vc4);
57 - vc4->is_vc5 = is_vc5;
60 vc4->hvs = __vc4_hvs_alloc(vc4, NULL);
61 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, vc4->hvs);
62 @@ -191,10 +191,10 @@ static struct vc4_dev *__mock_device(str
64 struct vc4_dev *vc4_mock_device(struct kunit *test)
66 - return __mock_device(test, false);
67 + return __mock_device(test, VC4_GEN_4);
70 struct vc4_dev *vc5_mock_device(struct kunit *test)
72 - return __mock_device(test, true);
73 + return __mock_device(test, VC4_GEN_5);
75 --- a/drivers/gpu/drm/vc4/vc4_bo.c
76 +++ b/drivers/gpu/drm/vc4/vc4_bo.c
77 @@ -251,7 +251,7 @@ void vc4_bo_add_to_purgeable_pool(struct
79 struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
81 - if (WARN_ON_ONCE(vc4->is_vc5))
82 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
85 mutex_lock(&vc4->purgeable.lock);
86 @@ -265,7 +265,7 @@ static void vc4_bo_remove_from_purgeable
88 struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
90 - if (WARN_ON_ONCE(vc4->is_vc5))
91 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
94 /* list_del_init() is used here because the caller might release
95 @@ -396,7 +396,7 @@ struct drm_gem_object *vc4_create_object
96 struct vc4_dev *vc4 = to_vc4_dev(dev);
99 - if (WARN_ON_ONCE(vc4->is_vc5))
100 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
101 return ERR_PTR(-ENODEV);
103 bo = kzalloc(sizeof(*bo), GFP_KERNEL);
104 @@ -427,7 +427,7 @@ struct vc4_bo *vc4_bo_create(struct drm_
105 struct drm_gem_dma_object *dma_obj;
108 - if (WARN_ON_ONCE(vc4->is_vc5))
109 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
110 return ERR_PTR(-ENODEV);
113 @@ -496,7 +496,7 @@ int vc4_bo_dumb_create(struct drm_file *
114 struct vc4_bo *bo = NULL;
117 - if (WARN_ON_ONCE(vc4->is_vc5))
118 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
121 ret = vc4_dumb_fixup_args(args);
122 @@ -622,7 +622,7 @@ int vc4_bo_inc_usecnt(struct vc4_bo *bo)
123 struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
126 - if (WARN_ON_ONCE(vc4->is_vc5))
127 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
130 /* Fast path: if the BO is already retained by someone, no need to
131 @@ -661,7 +661,7 @@ void vc4_bo_dec_usecnt(struct vc4_bo *bo
133 struct vc4_dev *vc4 = to_vc4_dev(bo->base.base.dev);
135 - if (WARN_ON_ONCE(vc4->is_vc5))
136 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
139 /* Fast path: if the BO is still retained by someone, no need to test
140 @@ -783,7 +783,7 @@ int vc4_create_bo_ioctl(struct drm_devic
141 struct vc4_bo *bo = NULL;
144 - if (WARN_ON_ONCE(vc4->is_vc5))
145 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
148 ret = vc4_grab_bin_bo(vc4, vc4file);
149 @@ -813,7 +813,7 @@ int vc4_mmap_bo_ioctl(struct drm_device
150 struct drm_vc4_mmap_bo *args = data;
151 struct drm_gem_object *gem_obj;
153 - if (WARN_ON_ONCE(vc4->is_vc5))
154 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
157 gem_obj = drm_gem_object_lookup(file_priv, args->handle);
158 @@ -839,7 +839,7 @@ vc4_create_shader_bo_ioctl(struct drm_de
159 struct vc4_bo *bo = NULL;
162 - if (WARN_ON_ONCE(vc4->is_vc5))
163 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
167 @@ -918,7 +918,7 @@ int vc4_set_tiling_ioctl(struct drm_devi
171 - if (WARN_ON_ONCE(vc4->is_vc5))
172 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
175 if (args->flags != 0)
176 @@ -964,7 +964,7 @@ int vc4_get_tiling_ioctl(struct drm_devi
177 struct drm_gem_object *gem_obj;
180 - if (WARN_ON_ONCE(vc4->is_vc5))
181 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
184 if (args->flags != 0 || args->modifier != 0)
185 @@ -1011,7 +1011,7 @@ int vc4_bo_cache_init(struct drm_device
189 - if (WARN_ON_ONCE(vc4->is_vc5))
190 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
193 /* Create the initial set of BO labels that the kernel will
194 @@ -1075,7 +1075,7 @@ int vc4_label_bo_ioctl(struct drm_device
195 struct drm_gem_object *gem_obj;
198 - if (WARN_ON_ONCE(vc4->is_vc5))
199 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
203 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
204 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
205 @@ -263,7 +263,7 @@ static u32 vc4_get_fifo_full_level(struc
206 * Removing 1 from the FIFO full level however
207 * seems to completely remove that issue.
210 + if (vc4->gen == VC4_GEN_4)
211 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
213 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
214 @@ -445,7 +445,7 @@ static void vc4_crtc_config_pv(struct dr
216 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
219 + if (vc4->gen == VC4_GEN_5)
220 CRTC_WRITE(PV_MUX_CFG,
221 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
222 PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
223 @@ -936,7 +936,7 @@ static int vc4_async_set_fence_cb(struct
224 struct dma_fence *fence;
227 - if (!vc4->is_vc5) {
228 + if (vc4->gen == VC4_GEN_4) {
229 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);
231 return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
232 @@ -1023,7 +1023,7 @@ static int vc4_async_page_flip(struct dr
233 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);
236 - if (WARN_ON_ONCE(vc4->is_vc5))
237 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
241 @@ -1066,7 +1066,7 @@ int vc4_page_flip(struct drm_crtc *crtc,
242 struct drm_device *dev = crtc->dev;
243 struct vc4_dev *vc4 = to_vc4_dev(dev);
246 + if (vc4->gen == VC4_GEN_5)
247 return vc5_async_page_flip(crtc, fb, event, flags);
249 return vc4_async_page_flip(crtc, fb, event, flags);
250 @@ -1358,13 +1358,13 @@ int __vc4_crtc_init(struct drm_device *d
252 drm_crtc_helper_add(crtc, crtc_helper_funcs);
254 - if (!vc4->is_vc5) {
255 + if (vc4->gen == VC4_GEN_4) {
256 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
257 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
261 - if (!vc4->is_vc5) {
262 + if (vc4->gen == VC4_GEN_4) {
263 /* We support CTM, but only for one CRTC at a time. It's therefore
264 * implemented as private driver state in vc4_kms, not here.
266 --- a/drivers/gpu/drm/vc4/vc4_drv.c
267 +++ b/drivers/gpu/drm/vc4/vc4_drv.c
268 @@ -98,7 +98,7 @@ static int vc4_get_param_ioctl(struct dr
272 - if (WARN_ON_ONCE(vc4->is_vc5))
273 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
277 @@ -147,7 +147,7 @@ static int vc4_open(struct drm_device *d
278 struct vc4_dev *vc4 = to_vc4_dev(dev);
279 struct vc4_file *vc4file;
281 - if (WARN_ON_ONCE(vc4->is_vc5))
282 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
285 vc4file = kzalloc(sizeof(*vc4file), GFP_KERNEL);
286 @@ -165,7 +165,7 @@ static void vc4_close(struct drm_device
287 struct vc4_dev *vc4 = to_vc4_dev(dev);
288 struct vc4_file *vc4file = file->driver_priv;
290 - if (WARN_ON_ONCE(vc4->is_vc5))
291 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
294 if (vc4file->bin_bo_used)
295 @@ -305,13 +305,17 @@ static int vc4_drm_bind(struct device *d
297 struct device_node *node;
298 struct drm_crtc *crtc;
303 dev->coherent_dma_mask = DMA_BIT_MASK(32);
305 - is_vc5 = of_device_is_compatible(dev->of_node, "brcm,bcm2711-vc5");
307 + if (of_device_is_compatible(dev->of_node, "brcm,bcm2711-vc5"))
312 + if (gen == VC4_GEN_5)
313 driver = &vc5_drm_driver;
315 driver = &vc4_drm_driver;
316 @@ -329,14 +333,14 @@ static int vc4_drm_bind(struct device *d
317 vc4 = devm_drm_dev_alloc(dev, driver, struct vc4_dev, base);
320 - vc4->is_vc5 = is_vc5;
325 platform_set_drvdata(pdev, drm);
326 INIT_LIST_HEAD(&vc4->debugfs_list);
329 + if (gen == VC4_GEN_4) {
330 ret = drmm_mutex_init(drm, &vc4->bin_bo_lock);
333 @@ -350,7 +354,7 @@ static int vc4_drm_bind(struct device *d
338 + if (gen == VC4_GEN_4) {
339 ret = vc4_gem_init(drm);
342 --- a/drivers/gpu/drm/vc4/vc4_drv.h
343 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
344 @@ -80,11 +80,16 @@ struct vc4_perfmon {
354 struct drm_device base;
362 --- a/drivers/gpu/drm/vc4/vc4_gem.c
363 +++ b/drivers/gpu/drm/vc4/vc4_gem.c
364 @@ -76,7 +76,7 @@ vc4_get_hang_state_ioctl(struct drm_devi
368 - if (WARN_ON_ONCE(vc4->is_vc5))
369 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
373 @@ -389,7 +389,7 @@ vc4_wait_for_seqno(struct drm_device *de
374 unsigned long timeout_expire;
377 - if (WARN_ON_ONCE(vc4->is_vc5))
378 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
381 if (vc4->finished_seqno >= seqno)
382 @@ -474,7 +474,7 @@ vc4_submit_next_bin_job(struct drm_devic
383 struct vc4_dev *vc4 = to_vc4_dev(dev);
384 struct vc4_exec_info *exec;
386 - if (WARN_ON_ONCE(vc4->is_vc5))
387 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
391 @@ -522,7 +522,7 @@ vc4_submit_next_render_job(struct drm_de
395 - if (WARN_ON_ONCE(vc4->is_vc5))
396 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
399 /* A previous RCL may have written to one of our textures, and
400 @@ -543,7 +543,7 @@ vc4_move_job_to_render(struct drm_device
401 struct vc4_dev *vc4 = to_vc4_dev(dev);
402 bool was_empty = list_empty(&vc4->render_job_list);
404 - if (WARN_ON_ONCE(vc4->is_vc5))
405 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
408 list_move_tail(&exec->head, &vc4->render_job_list);
409 @@ -1012,7 +1012,7 @@ vc4_job_handle_completed(struct vc4_dev
410 unsigned long irqflags;
411 struct vc4_seqno_cb *cb, *cb_temp;
413 - if (WARN_ON_ONCE(vc4->is_vc5))
414 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
417 spin_lock_irqsave(&vc4->job_lock, irqflags);
418 @@ -1051,7 +1051,7 @@ int vc4_queue_seqno_cb(struct drm_device
419 struct vc4_dev *vc4 = to_vc4_dev(dev);
420 unsigned long irqflags;
422 - if (WARN_ON_ONCE(vc4->is_vc5))
423 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
427 @@ -1107,7 +1107,7 @@ vc4_wait_seqno_ioctl(struct drm_device *
428 struct vc4_dev *vc4 = to_vc4_dev(dev);
429 struct drm_vc4_wait_seqno *args = data;
431 - if (WARN_ON_ONCE(vc4->is_vc5))
432 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
435 return vc4_wait_for_seqno_ioctl_helper(dev, args->seqno,
436 @@ -1124,7 +1124,7 @@ vc4_wait_bo_ioctl(struct drm_device *dev
437 struct drm_gem_object *gem_obj;
440 - if (WARN_ON_ONCE(vc4->is_vc5))
441 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
445 @@ -1173,7 +1173,7 @@ vc4_submit_cl_ioctl(struct drm_device *d
446 args->shader_rec_size,
447 args->bo_handle_count);
449 - if (WARN_ON_ONCE(vc4->is_vc5))
450 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
454 @@ -1310,7 +1310,7 @@ int vc4_gem_init(struct drm_device *dev)
455 struct vc4_dev *vc4 = to_vc4_dev(dev);
458 - if (WARN_ON_ONCE(vc4->is_vc5))
459 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
462 vc4->dma_fence_context = dma_fence_context_alloc(1);
463 @@ -1369,7 +1369,7 @@ int vc4_gem_madvise_ioctl(struct drm_dev
467 - if (WARN_ON_ONCE(vc4->is_vc5))
468 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
471 switch (args->madv) {
472 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
473 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
474 @@ -2614,7 +2614,7 @@ static int vc4_hdmi_audio_prepare(struct
475 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
477 /* Set the MAI threshold */
479 + if (vc4->gen >= VC4_GEN_5)
480 HDMI_WRITE(HDMI_MAI_THR,
481 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
482 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
483 --- a/drivers/gpu/drm/vc4/vc4_hvs.c
484 +++ b/drivers/gpu/drm/vc4/vc4_hvs.c
485 @@ -416,7 +416,7 @@ static void vc4_hvs_irq_enable_eof(const
486 unsigned int channel)
488 struct vc4_dev *vc4 = hvs->vc4;
489 - u32 irq_mask = vc4->is_vc5 ?
490 + u32 irq_mask = vc4->gen == VC4_GEN_5 ?
491 SCALER5_DISPCTRL_DSPEIEOF(channel) :
492 SCALER_DISPCTRL_DSPEIEOF(channel);
494 @@ -428,7 +428,7 @@ static void vc4_hvs_irq_clear_eof(const
495 unsigned int channel)
497 struct vc4_dev *vc4 = hvs->vc4;
498 - u32 irq_mask = vc4->is_vc5 ?
499 + u32 irq_mask = vc4->gen == VC4_GEN_5 ?
500 SCALER5_DISPCTRL_DSPEIEOF(channel) :
501 SCALER_DISPCTRL_DSPEIEOF(channel);
503 @@ -620,7 +620,7 @@ int vc4_hvs_get_fifo_from_output(struct
508 + if (vc4->gen == VC4_GEN_4)
512 @@ -701,7 +701,7 @@ static int vc4_hvs_init_channel(struct v
513 dispctrl = SCALER_DISPCTRLX_ENABLE;
514 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan));
516 - if (!vc4->is_vc5) {
517 + if (vc4->gen == VC4_GEN_4) {
518 dispctrl |= VC4_SET_FIELD(mode->hdisplay,
519 SCALER_DISPCTRLX_WIDTH) |
520 VC4_SET_FIELD(mode->vdisplay,
521 @@ -732,7 +732,7 @@ static int vc4_hvs_init_channel(struct v
522 /* Reload the LUT, since the SRAMs would have been disabled if
523 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
526 + if (vc4->gen == VC4_GEN_4)
527 vc4_hvs_lut_load(hvs, vc4_crtc);
529 vc5_hvs_lut_load(hvs, vc4_crtc);
530 @@ -782,7 +782,7 @@ static int vc4_hvs_gamma_check(struct dr
531 struct drm_device *dev = crtc->dev;
532 struct vc4_dev *vc4 = to_vc4_dev(dev);
535 + if (vc4->gen == VC4_GEN_4)
538 if (!crtc_state->color_mgmt_changed)
539 @@ -1036,7 +1036,7 @@ void vc4_hvs_atomic_flush(struct drm_crt
540 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel));
542 if (crtc->state->gamma_lut) {
543 - if (!vc4->is_vc5) {
544 + if (vc4->gen == VC4_GEN_4) {
545 vc4_hvs_update_gamma_lut(hvs, vc4_crtc);
546 dispbkgndx |= SCALER_DISPBKGND_GAMMA;
548 @@ -1053,7 +1053,7 @@ void vc4_hvs_atomic_flush(struct drm_crt
549 * should already be disabling/enabling the pipeline
550 * when gamma changes.
553 + if (vc4->gen == VC4_GEN_4)
554 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA;
556 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx);
557 @@ -1069,7 +1069,8 @@ void vc4_hvs_atomic_flush(struct drm_crt
559 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel)
561 - struct drm_device *drm = &hvs->vc4->base;
562 + struct vc4_dev *vc4 = hvs->vc4;
563 + struct drm_device *drm = &vc4->base;
567 @@ -1077,8 +1078,9 @@ void vc4_hvs_mask_underrun(struct vc4_hv
570 dispctrl = HVS_READ(SCALER_DISPCTRL);
571 - dispctrl &= ~(hvs->vc4->is_vc5 ? SCALER5_DISPCTRL_DSPEISLUR(channel) :
572 - SCALER_DISPCTRL_DSPEISLUR(channel));
573 + dispctrl &= ~((vc4->gen == VC4_GEN_5) ?
574 + SCALER5_DISPCTRL_DSPEISLUR(channel) :
575 + SCALER_DISPCTRL_DSPEISLUR(channel));
577 HVS_WRITE(SCALER_DISPCTRL, dispctrl);
579 @@ -1087,7 +1089,8 @@ void vc4_hvs_mask_underrun(struct vc4_hv
581 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel)
583 - struct drm_device *drm = &hvs->vc4->base;
584 + struct vc4_dev *vc4 = hvs->vc4;
585 + struct drm_device *drm = &vc4->base;
589 @@ -1095,8 +1098,9 @@ void vc4_hvs_unmask_underrun(struct vc4_
592 dispctrl = HVS_READ(SCALER_DISPCTRL);
593 - dispctrl |= (hvs->vc4->is_vc5 ? SCALER5_DISPCTRL_DSPEISLUR(channel) :
594 - SCALER_DISPCTRL_DSPEISLUR(channel));
595 + dispctrl |= ((vc4->gen == VC4_GEN_5) ?
596 + SCALER5_DISPCTRL_DSPEISLUR(channel) :
597 + SCALER_DISPCTRL_DSPEISLUR(channel));
599 HVS_WRITE(SCALER_DISPSTAT,
600 SCALER_DISPSTAT_EUFLOW(channel));
601 @@ -1139,8 +1143,10 @@ static irqreturn_t vc4_hvs_irq_handler(i
602 control = HVS_READ(SCALER_DISPCTRL);
604 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {
605 - dspeislur = vc4->is_vc5 ? SCALER5_DISPCTRL_DSPEISLUR(channel) :
606 - SCALER_DISPCTRL_DSPEISLUR(channel);
607 + dspeislur = (vc4->gen == VC4_GEN_5) ?
608 + SCALER5_DISPCTRL_DSPEISLUR(channel) :
609 + SCALER_DISPCTRL_DSPEISLUR(channel);
611 /* Interrupt masking is not always honored, so check it here. */
612 if (status & SCALER_DISPSTAT_EUFLOW(channel) &&
613 control & dspeislur) {
614 @@ -1177,7 +1183,7 @@ int vc4_hvs_debugfs_init(struct drm_mino
618 - if (!vc4->is_vc5) {
619 + if (vc4->gen == VC4_GEN_4) {
620 debugfs_create_bool("hvs_load_tracker", S_IRUGO | S_IWUSR,
622 &vc4->load_tracker_enabled);
623 @@ -1235,7 +1241,7 @@ struct vc4_hvs *__vc4_hvs_alloc(struct v
624 * between planes when they don't overlap on the screen, but
625 * for now we just allocate globally.
628 + if (vc4->gen == VC4_GEN_4)
629 /* 48k words of 2x12-bit pixels */
630 drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024);
632 @@ -1269,7 +1275,7 @@ static int vc4_hvs_bind(struct device *d
633 hvs->regset.regs = hvs_regs;
634 hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
637 + if (vc4->gen == VC4_GEN_5) {
638 struct rpi_firmware *firmware;
639 struct device_node *node;
640 unsigned int max_rate;
641 @@ -1307,7 +1313,7 @@ static int vc4_hvs_bind(struct device *d
646 + if (vc4->gen == VC4_GEN_4)
647 hvs->dlist = hvs->regs + SCALER_DLIST_START;
649 hvs->dlist = hvs->regs + SCALER5_DLIST_START;
650 @@ -1348,7 +1354,7 @@ static int vc4_hvs_bind(struct device *d
651 SCALER_DISPCTRL_DISPEIRQ(1) |
652 SCALER_DISPCTRL_DISPEIRQ(2);
655 + if (vc4->gen == VC4_GEN_4)
656 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |
657 SCALER_DISPCTRL_SLVWREIRQ |
658 SCALER_DISPCTRL_SLVRDEIRQ |
659 @@ -1403,7 +1409,7 @@ static int vc4_hvs_bind(struct device *d
661 /* Recompute Composite Output Buffer (COB) allocations for the displays
663 - if (!vc4->is_vc5) {
664 + if (vc4->gen == VC4_GEN_4) {
665 /* The COB is 20736 pixels, or just over 10 lines at 2048 wide.
666 * The bottom 2048 pixels are full 32bpp RGBA (intended for the
667 * TXP composing RGBA to memory), whilst the remainder are only
668 --- a/drivers/gpu/drm/vc4/vc4_irq.c
669 +++ b/drivers/gpu/drm/vc4/vc4_irq.c
670 @@ -265,7 +265,7 @@ vc4_irq_enable(struct drm_device *dev)
672 struct vc4_dev *vc4 = to_vc4_dev(dev);
674 - if (WARN_ON_ONCE(vc4->is_vc5))
675 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
679 @@ -282,7 +282,7 @@ vc4_irq_disable(struct drm_device *dev)
681 struct vc4_dev *vc4 = to_vc4_dev(dev);
683 - if (WARN_ON_ONCE(vc4->is_vc5))
684 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
688 @@ -305,7 +305,7 @@ int vc4_irq_install(struct drm_device *d
689 struct vc4_dev *vc4 = to_vc4_dev(dev);
692 - if (WARN_ON_ONCE(vc4->is_vc5))
693 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
696 if (irq == IRQ_NOTCONNECTED)
697 @@ -326,7 +326,7 @@ void vc4_irq_uninstall(struct drm_device
699 struct vc4_dev *vc4 = to_vc4_dev(dev);
701 - if (WARN_ON_ONCE(vc4->is_vc5))
702 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
705 vc4_irq_disable(dev);
706 @@ -339,7 +339,7 @@ void vc4_irq_reset(struct drm_device *de
707 struct vc4_dev *vc4 = to_vc4_dev(dev);
708 unsigned long irqflags;
710 - if (WARN_ON_ONCE(vc4->is_vc5))
711 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
714 /* Acknowledge any stale IRQs. */
715 --- a/drivers/gpu/drm/vc4/vc4_kms.c
716 +++ b/drivers/gpu/drm/vc4/vc4_kms.c
717 @@ -378,7 +378,7 @@ static void vc4_atomic_commit_tail(struc
718 old_hvs_state->fifo_state[channel].pending_commit = NULL;
721 - if (vc4->is_vc5 && !vc4->firmware_kms) {
722 + if (vc4->gen == VC4_GEN_5 && !vc4->firmware_kms) {
723 unsigned long state_rate = max(old_hvs_state->core_clock_rate,
724 new_hvs_state->core_clock_rate);
725 unsigned long core_rate = clamp_t(unsigned long, state_rate,
726 @@ -398,7 +398,7 @@ static void vc4_atomic_commit_tail(struc
727 vc4_ctm_commit(vc4, state);
729 if (!vc4->firmware_kms) {
731 + if (vc4->gen == VC4_GEN_5)
732 vc5_hvs_pv_muxing_commit(vc4, state);
734 vc4_hvs_pv_muxing_commit(vc4, state);
735 @@ -417,7 +417,7 @@ static void vc4_atomic_commit_tail(struc
737 drm_atomic_helper_cleanup_planes(dev, state);
739 - if (vc4->is_vc5 && !vc4->firmware_kms) {
740 + if (vc4->gen == VC4_GEN_5 && !vc4->firmware_kms) {
741 unsigned long core_rate = min_t(unsigned long,
743 new_hvs_state->core_clock_rate);
744 @@ -482,7 +482,7 @@ static struct drm_framebuffer *vc4_fb_cr
745 struct vc4_dev *vc4 = to_vc4_dev(dev);
746 struct drm_mode_fb_cmd2 mode_cmd_local;
748 - if (WARN_ON_ONCE(vc4->is_vc5))
749 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
750 return ERR_PTR(-ENODEV);
752 /* If the user didn't specify a modifier, use the
753 @@ -1065,7 +1065,7 @@ int vc4_kms_load(struct drm_device *dev)
754 * the BCM2711, but the load tracker computations are used for
755 * the core clock rate calculation.
757 - if (!vc4->is_vc5) {
758 + if (vc4->gen == VC4_GEN_4) {
759 /* Start with the load tracker enabled. Can be
760 * disabled through the debugfs load_tracker file.
762 @@ -1081,7 +1081,7 @@ int vc4_kms_load(struct drm_device *dev)
767 + if (vc4->gen == VC4_GEN_5) {
768 dev->mode_config.max_width = 7680;
769 dev->mode_config.max_height = 7680;
771 @@ -1089,7 +1089,7 @@ int vc4_kms_load(struct drm_device *dev)
772 dev->mode_config.max_height = 2048;
775 - dev->mode_config.funcs = vc4->is_vc5 ? &vc5_mode_funcs : &vc4_mode_funcs;
776 + dev->mode_config.funcs = (vc4->gen > VC4_GEN_4) ? &vc5_mode_funcs : &vc4_mode_funcs;
777 dev->mode_config.helper_private = &vc4_mode_config_helpers;
778 dev->mode_config.preferred_depth = 24;
779 dev->mode_config.async_page_flip = true;
780 --- a/drivers/gpu/drm/vc4/vc4_perfmon.c
781 +++ b/drivers/gpu/drm/vc4/vc4_perfmon.c
782 @@ -23,7 +23,7 @@ void vc4_perfmon_get(struct vc4_perfmon
786 - if (WARN_ON_ONCE(vc4->is_vc5))
787 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
790 refcount_inc(&perfmon->refcnt);
791 @@ -37,7 +37,7 @@ void vc4_perfmon_put(struct vc4_perfmon
795 - if (WARN_ON_ONCE(vc4->is_vc5))
796 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
799 if (refcount_dec_and_test(&perfmon->refcnt))
800 @@ -49,7 +49,7 @@ void vc4_perfmon_start(struct vc4_dev *v
804 - if (WARN_ON_ONCE(vc4->is_vc5))
805 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
808 if (WARN_ON_ONCE(!perfmon || vc4->active_perfmon))
809 @@ -69,7 +69,7 @@ void vc4_perfmon_stop(struct vc4_dev *vc
813 - if (WARN_ON_ONCE(vc4->is_vc5))
814 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
817 if (WARN_ON_ONCE(!vc4->active_perfmon ||
818 @@ -90,7 +90,7 @@ struct vc4_perfmon *vc4_perfmon_find(str
819 struct vc4_dev *vc4 = vc4file->dev;
820 struct vc4_perfmon *perfmon;
822 - if (WARN_ON_ONCE(vc4->is_vc5))
823 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
826 mutex_lock(&vc4file->perfmon.lock);
827 @@ -105,7 +105,7 @@ void vc4_perfmon_open_file(struct vc4_fi
829 struct vc4_dev *vc4 = vc4file->dev;
831 - if (WARN_ON_ONCE(vc4->is_vc5))
832 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
835 mutex_init(&vc4file->perfmon.lock);
836 @@ -126,7 +126,7 @@ void vc4_perfmon_close_file(struct vc4_f
838 struct vc4_dev *vc4 = vc4file->dev;
840 - if (WARN_ON_ONCE(vc4->is_vc5))
841 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
844 mutex_lock(&vc4file->perfmon.lock);
845 @@ -146,7 +146,7 @@ int vc4_perfmon_create_ioctl(struct drm_
849 - if (WARN_ON_ONCE(vc4->is_vc5))
850 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
854 @@ -200,7 +200,7 @@ int vc4_perfmon_destroy_ioctl(struct drm
855 struct drm_vc4_perfmon_destroy *req = data;
856 struct vc4_perfmon *perfmon;
858 - if (WARN_ON_ONCE(vc4->is_vc5))
859 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
863 @@ -228,7 +228,7 @@ int vc4_perfmon_get_values_ioctl(struct
864 struct vc4_perfmon *perfmon;
867 - if (WARN_ON_ONCE(vc4->is_vc5))
868 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
872 --- a/drivers/gpu/drm/vc4/vc4_plane.c
873 +++ b/drivers/gpu/drm/vc4/vc4_plane.c
874 @@ -633,10 +633,10 @@ static u32 vc4_lbm_size(struct drm_plane
877 /* Align it to 64 or 128 (hvs5) bytes */
878 - lbm = roundup(lbm, vc4->is_vc5 ? 128 : 64);
879 + lbm = roundup(lbm, vc4->gen == VC4_GEN_5 ? 128 : 64);
881 /* Each "word" of the LBM memory contains 2 or 4 (hvs5) pixels */
882 - lbm /= vc4->is_vc5 ? 4 : 2;
883 + lbm /= vc4->gen == VC4_GEN_5 ? 4 : 2;
887 @@ -760,7 +760,7 @@ static int vc4_plane_allocate_lbm(struct
888 ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
891 - vc4->is_vc5 ? 64 : 32,
892 + vc4->gen == VC4_GEN_5 ? 64 : 32,
894 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
896 @@ -1141,7 +1141,7 @@ static int vc4_plane_mode_set(struct drm
897 mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
898 fb->format->has_alpha;
900 - if (!vc4->is_vc5) {
901 + if (vc4->gen == VC4_GEN_4) {
903 vc4_dlist_write(vc4_state,
905 @@ -1714,7 +1714,7 @@ struct drm_plane *vc4_plane_init(struct
908 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
909 - if (!hvs_formats[i].hvs5_only || vc4->is_vc5) {
910 + if (!hvs_formats[i].hvs5_only || vc4->gen == VC4_GEN_5) {
911 formats[num_formats] = hvs_formats[i].drm;
914 @@ -1729,7 +1729,7 @@ struct drm_plane *vc4_plane_init(struct
915 return ERR_CAST(vc4_plane);
916 plane = &vc4_plane->base;
919 + if (vc4->gen == VC4_GEN_5)
920 drm_plane_helper_add(plane, &vc5_plane_helper_funcs);
922 drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
923 --- a/drivers/gpu/drm/vc4/vc4_render_cl.c
924 +++ b/drivers/gpu/drm/vc4/vc4_render_cl.c
925 @@ -599,7 +599,7 @@ int vc4_get_rcl(struct drm_device *dev,
926 bool has_bin = args->bin_cl_size != 0;
929 - if (WARN_ON_ONCE(vc4->is_vc5))
930 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
933 if (args->min_x_tile > args->max_x_tile ||
934 --- a/drivers/gpu/drm/vc4/vc4_v3d.c
935 +++ b/drivers/gpu/drm/vc4/vc4_v3d.c
936 @@ -127,7 +127,7 @@ static int vc4_v3d_debugfs_ident(struct
938 vc4_v3d_pm_get(struct vc4_dev *vc4)
940 - if (WARN_ON_ONCE(vc4->is_vc5))
941 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
944 mutex_lock(&vc4->power_lock);
945 @@ -148,7 +148,7 @@ vc4_v3d_pm_get(struct vc4_dev *vc4)
947 vc4_v3d_pm_put(struct vc4_dev *vc4)
949 - if (WARN_ON_ONCE(vc4->is_vc5))
950 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
953 mutex_lock(&vc4->power_lock);
954 @@ -178,7 +178,7 @@ int vc4_v3d_get_bin_slot(struct vc4_dev
956 struct vc4_exec_info *exec;
958 - if (WARN_ON_ONCE(vc4->is_vc5))
959 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
963 @@ -325,7 +325,7 @@ int vc4_v3d_bin_bo_get(struct vc4_dev *v
967 - if (WARN_ON_ONCE(vc4->is_vc5))
968 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
971 mutex_lock(&vc4->bin_bo_lock);
972 @@ -360,7 +360,7 @@ static void bin_bo_release(struct kref *
974 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4)
976 - if (WARN_ON_ONCE(vc4->is_vc5))
977 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
980 mutex_lock(&vc4->bin_bo_lock);
981 --- a/drivers/gpu/drm/vc4/vc4_validate.c
982 +++ b/drivers/gpu/drm/vc4/vc4_validate.c
983 @@ -109,7 +109,7 @@ vc4_use_bo(struct vc4_exec_info *exec, u
984 struct drm_gem_dma_object *obj;
987 - if (WARN_ON_ONCE(vc4->is_vc5))
988 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
991 if (hindex >= exec->bo_count) {
992 @@ -169,7 +169,7 @@ vc4_check_tex_size(struct vc4_exec_info
993 uint32_t utile_w = utile_width(cpp);
994 uint32_t utile_h = utile_height(cpp);
996 - if (WARN_ON_ONCE(vc4->is_vc5))
997 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
1000 /* The shaded vertex format stores signed 12.4 fixed point
1001 @@ -495,7 +495,7 @@ vc4_validate_bin_cl(struct drm_device *d
1002 uint32_t dst_offset = 0;
1003 uint32_t src_offset = 0;
1005 - if (WARN_ON_ONCE(vc4->is_vc5))
1006 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
1009 while (src_offset < len) {
1010 @@ -942,7 +942,7 @@ vc4_validate_shader_recs(struct drm_devi
1014 - if (WARN_ON_ONCE(vc4->is_vc5))
1015 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
1018 for (i = 0; i < exec->shader_state_count; i++) {
1019 --- a/drivers/gpu/drm/vc4/vc4_validate_shaders.c
1020 +++ b/drivers/gpu/drm/vc4/vc4_validate_shaders.c
1021 @@ -786,7 +786,7 @@ vc4_validate_shader(struct drm_gem_dma_o
1022 struct vc4_validated_shader_info *validated_shader = NULL;
1023 struct vc4_shader_validation_state validation_state;
1025 - if (WARN_ON_ONCE(vc4->is_vc5))
1026 + if (WARN_ON_ONCE(vc4->gen == VC4_GEN_5))
1029 memset(&validation_state, 0, sizeof(validation_state));