target/linux/bcm53xx/patches-3.10/001-clocksource-arm_global_timer-Add-ARM-global-timer-su.patch

   1 From 5afd20a1eeef4db1d694d58931519f65e2003503 Mon Sep 17 00:00:00 2001
   2 From: Stuart Menefy <stuart.menefy@st.com>
   3 Date: Wed, 26 Jun 2013 12:48:38 +0100
   4 Subject: [PATCH 01/18] clocksource: arm_global_timer: Add ARM global timer
   5  support
   6
   7 This is a simple driver for the global timer module found in the Cortex
   8 A9-MP cores from revision r1p0 onwards. This should be able to perform
   9 the functions of the system timer and the local timer in an SMP system.
  10
  11 The global timer has the following features:
  12     The global timer is a 64-bit incrementing counter with an
  13 auto-incrementing feature. It continues incrementing after sending
  14 interrupts. The global timer is memory mapped in the private memory
  15 region.
  16     The global timer is accessible to all Cortex-A9 processors in the
  17 cluster. Each Cortex-A9 processor has a private 64-bit comparator that
  18 is used to assert a private interrupt when the global timer has reached
  19 the comparator value. All the Cortex-A9 processors in a design use the
  20 banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
  21 Controller as a Private Peripheral Interrupt. The global timer is
  22 clocked by PERIPHCLK.
  23
  24 Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
  25 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
  26 CC: Arnd Bergmann <arnd@arndb.de>
  27 CC: Rob Herring <robherring2@gmail.com>
  28 CC: Linus Walleij <linus.walleij@linaro.org>
  29 CC: Will Deacon <will.deacon@arm.com>
  30 CC: Thomas Gleixner <tglx@linutronix.de>
  31 Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
  32 ---
  33  .../devicetree/bindings/arm/global_timer.txt       |   24 ++
  34  drivers/clocksource/Kconfig                        |   13 +
  35  drivers/clocksource/Makefile                       |    1 +
  36  drivers/clocksource/arm_global_timer.c             |  321 ++++++++++++++++++++
  37  4 files changed, 359 insertions(+)
  38  create mode 100644 Documentation/devicetree/bindings/arm/global_timer.txt
  39  create mode 100644 drivers/clocksource/arm_global_timer.c
  40
  41 --- /dev/null
  42 +++ b/Documentation/devicetree/bindings/arm/global_timer.txt
  43 @@ -0,0 +1,24 @@
  44 +
  45 +* ARM Global Timer
  46 +       Cortex-A9 are often associated with a per-core Global timer.
  47 +
  48 +** Timer node required properties:
  49 +
  50 +- compatible : Should be "arm,cortex-a9-global-timer"
  51 +               Driver supports versions r2p0 and above.
  52 +
  53 +- interrupts : One interrupt to each core
  54 +
  55 +- reg : Specify the base address and the size of the GT timer
  56 +       register window.
  57 +
  58 +- clocks : Should be phandle to a clock.
  59 +
  60 +Example:
  61 +
  62 +       timer@2c000600 {
  63 +               compatible = "arm,cortex-a9-global-timer";
  64 +               reg = <0x2c000600 0x20>;
  65 +               interrupts = <1 13 0xf01>;
  66 +               clocks = <&arm_periph_clk>;
  67 +       };
  68 --- a/drivers/clocksource/Kconfig
  69 +++ b/drivers/clocksource/Kconfig
  70 @@ -67,6 +67,19 @@ config ARM_ARCH_TIMER
  71         bool
  72         select CLKSRC_OF if OF
  73
  74 +config ARM_GLOBAL_TIMER
  75 +       bool
  76 +       select CLKSRC_OF if OF
  77 +       help
  78 +         This options enables support for the ARM global timer unit
  79 +
  80 +config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
  81 +       bool
  82 +       depends on ARM_GLOBAL_TIMER
  83 +       default y
  84 +       help
  85 +        Use ARM global timer clock source as sched_clock
  86 +
  87  config CLKSRC_METAG_GENERIC
  88         def_bool y if METAG
  89         help
  90 --- a/drivers/clocksource/Makefile
  91 +++ b/drivers/clocksource/Makefile
  92 @@ -28,4 +28,5 @@ obj-$(CONFIG_CLKSRC_EXYNOS_MCT)       += exyno
  93  obj-$(CONFIG_CLKSRC_SAMSUNG_PWM)       += samsung_pwm_timer.o
  94
  95  obj-$(CONFIG_ARM_ARCH_TIMER)           += arm_arch_timer.o
  96 +obj-$(CONFIG_ARM_GLOBAL_TIMER)         += arm_global_timer.o
  97  obj-$(CONFIG_CLKSRC_METAG_GENERIC)     += metag_generic.o
  98 --- /dev/null
  99 +++ b/drivers/clocksource/arm_global_timer.c
 100 @@ -0,0 +1,321 @@
 101 +/*
 102 + * drivers/clocksource/arm_global_timer.c
 103 + *
 104 + * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
 105 + * Author: Stuart Menefy <stuart.menefy@st.com>
 106 + * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
 107 + *
 108 + * This program is free software; you can redistribute it and/or modify
 109 + * it under the terms of the GNU General Public License version 2 as
 110 + * published by the Free Software Foundation.
 111 + */
 112 +
 113 +#include <linux/init.h>
 114 +#include <linux/interrupt.h>
 115 +#include <linux/clocksource.h>
 116 +#include <linux/clockchips.h>
 117 +#include <linux/cpu.h>
 118 +#include <linux/clk.h>
 119 +#include <linux/err.h>
 120 +#include <linux/io.h>
 121 +#include <linux/of.h>
 122 +#include <linux/of_irq.h>
 123 +#include <linux/of_address.h>
 124 +#include <asm/sched_clock.h>
 125 +
 126 +#include <asm/cputype.h>
 127 +
 128 +#define GT_COUNTER0    0x00
 129 +#define GT_COUNTER1    0x04
 130 +
 131 +#define GT_CONTROL     0x08
 132 +#define GT_CONTROL_TIMER_ENABLE                BIT(0)  /* this bit is NOT banked */
 133 +#define GT_CONTROL_COMP_ENABLE         BIT(1)  /* banked */
 134 +#define GT_CONTROL_IRQ_ENABLE          BIT(2)  /* banked */
 135 +#define GT_CONTROL_AUTO_INC            BIT(3)  /* banked */
 136 +
 137 +#define GT_INT_STATUS  0x0c
 138 +#define GT_INT_STATUS_EVENT_FLAG       BIT(0)
 139 +
 140 +#define GT_COMP0       0x10
 141 +#define GT_COMP1       0x14
 142 +#define GT_AUTO_INC    0x18
 143 +
 144 +/*
 145 + * We are expecting to be clocked by the ARM peripheral clock.
 146 + *
 147 + * Note: it is assumed we are using a prescaler value of zero, so this is
 148 + * the units for all operations.
 149 + */
 150 +static void __iomem *gt_base;
 151 +static unsigned long gt_clk_rate;
 152 +static int gt_ppi;
 153 +static struct clock_event_device __percpu *gt_evt;
 154 +
 155 +/*
 156 + * To get the value from the Global Timer Counter register proceed as follows:
 157 + * 1. Read the upper 32-bit timer counter register
 158 + * 2. Read the lower 32-bit timer counter register
 159 + * 3. Read the upper 32-bit timer counter register again. If the value is
 160 + *  different to the 32-bit upper value read previously, go back to step 2.
 161 + *  Otherwise the 64-bit timer counter value is correct.
 162 + */
 163 +static u64 gt_counter_read(void)
 164 +{
 165 +       u64 counter;
 166 +       u32 lower;
 167 +       u32 upper, old_upper;
 168 +
 169 +       upper = readl_relaxed(gt_base + GT_COUNTER1);
 170 +       do {
 171 +               old_upper = upper;
 172 +               lower = readl_relaxed(gt_base + GT_COUNTER0);
 173 +               upper = readl_relaxed(gt_base + GT_COUNTER1);
 174 +       } while (upper != old_upper);
 175 +
 176 +       counter = upper;
 177 +       counter <<= 32;
 178 +       counter |= lower;
 179 +       return counter;
 180 +}
 181 +
 182 +/**
 183 + * To ensure that updates to comparator value register do not set the
 184 + * Interrupt Status Register proceed as follows:
 185 + * 1. Clear the Comp Enable bit in the Timer Control Register.
 186 + * 2. Write the lower 32-bit Comparator Value Register.
 187 + * 3. Write the upper 32-bit Comparator Value Register.
 188 + * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
 189 + */
 190 +static void gt_compare_set(unsigned long delta, int periodic)
 191 +{
 192 +       u64 counter = gt_counter_read();
 193 +       unsigned long ctrl;
 194 +
 195 +       counter += delta;
 196 +       ctrl = GT_CONTROL_TIMER_ENABLE;
 197 +       writel(ctrl, gt_base + GT_CONTROL);
 198 +       writel(lower_32_bits(counter), gt_base + GT_COMP0);
 199 +       writel(upper_32_bits(counter), gt_base + GT_COMP1);
 200 +
 201 +       if (periodic) {
 202 +               writel(delta, gt_base + GT_AUTO_INC);
 203 +               ctrl |= GT_CONTROL_AUTO_INC;
 204 +       }
 205 +
 206 +       ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
 207 +       writel(ctrl, gt_base + GT_CONTROL);
 208 +}
 209 +
 210 +static void gt_clockevent_set_mode(enum clock_event_mode mode,
 211 +                                  struct clock_event_device *clk)
 212 +{
 213 +       unsigned long ctrl;
 214 +
 215 +       switch (mode) {
 216 +       case CLOCK_EVT_MODE_PERIODIC:
 217 +               gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
 218 +               break;
 219 +       case CLOCK_EVT_MODE_ONESHOT:
 220 +       case CLOCK_EVT_MODE_UNUSED:
 221 +       case CLOCK_EVT_MODE_SHUTDOWN:
 222 +               ctrl = readl(gt_base + GT_CONTROL);
 223 +               ctrl &= ~(GT_CONTROL_COMP_ENABLE |
 224 +                               GT_CONTROL_IRQ_ENABLE | GT_CONTROL_AUTO_INC);
 225 +               writel(ctrl, gt_base + GT_CONTROL);
 226 +               break;
 227 +       default:
 228 +               break;
 229 +       }
 230 +}
 231 +
 232 +static int gt_clockevent_set_next_event(unsigned long evt,
 233 +                                       struct clock_event_device *unused)
 234 +{
 235 +       gt_compare_set(evt, 0);
 236 +       return 0;
 237 +}
 238 +
 239 +static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
 240 +{
 241 +       struct clock_event_device *evt = dev_id;
 242 +
 243 +       if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
 244 +                               GT_INT_STATUS_EVENT_FLAG))
 245 +               return IRQ_NONE;
 246 +
 247 +       /**
 248 +        * ERRATA 740657( Global Timer can send 2 interrupts for
 249 +        * the same event in single-shot mode)
 250 +        * Workaround:
 251 +        *      Either disable single-shot mode.
 252 +        *      Or
 253 +        *      Modify the Interrupt Handler to avoid the
 254 +        *      offending sequence. This is achieved by clearing
 255 +        *      the Global Timer flag _after_ having incremented
 256 +        *      the Comparator register value to a higher value.
 257 +        */
 258 +       if (evt->mode == CLOCK_EVT_MODE_ONESHOT)
 259 +               gt_compare_set(ULONG_MAX, 0);
 260 +
 261 +       writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
 262 +       evt->event_handler(evt);
 263 +
 264 +       return IRQ_HANDLED;
 265 +}
 266 +
 267 +static int __cpuinit gt_clockevents_init(struct clock_event_device *clk)
 268 +{
 269 +       int cpu = smp_processor_id();
 270 +
 271 +       clk->name = "arm_global_timer";
 272 +       clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
 273 +       clk->set_mode = gt_clockevent_set_mode;
 274 +       clk->set_next_event = gt_clockevent_set_next_event;
 275 +       clk->cpumask = cpumask_of(cpu);
 276 +       clk->rating = 300;
 277 +       clk->irq = gt_ppi;
 278 +       clockevents_config_and_register(clk, gt_clk_rate,
 279 +                                       1, 0xffffffff);
 280 +       enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
 281 +       return 0;
 282 +}
 283 +
 284 +static void gt_clockevents_stop(struct clock_event_device *clk)
 285 +{
 286 +       gt_clockevent_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
 287 +       disable_percpu_irq(clk->irq);
 288 +}
 289 +
 290 +static cycle_t gt_clocksource_read(struct clocksource *cs)
 291 +{
 292 +       return gt_counter_read();
 293 +}
 294 +
 295 +static struct clocksource gt_clocksource = {
 296 +       .name   = "arm_global_timer",
 297 +       .rating = 300,
 298 +       .read   = gt_clocksource_read,
 299 +       .mask   = CLOCKSOURCE_MASK(64),
 300 +       .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 301 +};
 302 +
 303 +#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
 304 +static u32 notrace gt_sched_clock_read(void)
 305 +{
 306 +       return gt_counter_read();
 307 +}
 308 +#endif
 309 +
 310 +static void __init gt_clocksource_init(void)
 311 +{
 312 +       writel(0, gt_base + GT_CONTROL);
 313 +       writel(0, gt_base + GT_COUNTER0);
 314 +       writel(0, gt_base + GT_COUNTER1);
 315 +       /* enables timer on all the cores */
 316 +       writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
 317 +
 318 +#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
 319 +       setup_sched_clock(gt_sched_clock_read, 32, gt_clk_rate);
 320 +#endif
 321 +       clocksource_register_hz(&gt_clocksource, gt_clk_rate);
 322 +}
 323 +
 324 +static int __cpuinit gt_cpu_notify(struct notifier_block *self,
 325 +                                          unsigned long action, void *hcpu)
 326 +{
 327 +       switch (action & ~CPU_TASKS_FROZEN) {
 328 +       case CPU_STARTING:
 329 +               gt_clockevents_init(this_cpu_ptr(gt_evt));
 330 +               break;
 331 +       case CPU_DYING:
 332 +               gt_clockevents_stop(this_cpu_ptr(gt_evt));
 333 +               break;
 334 +       }
 335 +
 336 +       return NOTIFY_OK;
 337 +}
 338 +static struct notifier_block gt_cpu_nb __cpuinitdata = {
 339 +       .notifier_call = gt_cpu_notify,
 340 +};
 341 +
 342 +static void __init global_timer_of_register(struct device_node *np)
 343 +{
 344 +       struct clk *gt_clk;
 345 +       int err = 0;
 346 +
 347 +       /*
 348 +        * In r2p0 the comparators for each processor with the global timer
 349 +        * fire when the timer value is greater than or equal to. In previous
 350 +        * revisions the comparators fired when the timer value was equal to.
 351 +        */
 352 +       if ((read_cpuid_id() & 0xf0000f) < 0x200000) {
 353 +               pr_warn("global-timer: non support for this cpu version.\n");
 354 +               return;
 355 +       }
 356 +
 357 +       gt_ppi = irq_of_parse_and_map(np, 0);
 358 +       if (!gt_ppi) {
 359 +               pr_warn("global-timer: unable to parse irq\n");
 360 +               return;
 361 +       }
 362 +
 363 +       gt_base = of_iomap(np, 0);
 364 +       if (!gt_base) {
 365 +               pr_warn("global-timer: invalid base address\n");
 366 +               return;
 367 +       }
 368 +
 369 +       gt_clk = of_clk_get(np, 0);
 370 +       if (!IS_ERR(gt_clk)) {
 371 +               err = clk_prepare_enable(gt_clk);
 372 +               if (err)
 373 +                       goto out_unmap;
 374 +       } else {
 375 +               pr_warn("global-timer: clk not found\n");
 376 +               err = -EINVAL;
 377 +               goto out_unmap;
 378 +       }
 379 +
 380 +       gt_clk_rate = clk_get_rate(gt_clk);
 381 +       gt_evt = alloc_percpu(struct clock_event_device);
 382 +       if (!gt_evt) {
 383 +               pr_warn("global-timer: can't allocate memory\n");
 384 +               err = -ENOMEM;
 385 +               goto out_clk;
 386 +       }
 387 +
 388 +       err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
 389 +                                "gt", gt_evt);
 390 +       if (err) {
 391 +               pr_warn("global-timer: can't register interrupt %d (%d)\n",
 392 +                       gt_ppi, err);
 393 +               goto out_free;
 394 +       }
 395 +
 396 +       err = register_cpu_notifier(&gt_cpu_nb);
 397 +       if (err) {
 398 +               pr_warn("global-timer: unable to register cpu notifier.\n");
 399 +               goto out_irq;
 400 +       }
 401 +
 402 +       /* Immediately configure the timer on the boot CPU */
 403 +       gt_clocksource_init();
 404 +       gt_clockevents_init(this_cpu_ptr(gt_evt));
 405 +
 406 +       return;
 407 +
 408 +out_irq:
 409 +       free_percpu_irq(gt_ppi, gt_evt);
 410 +out_free:
 411 +       free_percpu(gt_evt);
 412 +out_clk:
 413 +       clk_disable_unprepare(gt_clk);
 414 +out_unmap:
 415 +       iounmap(gt_base);
 416 +       WARN(err, "ARM Global timer register failed (%d)\n", err);
 417 +}
 418 +
 419 +/* Only tested on r2p2 and r3p0  */
 420 +CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
 421 +                       global_timer_of_register);