1 From d27509f19b5f93ea3425cfef782bb3c6541cd44d Mon Sep 17 00:00:00 2001
2 From: Hauke Mehrtens <hauke@hauke-m.de>
3 Date: Tue, 4 Feb 2014 00:01:45 +0100
4 Subject: [PATCH] ARM: BCM5301X: add dts files for BCM4708 SoC
6 This uses the newly added BCM5301X SoC code.
8 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
9 Acked-by: Arnd Bergmann <arnd@arndb.de>
10 Acked-by: Christian Daudt <bcm@fixthebug.org>
11 Signed-off-by: Matt Porter <mporter@linaro.org>
13 arch/arm/boot/dts/Makefile | 1 +
14 arch/arm/boot/dts/bcm4708-netgear-r6250.dts | 35 ++++++++++
15 arch/arm/boot/dts/bcm4708.dtsi | 34 ++++++++++
16 arch/arm/boot/dts/bcm5301x.dtsi | 95 +++++++++++++++++++++++++++
17 4 files changed, 165 insertions(+)
18 create mode 100644 arch/arm/boot/dts/bcm4708-netgear-r6250.dts
19 create mode 100644 arch/arm/boot/dts/bcm4708.dtsi
20 create mode 100644 arch/arm/boot/dts/bcm5301x.dtsi
22 --- a/arch/arm/boot/dts/Makefile
23 +++ b/arch/arm/boot/dts/Makefile
24 @@ -50,6 +50,7 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rp
25 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm11351-brt.dtb \
27 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
28 +dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
29 dtb-$(CONFIG_ARCH_BERLIN) += \
30 berlin2-sony-nsz-gs7.dtb \
31 berlin2cd-google-chromecast.dtb
33 +++ b/arch/arm/boot/dts/bcm4708-netgear-r6250.dts
36 + * Broadcom BCM470X / BCM5301X arm platform code.
37 + * DTS for Netgear R6250 V1
39 + * Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
41 + * Licensed under the GNU/GPL. See COPYING for details.
46 +#include "bcm4708.dtsi"
49 + compatible = "netgear,r6250v1", "brcm,bcm4708";
50 + model = "Netgear R6250 V1 (BCM4708)";
53 + bootargs = "console=ttyS0,115200";
57 + reg = <0x00000000 0x08000000>;
61 + uart0: serial@0300 {
65 + uart1: serial@0400 {
71 +++ b/arch/arm/boot/dts/bcm4708.dtsi
74 + * Broadcom BCM470X / BCM5301X ARM platform code.
75 + * DTS for BCM4708 SoC.
77 + * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
79 + * Licensed under the GNU/GPL. See COPYING for details.
82 +#include "bcm5301x.dtsi"
85 + compatible = "brcm,bcm4708";
88 + #address-cells = <1>;
92 + device_type = "cpu";
93 + compatible = "arm,cortex-a9";
94 + next-level-cache = <&L2>;
99 + device_type = "cpu";
100 + compatible = "arm,cortex-a9";
101 + next-level-cache = <&L2>;
108 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
111 + * Broadcom BCM470X / BCM5301X ARM platform code.
112 + * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
113 + * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
115 + * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
117 + * Licensed under the GNU/GPL. See COPYING for details.
120 +#include <dt-bindings/interrupt-controller/irq.h>
121 +#include <dt-bindings/interrupt-controller/arm-gic.h>
122 +#include "skeleton.dtsi"
125 + interrupt-parent = <&gic>;
128 + compatible = "simple-bus";
129 + ranges = <0x00000000 0x18000000 0x00001000>;
130 + #address-cells = <1>;
133 + uart0: serial@0300 {
134 + compatible = "ns16550";
135 + reg = <0x0300 0x100>;
136 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
137 + clock-frequency = <100000000>;
138 + status = "disabled";
141 + uart1: serial@0400 {
142 + compatible = "ns16550";
143 + reg = <0x0400 0x100>;
144 + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
145 + clock-frequency = <100000000>;
146 + status = "disabled";
151 + compatible = "simple-bus";
152 + ranges = <0x00000000 0x19020000 0x00003000>;
153 + #address-cells = <1>;
157 + compatible = "arm,cortex-a9-scu";
158 + reg = <0x0000 0x100>;
162 + compatible = "arm,cortex-a9-global-timer";
163 + reg = <0x0200 0x100>;
164 + interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
165 + clocks = <&clk_periph>;
169 + compatible = "arm,cortex-a9-twd-timer";
170 + reg = <0x0600 0x100>;
171 + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
172 + clocks = <&clk_periph>;
175 + gic: interrupt-controller@1000 {
176 + compatible = "arm,cortex-a9-gic";
177 + #interrupt-cells = <3>;
178 + #address-cells = <0>;
179 + interrupt-controller;
180 + reg = <0x1000 0x1000>,
184 + L2: cache-controller@2000 {
185 + compatible = "arm,pl310-cache";
186 + reg = <0x2000 0x1000>;
193 + #address-cells = <1>;
196 + /* As long as we do not have a real clock driver us this
198 + clk_periph: periph {
199 + compatible = "fixed-clock";
200 + #clock-cells = <0>;
201 + clock-frequency = <400000000>;