target/linux/bcm53xx/patches-3.14/300-ARM-BCM5301X-Disable-MMU-and-Dcache-for-decompression.patch

   1 From 26023cdfacaf116545b1087b9d1fe50dc6fbda10 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
   3 Date: Wed, 24 Sep 2014 22:14:07 +0200
   4 Subject: [PATCH] ARM: BCM5301X: Disable MMU and Dcache for decompression
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Without this fix kernel was randomly hanging in ~25% of tries during
  10 early init. Hangs used to happen at random places in the start_kernel.
  11
  12 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
  13 ---
  14  arch/arm/boot/compressed/Makefile                |   5 +
  15  arch/arm/boot/compressed/head-bcm_5301x-mpcore.S |  37 +++++++
  16  arch/arm/boot/compressed/mpcore_cache.S          | 118 +++++++++++++++++++++++
  17  3 files changed, 160 insertions(+)
  18  create mode 100644 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
  19  create mode 100644 arch/arm/boot/compressed/mpcore_cache.S
  20
  21 diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
  22 index 9312edc..ce7438c 100644
  23 --- a/arch/arm/boot/compressed/Makefile
  24 +++ b/arch/arm/boot/compressed/Makefile
  25 @@ -44,6 +44,11 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
  26  OBJS           += ll_char_wr.o font.o
  27  endif
  28
  29 +ifeq ($(CONFIG_ARCH_BCM_5301X),y)
  30 +OBJS           += head-bcm_5301x-mpcore.o
  31 +OBJS           += mpcore_cache.o
  32 +endif
  33 +
  34  ifeq ($(CONFIG_ARCH_SA1100),y)
  35  OBJS           += head-sa1100.o
  36  endif
  37 diff --git a/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
  38 new file mode 100644
  39 index 0000000..fd076a0
  40 --- /dev/null
  41 +++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
  42 @@ -0,0 +1,37 @@
  43 +/*
  44 + *
  45 + * Platform specific tweaks.  This is merged into head.S by the linker.
  46 + *
  47 + */
  48 +
  49 +#include <linux/linkage.h>
  50 +#include <asm/assembler.h>
  51 +#include <asm/cp15.h>
  52 +
  53 +               .section        ".start", "ax"
  54 +
  55 +/*
  56 + * This code section is spliced into the head code by the linker
  57 + */
  58 +
  59 +__plat_uncompress_start:
  60 +
  61 +       @ Preserve r8/r7 i.e. kernel entry values
  62 +       mov     r12, r8
  63 +
  64 +       @ Clear MMU enable and Dcache enable bits
  65 +       mrc     p15, 0, r0, c1, c0, 0           @ Read SCTLR
  66 +       bic     r0, #CR_C|CR_M
  67 +       mcr     p15, 0, r0, c1, c0, 0           @ Write SCTLR
  68 +       nop
  69 +
  70 +       @ Call the cache invalidation routine
  71 +       bl      v7_all_dcache_invalidate
  72 +       nop
  73 +       mov     r0,#0
  74 +       ldr     r3, =0x19022000                 @ L2 cache controller, control reg
  75 +       str     r0, [r3, #0x100]                @ Disable L2 cache
  76 +       nop
  77 +
  78 +       @ Restore
  79 +       mov     r8, r12
  80 diff --git a/arch/arm/boot/compressed/mpcore_cache.S b/arch/arm/boot/compressed/mpcore_cache.S
  81 new file mode 100644
  82 index 0000000..ada734c
  83 --- /dev/null
  84 +++ b/arch/arm/boot/compressed/mpcore_cache.S
  85 @@ -0,0 +1,118 @@
  86 +/*****************************************************************************
  87 +* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
  88 +*
  89 +* Unless you and Broadcom execute a separate written software license
  90 +* agreement governing use of this software, this software is licensed to you
  91 +* under the terms of the GNU General Public License version 2, available at
  92 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
  93 +*
  94 +* Notwithstanding the above, under no circumstances may you combine this
  95 +* software in any way with any other Broadcom software provided under a
  96 +* license other than the GPL, without Broadcom's express prior written
  97 +* consent.
  98 +*****************************************************************************/
  99 +
 100 +#include <linux/linkage.h>
 101 +#include <linux/init.h>
 102 +
 103 +       __INIT
 104 +
 105 +/*
 106 + * v7_l1_cache_invalidate
 107 + *
 108 + * Invalidate contents of L1 cache without flushing its contents
 109 + * into outer cache and memory. This is needed when the contents
 110 + * of the cache are unpredictable after power-up.
 111 + *
 112 + * corrupts r0-r6
 113 + */
 114 +
 115 +ENTRY(v7_l1_cache_invalidate)
 116 +       mov     r0, #0
 117 +       mcr     p15, 2, r0, c0, c0, 0   @ set cache level to 1
 118 +       mrc     p15, 1, r0, c0, c0, 0   @ read CLIDR
 119 +
 120 +       ldr     r1, =0x7fff
 121 +       and     r2, r1, r0, lsr #13     @ get max # of index size
 122 +
 123 +       ldr     r1, =0x3ff
 124 +       and     r3, r1, r0, lsr #3      @ NumWays - 1
 125 +       add     r2, r2, #1              @ NumSets
 126 +
 127 +       and     r0, r0, #0x7
 128 +       add     r0, r0, #4              @ SetShift
 129 +
 130 +       clz     r1, r3                  @ WayShift
 131 +       add     r4, r3, #1              @ NumWays
 132 +1:     sub     r2, r2, #1              @ NumSets--
 133 +       mov     r3, r4                  @ Temp = NumWays
 134 +2:     subs    r3, r3, #1              @ Temp--
 135 +       mov     r5, r3, lsl r1
 136 +       mov     r6, r2, lsl r0
 137 +       orr     r5, r5, r6              @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
 138 +       mcr     p15, 0, r5, c7, c6, 2   @ Invalidate line
 139 +       bgt     2b
 140 +       cmp     r2, #0
 141 +       bgt     1b
 142 +       dsb
 143 +       mov     r0,#0
 144 +       mcr     p15,0,r0,c7,c5,0        /* Invalidate icache */
 145 +       isb
 146 +       mov     pc, lr
 147 +ENDPROC(v7_l1_cache_invalidate)
 148 +
 149 +/*
 150 + * v7_all_dcache_invalidate
 151 + *
 152 + * Invalidate without flushing the contents of all cache levels
 153 + * accesible by the current processor core.
 154 + * This is useful when the contents of cache memory are undetermined
 155 + * at power-up.
 156 + *     Corrupted registers: r0-r7, r9-r11
 157 + *
 158 + * Based on cache-v7.S: v7_flush_dcache_all()
 159 + */
 160 +
 161 +ENTRY(v7_all_dcache_invalidate)
 162 +       mrc     p15, 1, r0, c0, c0, 1   @ read clidr
 163 +       ands    r3, r0, #0x7000000      @ extract loc from clidr
 164 +       mov     r3, r3, lsr #23         @ left align loc bit field
 165 +       beq     finished                @ if loc is 0, then no need to clean
 166 +       mov     r10, #0                 @ start clean at cache level 0
 167 +loop1:
 168 +       add     r2, r10, r10, lsr #1    @ work out 3x current cache level
 169 +       mov     r1, r0, lsr r2          @ extract cache type bits from clidr
 170 +       and     r1, r1, #7              @ mask of bits for current cache only
 171 +       cmp     r1, #2                  @ see what cache we have at this level
 172 +       blt     skip                    @ skip if no cache, or just i-cache
 173 +       mcr     p15, 2, r10, c0, c0, 0  @ select current cache level in cssr
 174 +       isb                             @ isb to sych the new cssr&csidr
 175 +       mrc     p15, 1, r1, c0, c0, 0   @ read the new csidr
 176 +       and     r2, r1, #7              @ extract the length of the cache lines
 177 +       add     r2, r2, #4              @ add 4 (line length offset)
 178 +       ldr     r4, =0x3ff
 179 +       ands    r4, r4, r1, lsr #3      @ find maximum number on the way size
 180 +       clz     r5, r4                  @ find bit pos of way size increment
 181 +       ldr     r7, =0x7fff
 182 +       ands    r7, r7, r1, lsr #13     @ extract max number of the index size
 183 +loop2:
 184 +       mov     r9, r4                  @ create working copy of max way size
 185 +loop3:
 186 +       orr     r11, r10, r9, lsl r5    @ factor way and cache number into r11
 187 +       orr     r11, r11, r7, lsl r2    @ factor index number into r11
 188 +       mcr     p15, 0, r11, c7, c6, 2  @ Invalidate line
 189 +       subs    r9, r9, #1              @ decrement the way
 190 +       bge     loop3
 191 +       subs    r7, r7, #1              @ decrement the index
 192 +       bge     loop2
 193 +skip:
 194 +       add     r10, r10, #2            @ increment cache number
 195 +       cmp     r3, r10
 196 +       bgt     loop1
 197 +finished:
 198 +       mov     r10, #0                 @ swith back to cache level 0
 199 +       mcr     p15, 2, r10, c0, c0, 0  @ select current cache level in cssr
 200 +       dsb
 201 +       isb
 202 +       mov     pc, lr
 203 +ENDPROC(v7_all_dcache_invalidate)
 204 --
 205 1.8.4.5
 206