1 --- a/drivers/mtd/spi-nor/spi-nor.c
2 +++ b/drivers/mtd/spi-nor/spi-nor.c
3 @@ -538,6 +538,7 @@ static const struct spi_device_id spi_no
5 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
6 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
7 + { "gd25q128", INFO(0xc84018, 0, 64 * 1024, 256, SECT_4K) },
9 /* Intel/Numonyx -- xxxs33b */
10 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
11 @@ -564,14 +565,14 @@ static const struct spi_device_id spi_no
12 { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
15 - { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
16 - { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
17 - { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
18 - { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
19 - { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
20 - { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
21 - { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },
22 - { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },
23 + { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, SPI_NOR_QUAD_READ) },
24 + { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, SPI_NOR_QUAD_READ) },
25 + { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
26 + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SPI_NOR_QUAD_READ) },
27 + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
28 + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
29 + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
30 + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
33 { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
34 @@ -896,6 +897,45 @@ static int spansion_quad_enable(struct s
38 +static int micron_quad_enable(struct spi_nor *nor)
43 + ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
45 + dev_err(nor->dev, "error %d reading EVCR\n", ret);
51 + /* set EVCR, enable quad I/O */
52 + nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
53 + ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
55 + dev_err(nor->dev, "error while writing EVCR register\n");
59 + ret = spi_nor_wait_till_ready(nor);
63 + /* read EVCR and check it */
64 + ret = nor->read_reg(nor, SPINOR_OP_RD_EVCR, &val, 1);
66 + dev_err(nor->dev, "error %d reading EVCR\n", ret);
69 + if (val & EVCR_QUAD_EN_MICRON) {
70 + dev_err(nor->dev, "Micron EVCR Quad bit not clear\n");
77 static int set_quad_mode(struct spi_nor *nor, struct flash_info *info)
80 @@ -908,6 +948,13 @@ static int set_quad_mode(struct spi_nor
85 + status = micron_quad_enable(nor);
87 + dev_err(nor->dev, "Micron quad-read not enabled\n");
92 status = spansion_quad_enable(nor);
94 --- a/include/linux/mtd/spi-nor.h
95 +++ b/include/linux/mtd/spi-nor.h
97 /* Used for Spansion flashes only. */
98 #define SPINOR_OP_BRWR 0x17 /* Bank register write */
100 +/* Used for Micron flashes only. */
101 +#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
102 +#define SPINOR_OP_WD_EVCR 0x61 /* Write EVCR register */
104 /* Status Register bits. */
105 #define SR_WIP 1 /* Write in progress */
106 #define SR_WEL 2 /* Write enable latch */
109 #define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
111 +/* Enhanced Volatile Configuration Register bits */
112 +#define EVCR_QUAD_EN_MICRON 0x80 /* Micron Quad I/O */
114 /* Flag Status Register bits */
115 #define FSR_READY 0x80