1 From: Florian Fainelli <f.fainelli@gmail.com>
2 Subject: [PATCH] ARM: BCM5301x: Disable MMU and Dcache during decompression
3 Date: Tue, 14 Jul 2015 16:12:08 -0700
5 Use the existing __armv7_mmu_cache_flush() to perform the cache flush
6 since this does what we are after.
8 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
10 arch/arm/boot/compressed/Makefile | 4 +++
11 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S | 37 ++++++++++++++++++++++++
12 arch/arm/boot/compressed/head.S | 2 ++
13 3 files changed, 43 insertions(+)
14 create mode 100644 arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
16 --- a/arch/arm/boot/compressed/Makefile
17 +++ b/arch/arm/boot/compressed/Makefile
18 @@ -31,6 +31,10 @@ ifeq ($(CONFIG_ARCH_ACORN),y)
19 OBJS += ll_char_wr.o font.o
22 +ifeq ($(CONFIG_ARCH_BCM_5301X),y)
23 +OBJS += head-bcm_5301x-mpcore.o
26 ifeq ($(CONFIG_ARCH_SA1100),y)
30 +++ b/arch/arm/boot/compressed/head-bcm_5301x-mpcore.S
34 + * Platform specific tweaks. This is merged into head.S by the linker.
38 +#include <linux/linkage.h>
39 +#include <asm/assembler.h>
40 +#include <asm/cp15.h>
42 + .section ".start", "ax"
45 + * This code section is spliced into the head code by the linker
48 +__plat_uncompress_start:
50 + @ Preserve r8/r7 i.e. kernel entry values
53 + @ Clear MMU enable and Dcache enable bits
54 + mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR
56 + mcr p15, 0, r0, c1, c0, 0 @ Write SCTLR
59 + @ Call the cache invalidation routine
60 + bl __armv7_mmu_cache_flush_fn
63 + ldr r3, =0x19022000 @ L2 cache controller, control reg
64 + str r0, [r3, #0x100] @ Disable L2 cache
69 --- a/arch/arm/boot/compressed/head.S
70 +++ b/arch/arm/boot/compressed/head.S
71 @@ -1152,6 +1152,7 @@ __armv7_mmu_cache_flush:
73 mcr p15, 0, r10, c7, c10, 5 @ DMB
74 stmfd sp!, {r0-r7, r9-r11}
75 +ENTRY(__armv7_mmu_cache_flush_fn)
76 mrc p15, 1, r0, c0, c0, 1 @ read clidr
77 ands r3, r0, #0x7000000 @ extract loc from clidr
78 mov r3, r3, lsr #23 @ left align loc bit field
79 @@ -1201,6 +1202,7 @@ iflush:
80 mcr p15, 0, r10, c7, c10, 4 @ DSB
81 mcr p15, 0, r10, c7, c5, 4 @ ISB
83 +ENDPROC(__armv7_mmu_cache_flush_fn)
85 __armv5tej_mmu_cache_flush: