1 From fa236a7ef24048bafaeed13f68df35a819794758 Mon Sep 17 00:00:00 2001
2 From: Kamal Dasu <kdasu.kdev@gmail.com>
3 Date: Wed, 24 Aug 2016 18:04:23 -0400
4 Subject: [PATCH] spi: bcm-qspi: Add Broadcom MSPI driver
6 Master SPI driver for Broadcom settop, iProc SoCs. The driver
7 is used for devices that use SPI protocol on BRCMSTB, NSP, NS2
8 SoCs. SoC platform driver call exported porbe(), remove()
9 and suspend/resume pm_ops implemented in this common driver.
11 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
12 Signed-off-by: Yendapally Reddy Dhananjaya Reddy
13 Signed-off-by: Mark Brown <broonie@kernel.org>
15 drivers/spi/Kconfig | 10 +
16 drivers/spi/Makefile | 1 +
17 drivers/spi/spi-bcm-qspi.c | 712 +++++++++++++++++++++++++++++++++++++++++++++
18 drivers/spi/spi-bcm-qspi.h | 63 ++++
19 4 files changed, 786 insertions(+)
20 create mode 100644 drivers/spi/spi-bcm-qspi.c
21 create mode 100644 drivers/spi/spi-bcm-qspi.h
23 --- a/drivers/spi/Kconfig
24 +++ b/drivers/spi/Kconfig
25 @@ -147,6 +147,16 @@ config SPI_BCM63XX_HSSPI
26 This enables support for the High Speed SPI controller present on
27 newer Broadcom BCM63XX SoCs.
30 + tristate "Broadcom BSPI and MSPI controller support"
31 + depends on ARCH_BRCMSTB || ARCH_BCM || ARCH_BCM_IPROC || COMPILE_TEST
32 + default ARCH_BCM_IPROC
34 + Enables support for the Broadcom SPI flash and MSPI controller.
35 + Select this option for any one of BRCMSTB, iProc NSP and NS2 SoCs
36 + based platforms. This driver works for both SPI master for spi-nor
37 + flash device as well as MSPI device.
40 tristate "Utilities for Bitbanging SPI masters"
42 --- a/drivers/spi/Makefile
43 +++ b/drivers/spi/Makefile
44 @@ -19,6 +19,7 @@ obj-$(CONFIG_SPI_BCM2835AUX) += spi-bcm
45 obj-$(CONFIG_SPI_BCM53XX) += spi-bcm53xx.o
46 obj-$(CONFIG_SPI_BCM63XX) += spi-bcm63xx.o
47 obj-$(CONFIG_SPI_BCM63XX_HSSPI) += spi-bcm63xx-hsspi.o
48 +obj-$(CONFIG_SPI_BCM_QSPI) += spi-bcm-qspi.o
49 obj-$(CONFIG_SPI_BFIN5XX) += spi-bfin5xx.o
50 obj-$(CONFIG_SPI_ADI_V3) += spi-adi-v3.o
51 obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o
53 +++ b/drivers/spi/spi-bcm-qspi.c
56 + * Driver for Broadcom BRCMSTB, NSP, NS2, Cygnus SPI Controllers
58 + * Copyright 2016 Broadcom
60 + * This program is free software; you can redistribute it and/or modify
61 + * it under the terms of the GNU General Public License, version 2, as
62 + * published by the Free Software Foundation (the "GPL").
64 + * This program is distributed in the hope that it will be useful, but
65 + * WITHOUT ANY WARRANTY; without even the implied warranty of
66 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
67 + * General Public License version 2 (GPLv2) for more details.
69 + * You should have received a copy of the GNU General Public License
70 + * version 2 (GPLv2) along with this source code.
73 +#include <linux/clk.h>
74 +#include <linux/delay.h>
75 +#include <linux/device.h>
76 +#include <linux/init.h>
77 +#include <linux/interrupt.h>
78 +#include <linux/io.h>
79 +#include <linux/ioport.h>
80 +#include <linux/kernel.h>
81 +#include <linux/module.h>
82 +#include <linux/mtd/cfi.h>
83 +#include <linux/mtd/spi-nor.h>
84 +#include <linux/of.h>
85 +#include <linux/of_irq.h>
86 +#include <linux/platform_device.h>
87 +#include <linux/slab.h>
88 +#include <linux/spi/spi.h>
89 +#include <linux/sysfs.h>
90 +#include <linux/types.h>
91 +#include "spi-bcm-qspi.h"
93 +#define DRIVER_NAME "bcm_qspi"
95 +/* MSPI register offsets */
96 +#define MSPI_SPCR0_LSB 0x000
97 +#define MSPI_SPCR0_MSB 0x004
98 +#define MSPI_SPCR1_LSB 0x008
99 +#define MSPI_SPCR1_MSB 0x00c
100 +#define MSPI_NEWQP 0x010
101 +#define MSPI_ENDQP 0x014
102 +#define MSPI_SPCR2 0x018
103 +#define MSPI_MSPI_STATUS 0x020
104 +#define MSPI_CPTQP 0x024
105 +#define MSPI_SPCR3 0x028
106 +#define MSPI_TXRAM 0x040
107 +#define MSPI_RXRAM 0x0c0
108 +#define MSPI_CDRAM 0x140
109 +#define MSPI_WRITE_LOCK 0x180
111 +#define MSPI_MASTER_BIT BIT(7)
113 +#define MSPI_NUM_CDRAM 16
114 +#define MSPI_CDRAM_CONT_BIT BIT(7)
115 +#define MSPI_CDRAM_BITSE_BIT BIT(6)
116 +#define MSPI_CDRAM_PCS 0xf
118 +#define MSPI_SPCR2_SPE BIT(6)
119 +#define MSPI_SPCR2_CONT_AFTER_CMD BIT(7)
121 +#define MSPI_MSPI_STATUS_SPIF BIT(0)
123 +#define INTR_BASE_BIT_SHIFT 0x02
124 +#define INTR_COUNT 0x07
126 +#define NUM_CHIPSELECT 4
127 +#define QSPI_SPBR_MIN 8U
128 +#define QSPI_SPBR_MAX 255U
130 +#define OPCODE_DIOR 0xBB
131 +#define OPCODE_QIOR 0xEB
132 +#define OPCODE_DIOR_4B 0xBC
133 +#define OPCODE_QIOR_4B 0xEC
135 +#define MAX_CMD_SIZE 6
137 +#define ADDR_4MB_MASK GENMASK(22, 0)
139 +/* stop at end of transfer, no other reason */
140 +#define TRANS_STATUS_BREAK_NONE 0
141 +/* stop at end of spi_message */
142 +#define TRANS_STATUS_BREAK_EOM 1
143 +/* stop at end of spi_transfer if delay */
144 +#define TRANS_STATUS_BREAK_DELAY 2
145 +/* stop at end of spi_transfer if cs_change */
146 +#define TRANS_STATUS_BREAK_CS_CHANGE 4
147 +/* stop if we run out of bytes */
148 +#define TRANS_STATUS_BREAK_NO_BYTES 8
150 +/* events that make us stop filling TX slots */
151 +#define TRANS_STATUS_BREAK_TX (TRANS_STATUS_BREAK_EOM | \
152 + TRANS_STATUS_BREAK_DELAY | \
153 + TRANS_STATUS_BREAK_CS_CHANGE)
155 +/* events that make us deassert CS */
156 +#define TRANS_STATUS_BREAK_DESELECT (TRANS_STATUS_BREAK_EOM | \
157 + TRANS_STATUS_BREAK_CS_CHANGE)
159 +struct bcm_qspi_parms {
171 +struct bcm_qspi_irq {
172 + const char *irq_name;
173 + const irq_handler_t irq_handler;
177 +struct bcm_qspi_dev_id {
178 + const struct bcm_qspi_irq *irqp;
183 + struct spi_transfer *trans;
188 + struct platform_device *pdev;
189 + struct spi_master *master;
193 + void __iomem *base[BASEMAX];
194 + struct bcm_qspi_parms last_parms;
195 + struct qspi_trans trans_pos;
197 + u32 s3_strap_override_ctrl;
200 + struct bcm_qspi_dev_id *dev_ids;
201 + struct completion mspi_done;
204 +/* Read qspi controller register*/
205 +static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
206 + unsigned int offset)
208 + return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
211 +/* Write qspi controller register*/
212 +static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
213 + unsigned int offset, unsigned int data)
215 + bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
218 +static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
222 + if (qspi->curr_cs == cs)
224 + if (qspi->base[CHIP_SELECT]) {
225 + data = bcm_qspi_read(qspi, CHIP_SELECT, 0);
226 + data = (data & ~0xff) | (1 << cs);
227 + bcm_qspi_write(qspi, CHIP_SELECT, 0, data);
228 + usleep_range(10, 20);
230 + qspi->curr_cs = cs;
234 +static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
235 + const struct bcm_qspi_parms *xp)
237 + u32 spcr, spbr = 0;
240 + spbr = qspi->base_clk / (2 * xp->speed_hz);
242 + spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
243 + bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
245 + spcr = MSPI_MASTER_BIT;
246 + /* for 16 bit the data should be zero */
247 + if (xp->bits_per_word != 16)
248 + spcr |= xp->bits_per_word << 2;
249 + spcr |= xp->mode & 3;
250 + bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
252 + qspi->last_parms = *xp;
255 +static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
256 + struct spi_device *spi,
257 + struct spi_transfer *trans)
259 + struct bcm_qspi_parms xp;
261 + xp.speed_hz = trans->speed_hz;
262 + xp.bits_per_word = trans->bits_per_word;
263 + xp.mode = spi->mode;
265 + bcm_qspi_hw_set_parms(qspi, &xp);
268 +static int bcm_qspi_setup(struct spi_device *spi)
270 + struct bcm_qspi_parms *xp;
272 + if (spi->bits_per_word > 16)
275 + xp = spi_get_ctldata(spi);
277 + xp = kzalloc(sizeof(*xp), GFP_KERNEL);
280 + spi_set_ctldata(spi, xp);
282 + xp->speed_hz = spi->max_speed_hz;
283 + xp->mode = spi->mode;
285 + if (spi->bits_per_word)
286 + xp->bits_per_word = spi->bits_per_word;
288 + xp->bits_per_word = 8;
293 +static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
294 + struct qspi_trans *qt, int flags)
296 + int ret = TRANS_STATUS_BREAK_NONE;
298 + /* count the last transferred bytes */
299 + if (qt->trans->bits_per_word <= 8)
304 + if (qt->byte >= qt->trans->len) {
305 + /* we're at the end of the spi_transfer */
307 + /* in TX mode, need to pause for a delay or CS change */
308 + if (qt->trans->delay_usecs &&
309 + (flags & TRANS_STATUS_BREAK_DELAY))
310 + ret |= TRANS_STATUS_BREAK_DELAY;
311 + if (qt->trans->cs_change &&
312 + (flags & TRANS_STATUS_BREAK_CS_CHANGE))
313 + ret |= TRANS_STATUS_BREAK_CS_CHANGE;
317 + dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
318 + if (spi_transfer_is_last(qspi->master, qt->trans))
319 + ret = TRANS_STATUS_BREAK_EOM;
321 + ret = TRANS_STATUS_BREAK_NO_BYTES;
327 + dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
328 + qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
332 +static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
334 + u32 slot_offset = MSPI_RXRAM + (slot << 3) + 0x4;
336 + /* mask out reserved bits */
337 + return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
340 +static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
342 + u32 reg_offset = MSPI_RXRAM;
343 + u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
344 + u32 msb_offset = reg_offset + (slot << 3);
346 + return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
347 + ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
350 +static void read_from_hw(struct bcm_qspi *qspi, int slots)
352 + struct qspi_trans tp;
355 + if (slots > MSPI_NUM_CDRAM) {
356 + /* should never happen */
357 + dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
361 + tp = qspi->trans_pos;
363 + for (slot = 0; slot < slots; slot++) {
364 + if (tp.trans->bits_per_word <= 8) {
365 + u8 *buf = tp.trans->rx_buf;
368 + buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
369 + dev_dbg(&qspi->pdev->dev, "RD %02x\n",
370 + buf ? buf[tp.byte] : 0xff);
372 + u16 *buf = tp.trans->rx_buf;
375 + buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
377 + dev_dbg(&qspi->pdev->dev, "RD %04x\n",
378 + buf ? buf[tp.byte] : 0xffff);
381 + update_qspi_trans_byte_count(qspi, &tp,
382 + TRANS_STATUS_BREAK_NONE);
385 + qspi->trans_pos = tp;
388 +static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
391 + u32 reg_offset = MSPI_TXRAM + (slot << 3);
393 + /* mask out reserved bits */
394 + bcm_qspi_write(qspi, MSPI, reg_offset, val);
397 +static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
400 + u32 reg_offset = MSPI_TXRAM;
401 + u32 msb_offset = reg_offset + (slot << 3);
402 + u32 lsb_offset = reg_offset + (slot << 3) + 0x4;
404 + bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
405 + bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
408 +static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
410 + return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
413 +static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
415 + bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
418 +/* Return number of slots written */
419 +static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
421 + struct qspi_trans tp;
422 + int slot = 0, tstatus = 0;
423 + u32 mspi_cdram = 0;
425 + tp = qspi->trans_pos;
426 + bcm_qspi_update_parms(qspi, spi, tp.trans);
428 + /* Run until end of transfer or reached the max data */
429 + while (!tstatus && slot < MSPI_NUM_CDRAM) {
430 + if (tp.trans->bits_per_word <= 8) {
431 + const u8 *buf = tp.trans->tx_buf;
432 + u8 val = buf ? buf[tp.byte] : 0xff;
434 + write_txram_slot_u8(qspi, slot, val);
435 + dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
437 + const u16 *buf = tp.trans->tx_buf;
438 + u16 val = buf ? buf[tp.byte / 2] : 0xffff;
440 + write_txram_slot_u16(qspi, slot, val);
441 + dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
443 + mspi_cdram = MSPI_CDRAM_CONT_BIT;
444 + mspi_cdram |= (~(1 << spi->chip_select) &
446 + mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
447 + MSPI_CDRAM_BITSE_BIT);
449 + write_cdram_slot(qspi, slot, mspi_cdram);
451 + tstatus = update_qspi_trans_byte_count(qspi, &tp,
452 + TRANS_STATUS_BREAK_TX);
457 + dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
461 + dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
462 + bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
463 + bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
465 + if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
466 + mspi_cdram = read_cdram_slot(qspi, slot - 1) &
467 + ~MSPI_CDRAM_CONT_BIT;
468 + write_cdram_slot(qspi, slot - 1, mspi_cdram);
471 + /* Must flush previous writes before starting MSPI operation */
473 + /* Set cont | spe | spifie */
474 + bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
480 +static int bcm_qspi_transfer_one(struct spi_master *master,
481 + struct spi_device *spi,
482 + struct spi_transfer *trans)
484 + struct bcm_qspi *qspi = spi_master_get_devdata(master);
486 + unsigned long timeo = msecs_to_jiffies(100);
488 + bcm_qspi_chip_select(qspi, spi->chip_select);
489 + qspi->trans_pos.trans = trans;
490 + qspi->trans_pos.byte = 0;
492 + while (qspi->trans_pos.byte < trans->len) {
493 + reinit_completion(&qspi->mspi_done);
495 + slots = write_to_hw(qspi, spi);
496 + if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
497 + dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
501 + read_from_hw(qspi, slots);
507 +static void bcm_qspi_cleanup(struct spi_device *spi)
509 + struct bcm_qspi_parms *xp = spi_get_ctldata(spi);
514 +static irqreturn_t bcm_qspi_mspi_l2_isr(int irq, void *dev_id)
516 + struct bcm_qspi_dev_id *qspi_dev_id = dev_id;
517 + struct bcm_qspi *qspi = qspi_dev_id->dev;
518 + u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
520 + if (status & MSPI_MSPI_STATUS_SPIF) {
521 + /* clear interrupt */
522 + status &= ~MSPI_MSPI_STATUS_SPIF;
523 + bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
524 + complete(&qspi->mspi_done);
525 + return IRQ_HANDLED;
531 +static const struct bcm_qspi_irq qspi_irq_tab[] = {
533 + .irq_name = "mspi_done",
534 + .irq_handler = bcm_qspi_mspi_l2_isr,
535 + .mask = INTR_MSPI_DONE_MASK,
538 + .irq_name = "mspi_halted",
539 + .irq_handler = bcm_qspi_mspi_l2_isr,
540 + .mask = INTR_MSPI_HALTED_MASK,
544 +static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
546 + struct bcm_qspi_parms parms;
548 + bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
549 + bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
550 + bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
551 + bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
552 + bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
554 + parms.mode = SPI_MODE_3;
555 + parms.bits_per_word = 8;
556 + parms.speed_hz = qspi->max_speed_hz;
557 + bcm_qspi_hw_set_parms(qspi, &parms);
560 +static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
562 + bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
565 +static const struct of_device_id bcm_qspi_of_match[] = {
566 + { .compatible = "brcm,spi-bcm-qspi" },
569 +MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
571 +int bcm_qspi_probe(struct platform_device *pdev,
572 + struct bcm_qspi_soc_intc *soc)
574 + struct device *dev = &pdev->dev;
575 + struct bcm_qspi *qspi;
576 + struct spi_master *master;
577 + struct resource *res;
578 + int irq, ret = 0, num_ints = 0;
580 + const char *name = NULL;
581 + int num_irqs = ARRAY_SIZE(qspi_irq_tab);
583 + /* We only support device-tree instantiation */
587 + if (!of_match_node(bcm_qspi_of_match, dev->of_node))
590 + master = spi_alloc_master(dev, sizeof(struct bcm_qspi));
592 + dev_err(dev, "error allocating spi_master\n");
596 + qspi = spi_master_get_devdata(master);
598 + qspi->trans_pos.trans = NULL;
599 + qspi->trans_pos.byte = 0;
600 + qspi->master = master;
602 + master->bus_num = -1;
603 + master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD;
604 + master->setup = bcm_qspi_setup;
605 + master->transfer_one = bcm_qspi_transfer_one;
606 + master->cleanup = bcm_qspi_cleanup;
607 + master->dev.of_node = dev->of_node;
608 + master->num_chipselect = NUM_CHIPSELECT;
610 + qspi->big_endian = of_device_is_big_endian(dev->of_node);
612 + if (!of_property_read_u32(dev->of_node, "num-cs", &val))
613 + master->num_chipselect = val;
615 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
617 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
621 + qspi->base[MSPI] = devm_ioremap_resource(dev, res);
622 + if (IS_ERR(qspi->base[MSPI])) {
623 + ret = PTR_ERR(qspi->base[MSPI]);
624 + goto qspi_probe_err;
627 + goto qspi_probe_err;
630 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs_reg");
632 + qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
633 + if (IS_ERR(qspi->base[CHIP_SELECT])) {
634 + ret = PTR_ERR(qspi->base[CHIP_SELECT]);
635 + goto qspi_probe_err;
639 + qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
641 + if (IS_ERR(qspi->dev_ids)) {
642 + ret = PTR_ERR(qspi->dev_ids);
643 + goto qspi_probe_err;
646 + for (val = 0; val < num_irqs; val++) {
648 + name = qspi_irq_tab[val].irq_name;
649 + irq = platform_get_irq_byname(pdev, name);
652 + ret = devm_request_irq(&pdev->dev, irq,
653 + qspi_irq_tab[val].irq_handler, 0,
655 + &qspi->dev_ids[val]);
657 + dev_err(&pdev->dev, "IRQ %s not found\n", name);
658 + goto qspi_probe_err;
661 + qspi->dev_ids[val].dev = qspi;
662 + qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
664 + dev_dbg(&pdev->dev, "registered IRQ %s %d\n",
665 + qspi_irq_tab[val].irq_name,
671 + dev_err(&pdev->dev, "no IRQs registered, cannot init driver\n");
672 + goto qspi_probe_err;
675 + qspi->clk = devm_clk_get(&pdev->dev, NULL);
676 + if (IS_ERR(qspi->clk)) {
677 + dev_warn(dev, "unable to get clock\n");
678 + goto qspi_probe_err;
681 + ret = clk_prepare_enable(qspi->clk);
683 + dev_err(dev, "failed to prepare clock\n");
684 + goto qspi_probe_err;
687 + qspi->base_clk = clk_get_rate(qspi->clk);
688 + qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
690 + bcm_qspi_hw_init(qspi);
691 + init_completion(&qspi->mspi_done);
692 + qspi->curr_cs = -1;
694 + platform_set_drvdata(pdev, qspi);
695 + ret = devm_spi_register_master(&pdev->dev, master);
697 + dev_err(dev, "can't register master\n");
704 + bcm_qspi_hw_uninit(qspi);
705 + clk_disable_unprepare(qspi->clk);
707 + spi_master_put(master);
708 + kfree(qspi->dev_ids);
711 +/* probe function to be called by SoC specific platform driver probe */
712 +EXPORT_SYMBOL_GPL(bcm_qspi_probe);
714 +int bcm_qspi_remove(struct platform_device *pdev)
716 + struct bcm_qspi *qspi = platform_get_drvdata(pdev);
718 + platform_set_drvdata(pdev, NULL);
719 + bcm_qspi_hw_uninit(qspi);
720 + clk_disable_unprepare(qspi->clk);
721 + kfree(qspi->dev_ids);
722 + spi_unregister_master(qspi->master);
726 +/* function to be called by SoC specific platform driver remove() */
727 +EXPORT_SYMBOL_GPL(bcm_qspi_remove);
729 +#ifdef CONFIG_PM_SLEEP
730 +static int bcm_qspi_suspend(struct device *dev)
732 + struct bcm_qspi *qspi = dev_get_drvdata(dev);
734 + spi_master_suspend(qspi->master);
735 + clk_disable(qspi->clk);
736 + bcm_qspi_hw_uninit(qspi);
741 +static int bcm_qspi_resume(struct device *dev)
743 + struct bcm_qspi *qspi = dev_get_drvdata(dev);
746 + bcm_qspi_hw_init(qspi);
747 + bcm_qspi_chip_select(qspi, qspi->curr_cs);
748 + ret = clk_enable(qspi->clk);
750 + spi_master_resume(qspi->master);
754 +#endif /* CONFIG_PM_SLEEP */
756 +const struct dev_pm_ops bcm_qspi_pm_ops = {
757 + .suspend = bcm_qspi_suspend,
758 + .resume = bcm_qspi_resume,
760 +/* pm_ops to be called by SoC specific platform driver */
761 +EXPORT_SYMBOL_GPL(bcm_qspi_pm_ops);
763 +MODULE_AUTHOR("Kamal Dasu");
764 +MODULE_DESCRIPTION("Broadcom QSPI driver");
765 +MODULE_LICENSE("GPL v2");
766 +MODULE_ALIAS("platform:" DRIVER_NAME);
768 +++ b/drivers/spi/spi-bcm-qspi.h
771 + * Copyright 2016 Broadcom
773 + * This program is free software; you can redistribute it and/or modify
774 + * it under the terms of the GNU General Public License, version 2, as
775 + * published by the Free Software Foundation (the "GPL").
777 + * This program is distributed in the hope that it will be useful, but
778 + * WITHOUT ANY WARRANTY; without even the implied warranty of
779 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
780 + * General Public License version 2 (GPLv2) for more details.
782 + * You should have received a copy of the GNU General Public License
783 + * version 2 (GPLv2) along with this source code.
786 +#ifndef __SPI_BCM_QSPI_H__
787 +#define __SPI_BCM_QSPI_H__
789 +#include <linux/types.h>
790 +#include <linux/io.h>
792 +/* MSPI Interrupt masks */
793 +#define INTR_MSPI_HALTED_MASK BIT(6)
794 +#define INTR_MSPI_DONE_MASK BIT(5)
796 +#define MSPI_INTERRUPTS_ALL \
797 + (INTR_MSPI_DONE_MASK | \
798 + INTR_MSPI_HALTED_MASK)
800 +struct platform_device;
803 +struct bcm_qspi_soc_intc;
805 +/* Read controller register*/
806 +static inline u32 bcm_qspi_readl(bool be, void __iomem *addr)
809 + return ioread32be(addr);
811 + return readl_relaxed(addr);
814 +/* Write controller register*/
815 +static inline void bcm_qspi_writel(bool be,
816 + unsigned int data, void __iomem *addr)
819 + iowrite32be(data, addr);
821 + writel_relaxed(data, addr);
824 +/* The common driver functions to be called by the SoC platform driver */
825 +int bcm_qspi_probe(struct platform_device *pdev,
826 + struct bcm_qspi_soc_intc *soc_intc);
827 +int bcm_qspi_remove(struct platform_device *pdev);
829 +/* pm_ops used by the SoC platform driver called on PM suspend/resume */
830 +extern const struct dev_pm_ops bcm_qspi_pm_ops;
832 +#endif /* __SPI_BCM_QSPI_H__ */