1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
2 Subject: [PATCH] ARM: BCM5301X: Add basic dts for BCM53573 based Tenda AC9
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5 Content-Transfer-Encoding: 8bit
7 BCM53573 seems to be low priced alternative for standard Northstar
8 chipsets. It uses single core Cortex-A7, doesn't have SDU or local (TWD)
9 timer. It was also stripped out of independent SPI controller and 2
12 DTS for Tenda AC9 isn't completed yet. It misses e.g. switch entry (we
13 still need some bgmac/b53 fixes) and probably some clocks. It adds
14 support for basic features however and can be improved later.
16 Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
19 arch/arm/boot/dts/Makefile | 1 +
20 arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 74 ++++++++++++++++
21 arch/arm/boot/dts/bcm53573.dtsi | 147 +++++++++++++++++++++++++++++++
22 4 files changed, 224 insertions(+)
23 create mode 100644 arch/arm/boot/dts/bcm47189-tenda-ac9.dts
24 create mode 100644 arch/arm/boot/dts/bcm53573.dtsi
28 @@ -2337,6 +2337,8 @@ S: Maintained
29 F: arch/arm/mach-bcm/bcm_5301x.c
30 F: arch/arm/boot/dts/bcm5301x.dtsi
31 F: arch/arm/boot/dts/bcm470*
32 +F: arch/arm/boot/dts/bcm53573*
33 +F: arch/arm/boot/dts/bcm47189*
35 BROADCOM BCM53573 ARM ARCHITECTURE
36 M: Rafał Miłecki <rafal@milecki.pl>
37 --- a/arch/arm/boot/dts/Makefile
38 +++ b/arch/arm/boot/dts/Makefile
39 @@ -77,6 +77,7 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
40 bcm4709-netgear-r7000.dtb \
41 bcm4709-netgear-r8000.dtb \
42 bcm47094-dlink-dir-885l.dtb \
43 + bcm47189-tenda-ac9.dtb \
48 +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
51 + * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
53 + * Licensed under the ISC license.
58 +#include "bcm53573.dtsi"
61 + compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573";
62 + model = "Tenda AC9";
65 + bootargs = "console=ttyS0,115200 earlycon";
69 + reg = <0x00000000 0x08000000>;
73 + compatible = "gpio-leds";
76 + label = "bcm53xx:blue:usb";
77 + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
78 + linux,default-trigger = "default-off";
82 + label = "bcm53xx:blue:wps";
83 + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
84 + linux,default-trigger = "default-off";
88 + label = "bcm53xx:blue:5ghz";
89 + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
90 + linux,default-trigger = "default-off";
94 + label = "bcm53xx:blue:system";
95 + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
96 + linux,default-trigger = "timer";
101 + compatible = "gpio-keys";
102 + #address-cells = <1>;
107 + linux,code = <KEY_RFKILL>;
108 + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
113 + linux,code = <KEY_RESTART>;
114 + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
119 + linux,code = <KEY_WPS_BUTTON>;
120 + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
125 +++ b/arch/arm/boot/dts/bcm53573.dtsi
128 + * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
130 + * Licensed under the ISC license.
133 +#include <dt-bindings/gpio/gpio.h>
134 +#include <dt-bindings/input/input.h>
135 +#include <dt-bindings/interrupt-controller/irq.h>
136 +#include <dt-bindings/interrupt-controller/arm-gic.h>
137 +#include "skeleton.dtsi"
140 + interrupt-parent = <&gic>;
143 + stdout-path = &uart0;
147 + #address-cells = <1>;
151 + device_type = "cpu";
152 + compatible = "arm,cortex-a7";
158 + compatible = "simple-bus";
159 + ranges = <0x00000000 0x18310000 0x00008000>;
160 + #address-cells = <1>;
163 + gic: interrupt-controller@1000 {
164 + compatible = "arm,cortex-a7-gic";
165 + #interrupt-cells = <3>;
166 + #address-cells = <0>;
167 + interrupt-controller;
168 + reg = <0x1000 0x1000>,
174 + #address-cells = <1>;
179 + #clock-cells = <0>;
180 + compatible = "fixed-clock";
181 + clock-frequency = <40000000>;
186 + compatible = "brcm,bus-axi";
187 + reg = <0x18000000 0x1000>;
188 + ranges = <0x00000000 0x18000000 0x00100000>;
189 + #address-cells = <1>;
192 + #interrupt-cells = <1>;
193 + interrupt-map-mask = <0x000fffff 0xffff>;
196 + <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
198 + /* IEEE 802.11 0 */
199 + <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
201 + /* PCIe Controller 0 */
202 + <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
203 + <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
204 + <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
205 + <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
206 + <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
207 + <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
209 + /* USB 2.0 Controller */
210 + <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
212 + /* Ethernet Controller 0 */
213 + <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
215 + /* IEEE 802.11 1 */
216 + <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
218 + /* Ethernet Controller 1 */
219 + <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
221 + chipcommon: chipcommon@0 {
222 + compatible = "simple-bus";
223 + reg = <0x00000000 0x1000>;
226 + #address-cells = <1>;
232 + uart0: serial@0300 {
233 + compatible = "ns16550a";
234 + reg = <0x0300 0x100>;
235 + interrupt-parent = <&gic>;
236 + interrupts = <GIC_PPI 16 IRQ_TYPE_LEVEL_HIGH>;
243 + reg = <0x4000 0x1000>;
245 + #address-cells = <1>;
249 + compatible = "generic-ehci";
250 + reg = <0x4000 0x1000>;
251 + interrupt-parent = <&gic>;
252 + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
258 + compatible = "generic-ohci";
259 + reg = <0xd000 0x1000>;
260 + interrupt-parent = <&gic>;
261 + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
265 + gmac0: ethernet@5000 {
266 + reg = <0x5000 0x1000>;
269 + gmac1: ethernet@b000 {
270 + reg = <0xb000 0x1000>;