1 From 45444cb631555e2dc16b95d779b10aa075c7482e Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Fri, 24 Jun 2016 22:14:13 +0200
4 Subject: [PATCH 05/16] pinctrl: add a pincontrol driver for BCM6348
6 Add a pincotrol driver for BCM6348. BCM6348 allow muxing five groups of
7 up to ten gpios into fourteen potential functions. It does not allow
8 muxing individual pins. Some functions require more than one group to be
9 muxed to the same function.
11 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
13 drivers/pinctrl/bcm63xx/Kconfig | 7 +
14 drivers/pinctrl/bcm63xx/Makefile | 1 +
15 drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c | 391 ++++++++++++++++++++++++++++++
16 3 files changed, 399 insertions(+)
17 create mode 100644 drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c
19 --- a/drivers/pinctrl/bcm63xx/Kconfig
20 +++ b/drivers/pinctrl/bcm63xx/Kconfig
21 @@ -8,3 +8,10 @@ config PINCTRL_BCM6328
23 select PINCTRL_BCM63XX
24 select GENERIC_PINCONF
26 +config PINCTRL_BCM6348
27 + bool "BCM6348 pincontrol driver" if COMPILE_TEST
30 + select PINCTRL_BCM63XX
31 + select GENERIC_PINCONF
32 --- a/drivers/pinctrl/bcm63xx/Makefile
33 +++ b/drivers/pinctrl/bcm63xx/Makefile
35 obj-$(CONFIG_PINCTRL_BCM63XX) += pinctrl-bcm63xx.o
36 obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
37 +obj-$(CONFIG_PINCTRL_BCM6348) += pinctrl-bcm6348.o
39 +++ b/drivers/pinctrl/bcm63xx/pinctrl-bcm6348.c
42 + * This file is subject to the terms and conditions of the GNU General Public
43 + * License. See the file "COPYING" in the main directory of this archive
46 + * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
49 +#include <linux/kernel.h>
50 +#include <linux/spinlock.h>
51 +#include <linux/bitops.h>
52 +#include <linux/gpio.h>
53 +#include <linux/of.h>
54 +#include <linux/of_gpio.h>
55 +#include <linux/slab.h>
56 +#include <linux/platform_device.h>
58 +#include <linux/pinctrl/machine.h>
59 +#include <linux/pinctrl/pinconf.h>
60 +#include <linux/pinctrl/pinconf-generic.h>
61 +#include <linux/pinctrl/pinmux.h>
64 +#include "../pinctrl-utils.h"
66 +#include "pinctrl-bcm63xx.h"
68 +#define BCM6348_NGPIO 37
71 +#define PINS_PER_GROUP 8
72 +#define PIN_TO_GROUP(pin) (MAX_GROUP - ((pin) / PINS_PER_GROUP))
73 +#define GROUP_SHIFT(pin) (PIN_TO_GROUP(pin) * 4)
74 +#define GROUP_MASK(pin) (0xf << GROUP_SHIFT(pin))
76 +struct bcm6348_pingroup {
78 + const unsigned * const pins;
79 + const unsigned num_pins;
82 +struct bcm6348_function {
84 + const char * const *groups;
85 + const unsigned num_groups;
89 +struct bcm6348_pinctrl {
90 + struct pinctrl_dev *pctldev;
91 + struct pinctrl_desc desc;
95 + /* register access lock */
98 + struct gpio_chip gpio[2];
101 +#define BCM6348_PIN(a, b, group) \
105 + .drv_data = (void *)(group), \
108 +static const struct pinctrl_pin_desc bcm6348_pins[] = {
109 + BCM6348_PIN(0, "gpio0", 4),
110 + BCM6348_PIN(1, "gpio1", 4),
111 + BCM6348_PIN(2, "gpio2", 4),
112 + BCM6348_PIN(3, "gpio3", 4),
113 + BCM6348_PIN(4, "gpio4", 4),
114 + BCM6348_PIN(5, "gpio5", 4),
115 + BCM6348_PIN(6, "gpio6", 4),
116 + BCM6348_PIN(7, "gpio7", 4),
117 + BCM6348_PIN(8, "gpio8", 3),
118 + BCM6348_PIN(9, "gpio9", 3),
119 + BCM6348_PIN(10, "gpio10", 3),
120 + BCM6348_PIN(11, "gpio11", 3),
121 + BCM6348_PIN(12, "gpio12", 3),
122 + BCM6348_PIN(13, "gpio13", 3),
123 + BCM6348_PIN(14, "gpio14", 3),
124 + BCM6348_PIN(15, "gpio15", 3),
125 + BCM6348_PIN(16, "gpio16", 2),
126 + BCM6348_PIN(17, "gpio17", 2),
127 + BCM6348_PIN(18, "gpio18", 2),
128 + BCM6348_PIN(19, "gpio19", 2),
129 + BCM6348_PIN(20, "gpio20", 2),
130 + BCM6348_PIN(21, "gpio21", 2),
131 + BCM6348_PIN(22, "gpio22", 1),
132 + BCM6348_PIN(23, "gpio23", 1),
133 + BCM6348_PIN(24, "gpio24", 1),
134 + BCM6348_PIN(25, "gpio25", 1),
135 + BCM6348_PIN(26, "gpio26", 1),
136 + BCM6348_PIN(27, "gpio27", 1),
137 + BCM6348_PIN(28, "gpio28", 1),
138 + BCM6348_PIN(29, "gpio29", 1),
139 + BCM6348_PIN(30, "gpio30", 1),
140 + BCM6348_PIN(31, "gpio31", 1),
141 + BCM6348_PIN(32, "gpio32", 0),
142 + BCM6348_PIN(33, "gpio33", 0),
143 + BCM6348_PIN(34, "gpio34", 0),
144 + BCM6348_PIN(35, "gpio35", 0),
145 + BCM6348_PIN(36, "gpio36", 0),
148 +enum bcm6348_muxes {
149 + BCM6348_MUX_GPIO = 0,
150 + BCM6348_MUX_EXT_EPHY,
151 + BCM6348_MUX_MII_SNOOP,
152 + BCM6348_MUX_LEGACY_LED,
153 + BCM6348_MUX_MII_PCCARD,
155 + BCM6348_MUX_SPI_MASTER_UART,
156 + BCM6348_MUX_EXT_MII,
157 + BCM6348_MUX_UTOPIA,
161 +static unsigned group0_pins[] = {
162 + 32, 33, 34, 35, 36,
165 +static unsigned group1_pins[] = {
166 + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
169 +static unsigned group2_pins[] = {
170 + 16, 17, 18, 19, 20, 21,
173 +static unsigned group3_pins[] = {
174 + 8, 9, 10, 11, 12, 13, 14, 15,
177 +static unsigned group4_pins[] = {
178 + 0, 1, 2, 3, 4, 5, 6, 7,
181 +#define BCM6348_GROUP(n) \
184 + .pins = n##_pins, \
185 + .num_pins = ARRAY_SIZE(n##_pins), \
188 +static struct bcm6348_pingroup bcm6348_groups[] = {
189 + BCM6348_GROUP(group0),
190 + BCM6348_GROUP(group1),
191 + BCM6348_GROUP(group2),
192 + BCM6348_GROUP(group3),
193 + BCM6348_GROUP(group4),
196 +static const char * const ext_mii_groups[] = {
201 +static const char * const ext_ephy_groups[] = {
206 +static const char * const mii_snoop_groups[] = {
211 +static const char * const legacy_led_groups[] = {
215 +static const char * const mii_pccard_groups[] = {
219 +static const char * const pci_groups[] = {
223 +static const char * const spi_master_uart_groups[] = {
227 +static const char * const utopia_groups[] = {
233 +static const char * const diag_groups[] = {
241 +#define BCM6348_FUN(n, f) \
244 + .groups = n##_groups, \
245 + .num_groups = ARRAY_SIZE(n##_groups), \
246 + .value = BCM6348_MUX_##f, \
249 +static const struct bcm6348_function bcm6348_funcs[] = {
250 + BCM6348_FUN(ext_mii, EXT_MII),
251 + BCM6348_FUN(ext_ephy, EXT_EPHY),
252 + BCM6348_FUN(mii_snoop, MII_SNOOP),
253 + BCM6348_FUN(legacy_led, LEGACY_LED),
254 + BCM6348_FUN(mii_pccard, MII_PCCARD),
255 + BCM6348_FUN(pci, PCI),
256 + BCM6348_FUN(spi_master_uart, SPI_MASTER_UART),
257 + BCM6348_FUN(utopia, UTOPIA),
258 + BCM6348_FUN(diag, DIAG),
261 +static int bcm6348_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
263 + return ARRAY_SIZE(bcm6348_groups);
266 +static const char *bcm6348_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
269 + return bcm6348_groups[group].name;
272 +static int bcm6348_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
273 + unsigned group, const unsigned **pins,
274 + unsigned *num_pins)
276 + *pins = bcm6348_groups[group].pins;
277 + *num_pins = bcm6348_groups[group].num_pins;
282 +static int bcm6348_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
284 + return ARRAY_SIZE(bcm6348_funcs);
287 +static const char *bcm6348_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
290 + return bcm6348_funcs[selector].name;
293 +static int bcm6348_pinctrl_get_groups(struct pinctrl_dev *pctldev,
295 + const char * const **groups,
296 + unsigned * const num_groups)
298 + *groups = bcm6348_funcs[selector].groups;
299 + *num_groups = bcm6348_funcs[selector].num_groups;
304 +static void bcm6348_rmw_mux(struct bcm6348_pinctrl *pctl, u32 mask, u32 val)
306 + unsigned long flags;
309 + spin_lock_irqsave(&pctl->lock, flags);
311 + reg = __raw_readl(pctl->mode);
314 + __raw_writel(reg, pctl->mode);
316 + spin_unlock_irqrestore(&pctl->lock, flags);
319 +static int bcm6348_pinctrl_set_mux(struct pinctrl_dev *pctldev,
320 + unsigned selector, unsigned group)
322 + struct bcm6348_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
323 + const struct bcm6348_pingroup *grp = &bcm6348_groups[group];
324 + const struct bcm6348_function *f = &bcm6348_funcs[selector];
328 + * pins n..(n+7) share the same group, so we only need to look at
331 + mask = GROUP_MASK(grp->pins[0]);
332 + val = f->value << GROUP_SHIFT(grp->pins[0]);
334 + bcm6348_rmw_mux(pctl, mask, val);
339 +static struct pinctrl_ops bcm6348_pctl_ops = {
340 + .get_groups_count = bcm6348_pinctrl_get_group_count,
341 + .get_group_name = bcm6348_pinctrl_get_group_name,
342 + .get_group_pins = bcm6348_pinctrl_get_group_pins,
344 + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
345 + .dt_free_map = pinctrl_utils_free_map,
349 +static struct pinmux_ops bcm6348_pmx_ops = {
350 + .get_functions_count = bcm6348_pinctrl_get_func_count,
351 + .get_function_name = bcm6348_pinctrl_get_func_name,
352 + .get_function_groups = bcm6348_pinctrl_get_groups,
353 + .set_mux = bcm6348_pinctrl_set_mux,
357 +static int bcm6348_pinctrl_probe(struct platform_device *pdev)
359 + struct bcm6348_pinctrl *pctl;
360 + struct resource *res;
361 + void __iomem *mode;
363 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mode");
364 + mode = devm_ioremap_resource(&pdev->dev, res);
366 + return PTR_ERR(mode);
368 + pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
372 + spin_lock_init(&pctl->lock);
376 + /* disable all muxes by default */
377 + __raw_writel(0, pctl->mode);
379 + pctl->desc.name = dev_name(&pdev->dev);
380 + pctl->desc.owner = THIS_MODULE;
381 + pctl->desc.pctlops = &bcm6348_pctl_ops;
382 + pctl->desc.pmxops = &bcm6348_pmx_ops;
384 + pctl->desc.npins = ARRAY_SIZE(bcm6348_pins);
385 + pctl->desc.pins = bcm6348_pins;
387 + platform_set_drvdata(pdev, pctl);
389 + pctl->pctldev = bcm63xx_pinctrl_register(pdev, &pctl->desc, pctl,
390 + pctl->gpio, BCM6348_NGPIO);
391 + if (IS_ERR(pctl->pctldev))
392 + return PTR_ERR(pctl->pctldev);
397 +static const struct of_device_id bcm6348_pinctrl_match[] = {
398 + { .compatible = "brcm,bcm6348-pinctrl", },
402 +static struct platform_driver bcm6348_pinctrl_driver = {
403 + .probe = bcm6348_pinctrl_probe,
405 + .name = "bcm6348-pinctrl",
406 + .of_match_table = bcm6348_pinctrl_match,
410 +builtin_platform_driver(bcm6348_pinctrl_driver);