1 From d2d2489e0a4b740abd980e9d1cad952d15bc2d9e Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sun, 30 Nov 2014 14:55:02 +0100
4 Subject: [PATCH] MIPS: BCM63XX: switch to IRQ_DOMAIN
6 Now that we have working IRQ_DOMAIN drivers for both interrupt controllers,
9 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
11 arch/mips/Kconfig | 3 +
12 arch/mips/bcm63xx/irq.c | 612 +++++++++---------------------------------------
13 2 files changed, 108 insertions(+), 507 deletions(-)
15 --- a/arch/mips/Kconfig
16 +++ b/arch/mips/Kconfig
17 @@ -331,6 +331,9 @@ config BCM63XX
19 select DMA_NONCOHERENT
21 + select BCM6345_EXT_IRQ
22 + select BCM6345_PERIPH_IRQ
24 select SYS_SUPPORTS_32BIT_KERNEL
25 select SYS_SUPPORTS_BIG_ENDIAN
26 select SYS_HAS_EARLY_PRINTK
27 --- a/arch/mips/bcm63xx/irq.c
28 +++ b/arch/mips/bcm63xx/irq.c
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 -#include <linux/spinlock.h>
34 +#include <linux/irqchip.h>
35 +#include <linux/irqchip/irq-bcm6345-ext.h>
36 +#include <linux/irqchip/irq-bcm6345-periph.h>
37 #include <asm/irq_cpu.h>
38 #include <asm/mipsregs.h>
39 #include <bcm63xx_cpu.h>
41 #include <bcm63xx_io.h>
42 #include <bcm63xx_irq.h>
45 -static DEFINE_SPINLOCK(ipic_lock);
46 -static DEFINE_SPINLOCK(epic_lock);
48 -static u32 irq_stat_addr[2];
49 -static u32 irq_mask_addr[2];
50 -static void (*dispatch_internal)(int cpu);
51 -static int is_ext_irq_cascaded;
52 -static unsigned int ext_irq_count;
53 -static unsigned int ext_irq_start, ext_irq_end;
54 -static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
55 -static void (*internal_irq_mask)(struct irq_data *d);
56 -static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m);
59 -static inline u32 get_ext_irq_perf_reg(int irq)
62 - return ext_irq_cfg_reg1;
63 - return ext_irq_cfg_reg2;
66 -static inline void handle_internal(int intbit)
68 - if (is_ext_irq_cascaded &&
69 - intbit >= ext_irq_start && intbit <= ext_irq_end)
70 - do_IRQ(intbit - ext_irq_start + IRQ_EXTERNAL_BASE);
72 - do_IRQ(intbit + IRQ_INTERNAL_BASE);
75 -static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,
76 - const struct cpumask *m)
78 - bool enable = cpu_online(cpu);
82 - enable &= cpumask_test_cpu(cpu, m);
83 - else if (irqd_affinity_was_set(d))
84 - enable &= cpumask_test_cpu(cpu, irq_data_get_affinity_mask(d));
90 - * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
91 - * prioritize any interrupt relatively to another. the static counter
92 - * will resume the loop where it ended the last time we left this
96 -#define BUILD_IPIC_INTERNAL(width) \
97 -void __dispatch_internal_##width(int cpu) \
99 - u32 pending[width / 32]; \
100 - unsigned int src, tgt; \
101 - bool irqs_pending = false; \
102 - static unsigned int i[2]; \
103 - unsigned int *next = &i[cpu]; \
104 - unsigned long flags; \
106 - /* read registers in reverse order */ \
107 - spin_lock_irqsave(&ipic_lock, flags); \
108 - for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
111 - val = bcm_readl(irq_stat_addr[cpu] + src * sizeof(u32)); \
112 - val &= bcm_readl(irq_mask_addr[cpu] + src * sizeof(u32)); \
113 - pending[--tgt] = val; \
116 - irqs_pending = true; \
118 - spin_unlock_irqrestore(&ipic_lock, flags); \
120 - if (!irqs_pending) \
124 - unsigned int to_call = *next; \
126 - *next = (*next + 1) & (width - 1); \
127 - if (pending[to_call / 32] & (1 << (to_call & 0x1f))) { \
128 - handle_internal(to_call); \
134 -static void __internal_irq_mask_##width(struct irq_data *d) \
137 - unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
138 - unsigned reg = (irq / 32) ^ (width/32 - 1); \
139 - unsigned bit = irq & 0x1f; \
140 - unsigned long flags; \
143 - spin_lock_irqsave(&ipic_lock, flags); \
144 - for_each_present_cpu(cpu) { \
145 - if (!irq_mask_addr[cpu]) \
148 - val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
149 - val &= ~(1 << bit); \
150 - bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
152 - spin_unlock_irqrestore(&ipic_lock, flags); \
155 -static void __internal_irq_unmask_##width(struct irq_data *d, \
156 - const struct cpumask *m) \
159 - unsigned irq = d->irq - IRQ_INTERNAL_BASE; \
160 - unsigned reg = (irq / 32) ^ (width/32 - 1); \
161 - unsigned bit = irq & 0x1f; \
162 - unsigned long flags; \
165 - spin_lock_irqsave(&ipic_lock, flags); \
166 - for_each_present_cpu(cpu) { \
167 - if (!irq_mask_addr[cpu]) \
170 - val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
171 - if (enable_irq_for_cpu(cpu, d, m)) \
172 - val |= (1 << bit); \
174 - val &= ~(1 << bit); \
175 - bcm_writel(val, irq_mask_addr[cpu] + reg * sizeof(u32));\
177 - spin_unlock_irqrestore(&ipic_lock, flags); \
180 -BUILD_IPIC_INTERNAL(32);
181 -BUILD_IPIC_INTERNAL(64);
183 -asmlinkage void plat_irq_dispatch(void)
188 - cause = read_c0_cause() & read_c0_status() & ST0_IM;
193 - if (cause & CAUSEF_IP7)
195 - if (cause & CAUSEF_IP0)
197 - if (cause & CAUSEF_IP1)
199 - if (cause & CAUSEF_IP2)
200 - dispatch_internal(0);
201 - if (is_ext_irq_cascaded) {
202 - if (cause & CAUSEF_IP3)
203 - dispatch_internal(1);
205 - if (cause & CAUSEF_IP3)
207 - if (cause & CAUSEF_IP4)
209 - if (cause & CAUSEF_IP5)
211 - if (cause & CAUSEF_IP6)
218 - * internal IRQs operations: only mask/unmask on PERF irq mask
221 -static void bcm63xx_internal_irq_mask(struct irq_data *d)
223 - internal_irq_mask(d);
226 -static void bcm63xx_internal_irq_unmask(struct irq_data *d)
228 - internal_irq_unmask(d, NULL);
232 - * external IRQs operations: mask/unmask and clear on PERF external
233 - * irq control register.
235 -static void bcm63xx_external_irq_mask(struct irq_data *d)
237 - unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
239 - unsigned long flags;
241 - regaddr = get_ext_irq_perf_reg(irq);
242 - spin_lock_irqsave(&epic_lock, flags);
243 - reg = bcm_perf_readl(regaddr);
245 - if (BCMCPU_IS_6348())
246 - reg &= ~EXTIRQ_CFG_MASK_6348(irq % 4);
248 - reg &= ~EXTIRQ_CFG_MASK(irq % 4);
250 - bcm_perf_writel(reg, regaddr);
251 - spin_unlock_irqrestore(&epic_lock, flags);
253 - if (is_ext_irq_cascaded)
254 - internal_irq_mask(irq_get_irq_data(irq + ext_irq_start));
257 -static void bcm63xx_external_irq_unmask(struct irq_data *d)
259 - unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
261 - unsigned long flags;
263 - regaddr = get_ext_irq_perf_reg(irq);
264 - spin_lock_irqsave(&epic_lock, flags);
265 - reg = bcm_perf_readl(regaddr);
267 - if (BCMCPU_IS_6348())
268 - reg |= EXTIRQ_CFG_MASK_6348(irq % 4);
270 - reg |= EXTIRQ_CFG_MASK(irq % 4);
272 - bcm_perf_writel(reg, regaddr);
273 - spin_unlock_irqrestore(&epic_lock, flags);
275 - if (is_ext_irq_cascaded)
276 - internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start),
280 -static void bcm63xx_external_irq_clear(struct irq_data *d)
282 - unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
284 - unsigned long flags;
286 - regaddr = get_ext_irq_perf_reg(irq);
287 - spin_lock_irqsave(&epic_lock, flags);
288 - reg = bcm_perf_readl(regaddr);
290 - if (BCMCPU_IS_6348())
291 - reg |= EXTIRQ_CFG_CLEAR_6348(irq % 4);
293 - reg |= EXTIRQ_CFG_CLEAR(irq % 4);
295 - bcm_perf_writel(reg, regaddr);
296 - spin_unlock_irqrestore(&epic_lock, flags);
299 -static int bcm63xx_external_irq_set_type(struct irq_data *d,
300 - unsigned int flow_type)
302 - unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
304 - int levelsense, sense, bothedge;
305 - unsigned long flags;
307 - flow_type &= IRQ_TYPE_SENSE_MASK;
309 - if (flow_type == IRQ_TYPE_NONE)
310 - flow_type = IRQ_TYPE_LEVEL_LOW;
312 - levelsense = sense = bothedge = 0;
313 - switch (flow_type) {
314 - case IRQ_TYPE_EDGE_BOTH:
318 - case IRQ_TYPE_EDGE_RISING:
322 - case IRQ_TYPE_EDGE_FALLING:
325 - case IRQ_TYPE_LEVEL_HIGH:
330 - case IRQ_TYPE_LEVEL_LOW:
335 - pr_err("bogus flow type combination given !\n");
339 - regaddr = get_ext_irq_perf_reg(irq);
340 - spin_lock_irqsave(&epic_lock, flags);
341 - reg = bcm_perf_readl(regaddr);
344 - switch (bcm63xx_get_cpu_id()) {
345 - case BCM6348_CPU_ID:
347 - reg |= EXTIRQ_CFG_LEVELSENSE_6348(irq);
349 - reg &= ~EXTIRQ_CFG_LEVELSENSE_6348(irq);
351 - reg |= EXTIRQ_CFG_SENSE_6348(irq);
353 - reg &= ~EXTIRQ_CFG_SENSE_6348(irq);
355 - reg |= EXTIRQ_CFG_BOTHEDGE_6348(irq);
357 - reg &= ~EXTIRQ_CFG_BOTHEDGE_6348(irq);
360 - case BCM3368_CPU_ID:
361 - case BCM6328_CPU_ID:
362 - case BCM6338_CPU_ID:
363 - case BCM6345_CPU_ID:
364 - case BCM6358_CPU_ID:
365 - case BCM6362_CPU_ID:
366 - case BCM6368_CPU_ID:
368 - reg |= EXTIRQ_CFG_LEVELSENSE(irq);
370 - reg &= ~EXTIRQ_CFG_LEVELSENSE(irq);
372 - reg |= EXTIRQ_CFG_SENSE(irq);
374 - reg &= ~EXTIRQ_CFG_SENSE(irq);
376 - reg |= EXTIRQ_CFG_BOTHEDGE(irq);
378 - reg &= ~EXTIRQ_CFG_BOTHEDGE(irq);
384 - bcm_perf_writel(reg, regaddr);
385 - spin_unlock_irqrestore(&epic_lock, flags);
387 - irqd_set_trigger_type(d, flow_type);
388 - if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
389 - irq_set_handler_locked(d, handle_level_irq);
391 - irq_set_handler_locked(d, handle_edge_irq);
393 - return IRQ_SET_MASK_OK_NOCOPY;
397 -static int bcm63xx_internal_set_affinity(struct irq_data *data,
398 - const struct cpumask *dest,
401 - if (!irqd_irq_disabled(data))
402 - internal_irq_unmask(data, dest);
408 -static struct irq_chip bcm63xx_internal_irq_chip = {
409 - .name = "bcm63xx_ipic",
410 - .irq_mask = bcm63xx_internal_irq_mask,
411 - .irq_unmask = bcm63xx_internal_irq_unmask,
414 -static struct irq_chip bcm63xx_external_irq_chip = {
415 - .name = "bcm63xx_epic",
416 - .irq_ack = bcm63xx_external_irq_clear,
418 - .irq_mask = bcm63xx_external_irq_mask,
419 - .irq_unmask = bcm63xx_external_irq_unmask,
421 - .irq_set_type = bcm63xx_external_irq_set_type,
424 -static void bcm63xx_init_irq(void)
425 +void __init arch_init_irq(void)
429 - irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
430 - irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
431 - irq_stat_addr[1] = bcm63xx_regset_address(RSET_PERF);
432 - irq_mask_addr[1] = bcm63xx_regset_address(RSET_PERF);
433 + void __iomem *periph_bases[2];
434 + void __iomem *ext_intc_bases[2];
435 + int periph_irq_count, periph_width, ext_irq_count, ext_shift;
436 + int periph_irqs[2] = { 2, 3 };
439 + periph_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
440 + periph_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
441 + ext_intc_bases[0] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
442 + ext_intc_bases[1] = (void __iomem *)bcm63xx_regset_address(RSET_PERF);
444 switch (bcm63xx_get_cpu_id()) {
446 - irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
447 - irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
448 - irq_stat_addr[1] = 0;
449 - irq_mask_addr[1] = 0;
452 - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
453 + periph_bases[0] += PERF_IRQMASK_3368_REG;
454 + periph_irq_count = 1;
457 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_3368;
459 + ext_irqs[0] = BCM_3368_EXT_IRQ0;
460 + ext_irqs[1] = BCM_3368_EXT_IRQ1;
461 + ext_irqs[2] = BCM_3368_EXT_IRQ2;
462 + ext_irqs[3] = BCM_3368_EXT_IRQ3;
466 - irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
467 - irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
468 - irq_stat_addr[1] += PERF_IRQSTAT_6328_REG(1);
469 - irq_mask_addr[1] += PERF_IRQMASK_6328_REG(1);
472 - is_ext_irq_cascaded = 1;
473 - ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
474 - ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
475 - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
476 + periph_bases[0] += PERF_IRQMASK_6328_REG(0);
477 + periph_bases[1] += PERF_IRQMASK_6328_REG(1);
478 + periph_irq_count = 2;
481 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6328;
483 + ext_irqs[0] = BCM_6328_EXT_IRQ0;
484 + ext_irqs[1] = BCM_6328_EXT_IRQ1;
485 + ext_irqs[2] = BCM_6328_EXT_IRQ2;
486 + ext_irqs[3] = BCM_6328_EXT_IRQ3;
490 - irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
491 - irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
492 - irq_stat_addr[1] = 0;
493 - irq_mask_addr[1] = 0;
496 - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
497 + periph_bases[0] += PERF_IRQMASK_6338_REG;
498 + periph_irq_count = 1;
501 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6338;
510 - irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
511 - irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
512 - irq_stat_addr[1] = 0;
513 - irq_mask_addr[1] = 0;
516 - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
517 + periph_bases[0] += PERF_IRQMASK_6345_REG;
518 + periph_irq_count = 1;
521 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6345;
530 - irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
531 - irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
532 - irq_stat_addr[1] = 0;
533 - irq_mask_addr[1] = 0;
536 - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
537 + periph_bases[0] += PERF_IRQMASK_6348_REG;
538 + periph_irq_count = 1;
541 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6348;
550 - irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
551 - irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
552 - irq_stat_addr[1] += PERF_IRQSTAT_6358_REG(1);
553 - irq_mask_addr[1] += PERF_IRQMASK_6358_REG(1);
556 - is_ext_irq_cascaded = 1;
557 - ext_irq_start = BCM_6358_EXT_IRQ0 - IRQ_INTERNAL_BASE;
558 - ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
559 - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
560 + periph_bases[0] += PERF_IRQMASK_6358_REG(0);
561 + periph_bases[1] += PERF_IRQMASK_6358_REG(1);
562 + periph_irq_count = 2;
565 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6358;
567 + ext_irqs[0] = BCM_6358_EXT_IRQ0;
568 + ext_irqs[1] = BCM_6358_EXT_IRQ1;
569 + ext_irqs[2] = BCM_6358_EXT_IRQ2;
570 + ext_irqs[3] = BCM_6358_EXT_IRQ3;
574 - irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
575 - irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
576 - irq_stat_addr[1] += PERF_IRQSTAT_6362_REG(1);
577 - irq_mask_addr[1] += PERF_IRQMASK_6362_REG(1);
580 - is_ext_irq_cascaded = 1;
581 - ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
582 - ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
583 - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
584 + periph_bases[0] += PERF_IRQMASK_6362_REG(0);
585 + periph_bases[1] += PERF_IRQMASK_6362_REG(1);
586 + periph_irq_count = 2;
589 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6362;
591 + ext_irqs[0] = BCM_6362_EXT_IRQ0;
592 + ext_irqs[1] = BCM_6362_EXT_IRQ1;
593 + ext_irqs[2] = BCM_6362_EXT_IRQ2;
594 + ext_irqs[3] = BCM_6362_EXT_IRQ3;
598 - irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
599 - irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
600 - irq_stat_addr[1] += PERF_IRQSTAT_6368_REG(1);
601 - irq_mask_addr[1] += PERF_IRQMASK_6368_REG(1);
604 - is_ext_irq_cascaded = 1;
605 - ext_irq_start = BCM_6368_EXT_IRQ0 - IRQ_INTERNAL_BASE;
606 - ext_irq_end = BCM_6368_EXT_IRQ5 - IRQ_INTERNAL_BASE;
607 - ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6368;
608 - ext_irq_cfg_reg2 = PERF_EXTIRQ_CFG_REG2_6368;
609 + periph_bases[0] += PERF_IRQMASK_6368_REG(0);
610 + periph_bases[1] += PERF_IRQMASK_6368_REG(1);
611 + periph_irq_count = 2;
614 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_6368;
615 + ext_intc_bases[1] += PERF_EXTIRQ_CFG_REG2_6368;
617 + ext_irqs[0] = BCM_6368_EXT_IRQ0;
618 + ext_irqs[1] = BCM_6368_EXT_IRQ1;
619 + ext_irqs[2] = BCM_6368_EXT_IRQ2;
620 + ext_irqs[3] = BCM_6368_EXT_IRQ3;
621 + ext_irqs[4] = BCM_6368_EXT_IRQ4;
622 + ext_irqs[5] = BCM_6368_EXT_IRQ5;
629 - if (irq_bits == 32) {
630 - dispatch_internal = __dispatch_internal_32;
631 - internal_irq_mask = __internal_irq_mask_32;
632 - internal_irq_unmask = __internal_irq_unmask_32;
634 - dispatch_internal = __dispatch_internal_64;
635 - internal_irq_mask = __internal_irq_mask_64;
636 - internal_irq_unmask = __internal_irq_unmask_64;
640 -void __init arch_init_irq(void)
644 - bcm63xx_init_irq();
646 - for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
647 - irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
650 - for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
651 - irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
654 - if (!is_ext_irq_cascaded) {
655 - for (i = 3; i < 3 + ext_irq_count; ++i) {
656 - irq = MIPS_CPU_IRQ_BASE + i;
657 - if (request_irq(irq, no_action, IRQF_NO_THREAD,
658 - "cascade_extirq", NULL)) {
659 - pr_err("Failed to request irq %d (cascade_extirq)\n",
665 - irq = MIPS_CPU_IRQ_BASE + 2;
666 - if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade_ip2", NULL))
667 - pr_err("Failed to request irq %d (cascade_ip2)\n", irq);
669 - if (is_ext_irq_cascaded) {
670 - irq = MIPS_CPU_IRQ_BASE + 3;
671 - if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade_ip3",
673 - pr_err("Failed to request irq %d (cascade_ip3)\n", irq);
674 - bcm63xx_internal_irq_chip.irq_set_affinity =
675 - bcm63xx_internal_set_affinity;
677 - cpumask_clear(irq_default_affinity);
678 - cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
681 + bcm6345_periph_intc_init(periph_irq_count, periph_irqs, periph_bases,
683 + bcm6345_ext_intc_init(4, ext_irqs, ext_intc_bases[0], ext_shift);
684 + if (ext_irq_count > 4)
685 + bcm6345_ext_intc_init(2, &ext_irqs[4], ext_intc_bases[1],