1 --- a/arch/mips/bcm63xx/clk.c
2 +++ b/arch/mips/bcm63xx/clk.c
3 @@ -258,6 +258,8 @@ static struct clk clk_pcm = {
5 static void usbh_set(struct clk *clk, int enable)
9 if (BCMCPU_IS_6318()) {
10 bcm_hwclock_set(CKCTL_6318_USB_EN, enable);
11 bcm_ub_hwclock_set(UB_CKCTL_6318_USB_EN, enable);
12 @@ -265,13 +267,19 @@ static void usbh_set(struct clk *clk, in
13 bcm_hwclock_set(CKCTL_6328_USBH_EN, enable);
14 } else if (BCMCPU_IS_6348()) {
15 bcm_hwclock_set(CKCTL_6348_USBH_EN, enable);
16 + } else if (BCMCPU_IS_6358()) {
17 + /* power cycle the USB PLL */
18 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL_6358_REG);
19 + reg &= ~USBH_PRIV_PLL_CTRL_6358_EN;
20 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL_6358_REG);
22 + reg |= USBH_PRIV_PLL_CTRL_6358_EN;
23 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL_6358_REG);
24 } else if (BCMCPU_IS_6362()) {
25 bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
26 } else if (BCMCPU_IS_6368()) {
27 bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
28 } else if (BCMCPU_IS_63268()) {
31 bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
32 bcm_misc_iddq_set(IDDQ_CTRL_63268_USBH, enable);
33 bcm63xx_core_set_reset(BCM63XX_RESET_USBH, !enable);
34 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
35 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
36 @@ -1043,9 +1043,11 @@
37 #define USBH_PRIV_SETUP_IPP_MASK (1 << USBH_PRIV_SETUP_IPP_SHIFT)
39 #define USBH_PRIV_SETUP_6318_REG 0x00
40 +#define USBH_PRIV_PLL_CTRL_6358_REG 0x0c
41 #define USBH_PRIV_PLL_CTRL1_6368_REG 0x18
42 #define USBH_PRIV_PLL_CTRL1_6318_REG 0x04
44 +#define USBH_PRIV_PLL_CTRL_6358_EN (1 << 25)
45 #define USBH_PRIV_PLL_CTRL1_6318_SUSP_EN (1 << 27)
46 #define USBH_PRIV_PLL_CTRL1_6318_IDDQ_PWRDN (1 << 31)
47 #define USBH_PRIV_PLL_CTRL1_63268_IDDQ_PWRDN (1 << 9)