1 From cf908990d4a8ccdb73ee4484aa8cadad379ca314 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sun, 30 Nov 2014 14:54:27 +0100
4 Subject: [PATCH 2/5] irqchip: add support for bcm6345-style external
7 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
9 .../interrupt-controller/brcm,bcm6345-ext-intc.txt | 29 ++
10 drivers/irqchip/Kconfig | 4 +
11 drivers/irqchip/Makefile | 1 +
12 drivers/irqchip/irq-bcm6345-ext.c | 287 ++++++++++++++++++++
13 include/linux/irqchip/irq-bcm6345-ext.h | 14 +
14 5 files changed, 335 insertions(+)
15 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
16 create mode 100644 drivers/irqchip/irq-bcm6345-ext.c
17 create mode 100644 include/linux/irqchip/irq-bcm6345-ext.h
20 +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-ext-intc.txt
22 +Broadcom BCM6345-style external interrupt controller
26 +- compatible: Should be "brcm,bcm6345-ext-intc" or "brcm,bcm6318-ext-intc".
27 +- reg: Specifies the base physical addresses and size of the registers.
28 +- interrupt-controller: identifies the node as an interrupt controller.
29 +- #interrupt-cells: Specifies the number of cells needed to encode an interrupt
30 + source, Should be 2.
31 +- interrupt-parent: Specifies the phandle to the parent interrupt controller
32 + this one is cascaded from.
33 +- interrupts: Specifies the interrupt line(s) in the interrupt-parent controller
34 + node, valid values depend on the type of parent interrupt controller.
38 +- brcm,field-width: Size of each field (mask, clear, sense, ...) in bits in the
39 + register. Defaults to 4.
43 +ext_intc: interrupt-controller@10000018 {
44 + compatible = "brcm,bcm6345-ext-intc";
45 + interrupt-parent = <&periph_intc>;
46 + #interrupt-cells = <2>;
47 + reg = <0x10000018 0x4>;
48 + interrupt-controller;
49 + interrupts = <24>, <25>, <26>, <27>;
51 --- a/drivers/irqchip/Kconfig
52 +++ b/drivers/irqchip/Kconfig
53 @@ -129,6 +129,10 @@ config BRCMSTB_L2_IRQ
54 select GENERIC_IRQ_CHIP
57 +config BCM6345_EXT_IRQ
61 config BCM6345_PERIPH_IRQ
64 --- a/drivers/irqchip/Makefile
65 +++ b/drivers/irqchip/Makefile
66 @@ -14,6 +14,7 @@ obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
67 obj-$(CONFIG_IRQ_MXS) += irq-mxs.o
68 obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
69 obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
70 +obj-$(CONFIG_BCM6345_EXT_IRQ) += irq-bcm6345-ext.o
71 obj-$(CONFIG_BCM6345_PERIPH_IRQ) += irq-bcm6345-periph.o
72 obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
73 obj-$(CONFIG_CLPS711X_IRQCHIP) += irq-clps711x.o
75 +++ b/drivers/irqchip/irq-bcm6345-ext.c
78 + * This file is subject to the terms and conditions of the GNU General Public
79 + * License. See the file "COPYING" in the main directory of this archive
82 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
85 +#include <linux/ioport.h>
86 +#include <linux/irq.h>
87 +#include <linux/irqchip.h>
88 +#include <linux/irqchip/chained_irq.h>
89 +#include <linux/irqchip/irq-bcm6345-ext.h>
90 +#include <linux/kernel.h>
91 +#include <linux/of.h>
92 +#include <linux/of_irq.h>
93 +#include <linux/of_address.h>
94 +#include <linux/slab.h>
95 +#include <linux/spinlock.h>
97 +#ifdef CONFIG_BCM63XX
98 +#include <asm/mach-bcm63xx/bcm63xx_irq.h>
100 +#define VIRQ_BASE IRQ_EXTERNAL_BASE
107 +#define EXTIRQ_CFG_SENSE 0
108 +#define EXTIRQ_CFG_STAT 1
109 +#define EXTIRQ_CFG_CLEAR 2
110 +#define EXTIRQ_CFG_MASK 3
111 +#define EXTIRQ_CFG_BOTHEDGE 4
112 +#define EXTIRQ_CFG_LEVELSENSE 5
115 + struct irq_chip chip;
116 + struct irq_domain *domain;
117 + raw_spinlock_t lock;
119 + int parent_irq[MAX_IRQS];
122 + unsigned int toggle_clear_on_ack:1;
125 +static void bcm6345_ext_intc_irq_handle(struct irq_desc *desc)
127 + struct intc_data *data = irq_desc_get_handler_data(desc);
128 + struct irq_chip *chip = irq_desc_get_chip(desc);
129 + unsigned int irq = irq_desc_get_irq(desc);
132 + chained_irq_enter(chip, desc);
134 + for (idx = 0; idx < MAX_IRQS; idx++) {
135 + if (data->parent_irq[idx] != irq)
138 + generic_handle_irq(irq_find_mapping(data->domain, idx));
141 + chained_irq_exit(chip, desc);
144 +static void bcm6345_ext_intc_irq_ack(struct irq_data *data)
146 + struct intc_data *priv = data->domain->host_data;
147 + irq_hw_number_t hwirq = irqd_to_hwirq(data);
150 + raw_spin_lock(&priv->lock);
151 + reg = __raw_readl(priv->reg);
152 + __raw_writel(reg | (1 << (hwirq + EXTIRQ_CFG_CLEAR * priv->shift)),
154 + if (priv->toggle_clear_on_ack)
155 + __raw_writel(reg, priv->reg);
156 + raw_spin_unlock(&priv->lock);
159 +static void bcm6345_ext_intc_irq_mask(struct irq_data *data)
161 + struct intc_data *priv = data->domain->host_data;
162 + irq_hw_number_t hwirq = irqd_to_hwirq(data);
165 + raw_spin_lock(&priv->lock);
166 + reg = __raw_readl(priv->reg);
167 + reg &= ~(1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift));
168 + __raw_writel(reg, priv->reg);
169 + raw_spin_unlock(&priv->lock);
172 +static void bcm6345_ext_intc_irq_unmask(struct irq_data *data)
174 + struct intc_data *priv = data->domain->host_data;
175 + irq_hw_number_t hwirq = irqd_to_hwirq(data);
178 + raw_spin_lock(&priv->lock);
179 + reg = __raw_readl(priv->reg);
180 + reg |= 1 << (hwirq + EXTIRQ_CFG_MASK * priv->shift);
181 + __raw_writel(reg, priv->reg);
182 + raw_spin_unlock(&priv->lock);
185 +static int bcm6345_ext_intc_set_type(struct irq_data *data,
186 + unsigned int flow_type)
188 + struct intc_data *priv = data->domain->host_data;
189 + irq_hw_number_t hwirq = irqd_to_hwirq(data);
190 + bool levelsense = 0, sense = 0, bothedge = 0;
193 + flow_type &= IRQ_TYPE_SENSE_MASK;
195 + if (flow_type == IRQ_TYPE_NONE)
196 + flow_type = IRQ_TYPE_LEVEL_LOW;
198 + switch (flow_type) {
199 + case IRQ_TYPE_EDGE_BOTH:
203 + case IRQ_TYPE_EDGE_RISING:
207 + case IRQ_TYPE_EDGE_FALLING:
210 + case IRQ_TYPE_LEVEL_HIGH:
215 + case IRQ_TYPE_LEVEL_LOW:
220 + pr_err("bogus flow type combination given!\n");
224 + raw_spin_lock(&priv->lock);
225 + reg = __raw_readl(priv->reg);
228 + reg |= 1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift);
230 + reg &= ~(1 << (hwirq + EXTIRQ_CFG_LEVELSENSE * priv->shift));
232 + reg |= 1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift);
234 + reg &= ~(1 << (hwirq + EXTIRQ_CFG_SENSE * priv->shift));
236 + reg |= 1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift);
238 + reg &= ~(1 << (hwirq + EXTIRQ_CFG_BOTHEDGE * priv->shift));
240 + __raw_writel(reg, priv->reg);
241 + raw_spin_unlock(&priv->lock);
243 + irqd_set_trigger_type(data, flow_type);
244 + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
245 + irq_set_handler_locked(data, handle_level_irq);
247 + irq_set_handler_locked(data, handle_edge_irq);
252 +static int bcm6345_ext_intc_map(struct irq_domain *d, unsigned int irq,
253 + irq_hw_number_t hw)
255 + struct intc_data *priv = d->host_data;
257 + irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
262 +static const struct irq_domain_ops bcm6345_ext_domain_ops = {
263 + .xlate = irq_domain_xlate_twocell,
264 + .map = bcm6345_ext_intc_map,
267 +static int __init __bcm6345_ext_intc_init(struct device_node *node,
268 + int num_irqs, int *irqs,
269 + void __iomem *reg, int shift,
270 + bool toggle_clear_on_ack)
272 + struct intc_data *data;
274 + int start = VIRQ_BASE;
276 + data = kzalloc(sizeof(*data), GFP_KERNEL);
280 + raw_spin_lock_init(&data->lock);
282 + for (i = 0; i < num_irqs; i++) {
283 + data->parent_irq[i] = irqs[i];
285 + irq_set_handler_data(irqs[i], data);
286 + irq_set_chained_handler(irqs[i], bcm6345_ext_intc_irq_handle);
290 + data->shift = shift;
291 + data->toggle_clear_on_ack = toggle_clear_on_ack;
293 + data->chip.name = "bcm6345-ext-intc";
294 + data->chip.irq_ack = bcm6345_ext_intc_irq_ack;
295 + data->chip.irq_mask = bcm6345_ext_intc_irq_mask;
296 + data->chip.irq_unmask = bcm6345_ext_intc_irq_unmask;
297 + data->chip.irq_set_type = bcm6345_ext_intc_set_type;
300 + * If we have less than 4 irqs, this is the second controller on
301 + * bcm63xx. So increase the VIRQ start to not overlap with the first
302 + * one, but only do so if we actually use a non-zero start.
304 + * This can be removed when bcm63xx has no legacy users anymore.
306 + if (start && num_irqs < 4)
309 + data->domain = irq_domain_add_simple(node, num_irqs, start,
310 + &bcm6345_ext_domain_ops, data);
311 + if (!data->domain) {
319 +void __init bcm6345_ext_intc_init(int num_irqs, int *irqs, void __iomem *reg,
322 + __bcm6345_ext_intc_init(NULL, num_irqs, irqs, reg, shift, false);
326 +static int __init bcm6345_ext_intc_of_init(struct device_node *node,
327 + struct device_node *parent)
329 + int num_irqs, ret = -EINVAL;
331 + void __iomem *base;
332 + int irqs[MAX_IRQS] = { 0 };
334 + bool toggle_clear_on_ack = false;
336 + num_irqs = of_irq_count(node);
338 + if (!num_irqs || num_irqs > MAX_IRQS)
341 + if (of_property_read_u32(node, "brcm,field-width", &shift))
344 + /* on BCM6318 setting CLEAR seems to continuously mask interrupts */
345 + if (of_device_is_compatible(node, "brcm,bcm6318-ext-intc"))
346 + toggle_clear_on_ack = true;
348 + for (i = 0; i < num_irqs; i++) {
349 + irqs[i] = irq_of_parse_and_map(node, i);
356 + base = of_iomap(node, 0);
360 + ret = __bcm6345_ext_intc_init(node, num_irqs, irqs, base, shift,
361 + toggle_clear_on_ack);
367 + for (i = 0; i < num_irqs; i++)
368 + irq_dispose_mapping(irqs[i]);
373 +IRQCHIP_DECLARE(bcm6318_ext_intc, "brcm,bcm6318-ext-intc",
374 + bcm6345_ext_intc_of_init);
375 +IRQCHIP_DECLARE(bcm6345_ext_intc, "brcm,bcm6345-ext-intc",
376 + bcm6345_ext_intc_of_init);
379 +++ b/include/linux/irqchip/irq-bcm6345-ext.h
382 + * This file is subject to the terms and conditions of the GNU General Public
383 + * License. See the file "COPYING" in the main directory of this archive
384 + * for more details.
386 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
389 +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
390 +#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H
392 +void bcm6345_ext_intc_init(int n_irqs, int *irqs, void __iomem *reg, int shift);
394 +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_EXT_H */