1 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
2 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
4 #include <linux/kernel.h>
5 #include <linux/string.h>
6 #include <linux/pci_ids.h>
7 +#include <linux/platform_data/b53.h>
8 +#include <linux/spi/spi.h>
9 #include <asm/addrspace.h>
10 #include <bcm63xx_board.h>
11 #include <bcm63xx_cpu.h>
12 @@ -1898,6 +1900,648 @@ static struct board_info __initdata boar
13 #endif /* CONFIG_BCM63XX_CPU_6362 */
18 +#ifdef CONFIG_BCM63XX_CPU_6368
19 +static struct board_info __initdata board_96368mvngr = {
20 + .name = "96368MVNgr",
21 + .expected_cpu_id = 0x6368,
54 +static struct board_info __initdata board_96368mvwg = {
55 + .name = "96368MVWG",
56 + .expected_cpu_id = 0x6368,
95 +static struct board_info __initdata board_AV4202N = {
96 + .name = "96368_Swiss_S1",
97 + .expected_cpu_id = 0x6368,
102 + .num_usbh_ports = 2,
130 + .use_fallback_sprom = 1,
131 + .fallback_sprom = {
132 + .type = SPROM_BCM4322,
138 +static struct board_info __initdata board_DGND3700v1_3800B = {
139 + .name = "DGND3700v1_3800B",
140 + .expected_cpu_id = 0x6368,
145 + .num_usbh_ports = 2,
154 + .force_speed = 1000,
155 + .force_duplex_full = 1,
162 +static struct sprom_fixup __initdata EVG2000_fixups[] = {
163 + { .offset = 219, .value = 0xec08 },
166 +static struct board_info __initdata board_EVG2000 = {
167 + .name = "96369PVG",
168 + .expected_cpu_id = 0x6368,
173 + .num_usbh_ports = 2,
182 + .force_speed = 1000,
183 + .force_duplex_full = 1,
189 + .use_fallback_sprom = 1,
190 + .fallback_sprom = {
191 + .type = SPROM_BCM4322,
194 + .board_fixups = EVG2000_fixups,
195 + .num_board_fixups = ARRAY_SIZE(EVG2000_fixups),
199 +static struct board_info __initdata board_HG622 = {
200 + .name = "96368MVWG_hg622",
201 + .expected_cpu_id = 0x6368,
206 + .num_usbh_ports = 2,
211 + .vendor = PCI_VENDOR_ID_RALINK,
212 + .caldata_offset = 0xfa0000,
214 + .eeprom = "rt2x00.eeprom",
245 +static struct board_info __initdata board_HG655b = {
247 + .expected_cpu_id = 0x6368,
252 + .num_usbh_ports = 2,
257 + .vendor = PCI_VENDOR_ID_RALINK,
258 + .caldata_offset = 0x7c0000,
260 + .eeprom = "rt2x00.eeprom",
291 +static struct board_info __initdata board_P870HW51A_V2 = {
292 + .name = "P870HW-51a_v2",
293 + .expected_cpu_id = 0x6368,
325 + .use_fallback_sprom = 1,
326 + .fallback_sprom = {
327 + .type = SPROM_BCM4318,
333 +static struct board_info __initdata board_R1000H = {
335 + .expected_cpu_id = 0x6368,
348 + .force_speed = 1000,
349 + .force_duplex_full = 1,
356 +static struct sprom_fixup __initdata vh4032n_fixups[] = {
357 + { .offset = 2, .value = 0x04d2 },
358 + { .offset = 4, .value = 0x4350 },
359 + { .offset = 65, .value = 0x1300 },
360 + { .offset = 68, .value = 0x0402 },
361 + { .offset = 70, .value = 0x0090 },
362 + { .offset = 71, .value = 0x4c19 },
363 + { .offset = 72, .value = 0x2345 },
364 + { .offset = 87, .value = 0x0315 },
365 + { .offset = 88, .value = 0x0315 },
366 + { .offset = 96, .value = 0x2048 },
367 + { .offset = 97, .value = 0xfed7 },
368 + { .offset = 98, .value = 0x15a6 },
369 + { .offset = 99, .value = 0xfaee },
370 + { .offset = 100, .value = 0x3e3a },
371 + { .offset = 101, .value = 0x3a36 },
372 + { .offset = 102, .value = 0xff7f },
373 + { .offset = 103, .value = 0x11b9 },
374 + { .offset = 104, .value = 0xfc53 },
375 + { .offset = 105, .value = 0xffe6 },
376 + { .offset = 106, .value = 0xfdd2 },
377 + { .offset = 107, .value = 0xfe49 },
378 + { .offset = 108, .value = 0xff6a },
379 + { .offset = 109, .value = 0x136e },
380 + { .offset = 110, .value = 0xfbed },
381 + { .offset = 111, .value = 0x0000 },
382 + { .offset = 112, .value = 0x2048 },
383 + { .offset = 113, .value = 0xfee2 },
384 + { .offset = 114, .value = 0x15e5 },
385 + { .offset = 115, .value = 0xfaed },
386 + { .offset = 116, .value = 0x3e3a },
387 + { .offset = 117, .value = 0x3a36 },
388 + { .offset = 118, .value = 0xffc8 },
389 + { .offset = 119, .value = 0x12b8 },
390 + { .offset = 120, .value = 0xfca1 },
391 + { .offset = 121, .value = 0xff9b },
392 + { .offset = 122, .value = 0x122a },
393 + { .offset = 123, .value = 0xfcc8 },
394 + { .offset = 124, .value = 0xff95 },
395 + { .offset = 125, .value = 0x146b },
396 + { .offset = 126, .value = 0xfbba },
397 + { .offset = 127, .value = 0x0000 },
398 + { .offset = 161, .value = 0x0000 },
399 + { .offset = 162, .value = 0x0000 },
400 + { .offset = 169, .value = 0x0000 },
401 + { .offset = 170, .value = 0x0000 },
402 + { .offset = 171, .value = 0x0000 },
403 + { .offset = 172, .value = 0x0000 },
404 + { .offset = 173, .value = 0x0000 },
405 + { .offset = 174, .value = 0x0000 },
406 + { .offset = 175, .value = 0x0000 },
407 + { .offset = 176, .value = 0x0000 },
408 + { .offset = 219, .value = 0x1108 },
411 +static struct board_info __initdata board_VH4032N = {
413 + .expected_cpu_id = 0x6368,
418 + .num_usbh_ports = 2,
446 + .use_fallback_sprom = 1,
447 + .fallback_sprom = {
448 + .type = SPROM_BCM43222,
451 + .board_fixups = vh4032n_fixups,
452 + .num_board_fixups = ARRAY_SIZE(vh4032n_fixups),
456 +static struct sprom_fixup __initdata vr3025u_fixups[] = {
457 + { .offset = 97, .value = 0xfeb3 },
458 + { .offset = 98, .value = 0x1618 },
459 + { .offset = 99, .value = 0xfab0 },
460 + { .offset = 113, .value = 0xfed1 },
461 + { .offset = 114, .value = 0x1609 },
462 + { .offset = 115, .value = 0xfad9 },
465 +static struct board_info __initdata board_VR3025u = {
466 + .name = "96368M-1541N",
467 + .expected_cpu_id = 0x6368,
499 + .use_fallback_sprom = 1,
500 + .fallback_sprom = {
501 + .type = SPROM_BCM43222,
504 + .board_fixups = vr3025u_fixups,
505 + .num_board_fixups = ARRAY_SIZE(vr3025u_fixups),
509 +static struct sprom_fixup __initdata vr3025un_fixups[] = {
510 + { .offset = 97, .value = 0xfeb3 },
511 + { .offset = 98, .value = 0x1618 },
512 + { .offset = 99, .value = 0xfab0 },
513 + { .offset = 113, .value = 0xfed1 },
514 + { .offset = 114, .value = 0x1609 },
515 + { .offset = 115, .value = 0xfad9 },
518 +static struct board_info __initdata board_VR3025un = {
519 + .name = "96368M-1341N",
520 + .expected_cpu_id = 0x6368,
552 + .use_fallback_sprom = 1,
553 + .fallback_sprom = {
554 + .type = SPROM_BCM43222,
557 + .board_fixups = vr3025un_fixups,
558 + .num_board_fixups = ARRAY_SIZE(vr3025un_fixups),
562 +static struct sprom_fixup __initdata vr3026e_fixups[] = {
563 + { .offset = 97, .value = 0xfeb3 },
564 + { .offset = 98, .value = 0x1618 },
565 + { .offset = 99, .value = 0xfab0 },
566 + { .offset = 113, .value = 0xfed1 },
567 + { .offset = 114, .value = 0x1609 },
568 + { .offset = 115, .value = 0xfad9 },
571 +static struct board_info __initdata board_VR3026e = {
572 + .name = "96368MT-1341N1",
573 + .expected_cpu_id = 0x6368,
605 + .use_fallback_sprom = 1,
606 + .fallback_sprom = {
607 + .type = SPROM_BCM43222,
610 + .board_fixups = vr3026e_fixups,
611 + .num_board_fixups = ARRAY_SIZE(vr3026e_fixups),
615 +static struct sprom_fixup __initdata wap5813n_fixups[] = {
616 + { .offset = 97, .value = 0xfeed },
617 + { .offset = 98, .value = 0x15d1 },
618 + { .offset = 99, .value = 0xfb0d },
619 + { .offset = 113, .value = 0xfef7 },
620 + { .offset = 114, .value = 0x15f7 },
621 + { .offset = 115, .value = 0xfb1a },
624 +static struct board_info __initdata board_WAP5813n = {
625 + .name = "96369R-1231N",
626 + .expected_cpu_id = 0x6368,
639 + .force_speed = 1000,
640 + .force_duplex_full = 1,
646 + .use_fallback_sprom = 1,
647 + .fallback_sprom = {
648 + .type = SPROM_BCM43222,
651 + .board_fixups = wap5813n_fixups,
652 + .num_board_fixups = ARRAY_SIZE(wap5813n_fixups),
655 +#endif /* CONFIG_BCM63XX_CPU_6368 */
660 static const struct board_info __initconst *bcm963xx_boards[] = {
661 @@ -1982,6 +2626,22 @@ static const struct board_info __initcon
664 #endif /* CONFIG_BCM63XX_CPU_6362 */
665 +#ifdef CONFIG_BCM63XX_CPU_6368
669 + &board_DGND3700v1_3800B,
673 + &board_P870HW51A_V2,
680 +#endif /* CONFIG_BCM63XX_CPU_6368 */
683 static struct of_device_id const bcm963xx_boards_dt[] = {
684 @@ -2078,6 +2738,20 @@ static struct of_device_id const bcm963x
685 { .compatible = "sfr,neufbox-6-sercomm-r0", .data = &board_nb6, },
686 #endif /* CONFIG_BCM63XX_CPU_6362 */
687 #ifdef CONFIG_BCM63XX_CPU_6368
688 + { .compatible = "actiontec,r1000h", .data = &board_R1000H, },
689 + { .compatible = "adb,av4202n", .data = &board_AV4202N, },
690 + { .compatible = "brcm,bcm96368mvngr", .data = &board_96368mvngr, },
691 + { .compatible = "brcm,bcm96368mvwg", .data = &board_96368mvwg, },
692 + { .compatible = "comtrend,vr-3025u", .data = &board_VR3025u, },
693 + { .compatible = "comtrend,vr-3025un", .data = &board_VR3025un, },
694 + { .compatible = "comtrend,vr-3026e", .data = &board_VR3026e, },
695 + { .compatible = "comtrend,wap-5813n", .data = &board_WAP5813n, },
696 + { .compatible = "huawei,echolife-hg622", .data = &board_HG622, },
697 + { .compatible = "huawei,echolife-hg655b", .data = &board_HG655b, },
698 + { .compatible = "netgear,dgnd3700-v1", .data = &board_DGND3700v1_3800B, },
699 + { .compatible = "netgear,evg2000", .data = &board_EVG2000, },
700 + { .compatible = "observa,vh4032n", .data = &board_VH4032N, },
701 + { .compatible = "zyxel,p870hw-51a-v2", .data = &board_P870HW51A_V2, },
702 #endif /* CONFIG_BCM63XX_CPU_6368 */
703 #ifdef CONFIG_BCM63XX_CPU_63268
704 #endif /* CONFIG_BCM63XX_CPU_63268 */
705 --- a/arch/mips/bcm63xx/boards/board_common.c
706 +++ b/arch/mips/bcm63xx/boards/board_common.c
707 @@ -81,12 +81,25 @@ void __init board_early_setup(const stru
708 bcm63xx_pci_enabled = 1;
709 if (BCMCPU_IS_6348())
710 val |= GPIO_MODE_6348_G2_PCI;
712 + if (BCMCPU_IS_6368())
713 + val |= GPIO_MODE_6368_PCI_REQ1 |
714 + GPIO_MODE_6368_PCI_GNT1 |
715 + GPIO_MODE_6368_PCI_INTB |
716 + GPIO_MODE_6368_PCI_REQ0 |
717 + GPIO_MODE_6368_PCI_GNT0;
721 if (board.has_pccard) {
722 if (BCMCPU_IS_6348())
723 val |= GPIO_MODE_6348_G1_MII_PCCARD;
725 + if (BCMCPU_IS_6368())
726 + val |= GPIO_MODE_6368_PCMCIA_CD1 |
727 + GPIO_MODE_6368_PCMCIA_CD2 |
728 + GPIO_MODE_6368_PCMCIA_VS1 |
729 + GPIO_MODE_6368_PCMCIA_VS2;
732 if (board.has_enet0 && !board.enet0.use_internal_phy) {