eb012fe243be54ad31dd430912d2c7585cdd0432
[openwrt/staging/dedeckeh.git] / target / linux / bmips / dts / bcm6318.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /dts-v1/;
4
5 #include <dt-bindings/clock/bcm6318-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/bcm6318-interrupt-controller.h>
9 #include <dt-bindings/reset/bcm6318-reset.h>
10 #include <dt-bindings/soc/bcm6318-pm.h>
11
12 / {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 compatible = "brcm,bcm6318";
16
17 aliases {
18 pinctrl = &pinctrl;
19 serial0 = &uart0;
20 spi1 = &hsspi;
21 };
22
23 chosen {
24 bootargs = "earlycon";
25 stdout-path = "serial0:115200n8";
26 };
27
28 clocks {
29 periph_osc: periph-osc {
30 compatible = "fixed-clock";
31
32 #clock-cells = <0>;
33
34 clock-frequency = <50000000>;
35 clock-output-names = "periph";
36 };
37
38 hsspi_osc: hsspi-osc {
39 compatible = "fixed-clock";
40
41 #clock-cells = <0>;
42
43 clock-frequency = <250000000>;
44 clock-output-names = "hsspi_osc";
45 };
46 };
47
48 cpus {
49 #address-cells = <1>;
50 #size-cells = <0>;
51 mips-hpt-frequency = <166500000>;
52
53 cpu@0 {
54 compatible = "brcm,bmips3300", "mips,mips4Kc";
55 device_type = "cpu";
56 reg = <0>;
57 };
58 };
59
60 cpu_intc: interrupt-controller {
61 #address-cells = <0>;
62 compatible = "mti,cpu-interrupt-controller";
63
64 interrupt-controller;
65 #interrupt-cells = <1>;
66 };
67
68 memory@0 {
69 device_type = "memory";
70 reg = <0 0>;
71 };
72
73 ubus {
74 #address-cells = <1>;
75 #size-cells = <1>;
76
77 compatible = "simple-bus";
78 ranges;
79
80 periph_clk: clock-controller@10000004 {
81 compatible = "brcm,bcm6318-clocks";
82 reg = <0x10000004 0x4>;
83 #clock-cells = <1>;
84 };
85
86 ubus_clk: clock-controller@10000008 {
87 compatible = "brcm,bcm6318-ubus-clocks";
88 reg = <0x10000008 0x4>;
89 #clock-cells = <1>;
90 };
91
92 periph_rst: reset-controller@10000010 {
93 compatible = "brcm,bcm6345-reset";
94 reg = <0x10000010 0x4>;
95 #reset-cells = <1>;
96 };
97
98 ext_intc: interrupt-controller@10000018 {
99 #address-cells = <1>;
100 compatible = "brcm,bcm6318-ext-intc";
101 reg = <0x10000018 0x4>;
102
103 interrupt-controller;
104 #interrupt-cells = <2>;
105
106 interrupt-parent = <&periph_intc>;
107 interrupts = <BCM6318_IRQ_EXT0>,
108 <BCM6318_IRQ_EXT1>,
109 <BCM6318_IRQ_EXT2>,
110 <BCM6318_IRQ_EXT3>;
111 };
112
113 periph_intc: interrupt-controller@10000020 {
114 #address-cells = <1>;
115 compatible = "brcm,bcm6345-l1-intc";
116 reg = <0x10000020 0x20>;
117
118 interrupt-controller;
119 #interrupt-cells = <1>;
120
121 interrupt-parent = <&cpu_intc>;
122 interrupts = <2>, <3>;
123 };
124
125 wdt: watchdog@10000068 {
126 compatible = "brcm,bcm7038-wdt";
127 reg = <0x10000068 0xc>;
128
129 clocks = <&periph_osc>;
130
131 timeout-sec = <30>;
132 };
133
134 pll_cntl: syscon@10000074 {
135 compatible = "syscon", "simple-mfd";
136 reg = <0x10000074 0x4>;
137 native-endian;
138
139 syscon-reboot {
140 compatible = "syscon-reboot";
141 offset = <0>;
142 mask = <0x1>;
143 };
144 };
145
146 gpio_cntl: syscon@10000080 {
147 #address-cells = <1>;
148 #size-cells = <1>;
149 compatible = "brcm,bcm6318-gpio-sysctl",
150 "syscon", "simple-mfd";
151 reg = <0x10000080 0x80>;
152 ranges = <0 0x10000080 0x80>;
153 native-endian;
154
155 gpio: gpio@0 {
156 compatible = "brcm,bcm6318-gpio";
157 reg-names = "dirout", "dat";
158 reg = <0x0 0x8>, <0x8 0x8>;
159
160 gpio-controller;
161 gpio-ranges = <&pinctrl 0 0 50>;
162 #gpio-cells = <2>;
163 };
164
165 pinctrl: pinctrl@18 {
166 compatible = "brcm,bcm6318-pinctrl";
167 reg = <0x18 0x10>, <0x54 0x18>;
168
169 pinctrl_ephy0_spd_led: ephy0_spd_led-pins {
170 function = "ephy0_spd_led";
171 pins = "gpio0";
172 };
173
174 pinctrl_ephy1_spd_led: ephy1_spd_led-pins {
175 function = "ephy1_spd_led";
176 pins = "gpio1";
177 };
178
179 pinctrl_ephy2_spd_led: ephy2_spd_led-pins {
180 function = "ephy2_spd_led";
181 pins = "gpio2";
182 };
183
184 pinctrl_ephy3_spd_led: ephy3_spd_led-pins {
185 function = "ephy3_spd_led";
186 pins = "gpio3";
187 };
188
189 pinctrl_ephy0_act_led: ephy0_act_led-pins {
190 function = "ephy0_act_led";
191 pins = "gpio4";
192 };
193
194 pinctrl_ephy1_act_led: ephy1_act_led-pins {
195 function = "ephy1_act_led";
196 pins = "gpio5";
197 };
198
199 pinctrl_ephy2_act_led: ephy2_act_led-pins {
200 function = "ephy2_act_led";
201 pins = "gpio6";
202 };
203
204 pinctrl_ephy3_act_led: ephy3_act_led-pins {
205 function = "ephy3_act_led";
206 pins = "gpio7";
207 };
208
209 pinctrl_serial_led: serial_led-pins {
210 pinctrl_serial_led_data: serial_led_data-pins {
211 function = "serial_led_data";
212 pins = "gpio6";
213 };
214
215 pinctrl_serial_led_clk: serial_led_clk-pins {
216 function = "serial_led_clk";
217 pins = "gpio7";
218 };
219 };
220
221 pinctrl_inet_act_led: inet_act_led-pins {
222 function = "inet_act_led";
223 pins = "gpio8";
224 };
225
226 pinctrl_inet_fail_led: inet_fail_led-pins {
227 function = "inet_fail_led";
228 pins = "gpio9";
229 };
230
231 pinctrl_dsl_led: dsl_led-pins {
232 function = "dsl_led";
233 pins = "gpio10";
234 };
235
236 pinctrl_post_fail_led: post_fail_led-pins {
237 function = "post_fail_led";
238 pins = "gpio11";
239 };
240
241 pinctrl_wlan_wps_led: wlan_wps_led-pins {
242 function = "wlan_wps_led";
243 pins = "gpio12";
244 };
245
246 pinctrl_usb_pwron: usb_pwron-pins {
247 function = "usb_pwron";
248 pins = "gpio13";
249 };
250
251 pinctrl_usb_device_led: usb_device_led-pins {
252 function = "usb_device_led";
253 pins = "gpio13";
254 };
255
256 pinctrl_usb_active: usb_active-pins {
257 function = "usb_active";
258 pins = "gpio40";
259 };
260 };
261 };
262
263 uart0: serial@10000100 {
264 compatible = "brcm,bcm6345-uart";
265 reg = <0x10000100 0x18>;
266
267 interrupt-parent = <&periph_intc>;
268 interrupts = <BCM6318_IRQ_UART0>;
269
270 clocks = <&periph_osc>;
271 clock-names = "periph";
272
273 status = "disabled";
274 };
275
276 leds: led-controller@10000200 {
277 #address-cells = <1>;
278 #size-cells = <0>;
279 compatible = "brcm,bcm6328-leds";
280 reg = <0x10000200 0x24>;
281
282 status = "disabled";
283 };
284
285 periph_pwr: power-controller@100008e8 {
286 compatible = "brcm,bcm6318-power-controller";
287 reg = <0x100008e8 0x4>;
288
289 #power-domain-cells = <1>;
290 };
291
292 hsspi: spi@10003000 {
293 #address-cells = <1>;
294 #size-cells = <0>;
295 compatible = "brcm,bcm6328-hsspi";
296 reg = <0x10003000 0x600>;
297
298 interrupt-parent = <&periph_intc>;
299 interrupts = <BCM6318_IRQ_HSSPI>;
300
301 clocks = <&periph_clk BCM6318_CLK_HSSPI>,
302 <&hsspi_osc>;
303 clock-names = "hsspi",
304 "pll";
305
306 resets = <&periph_rst BCM6318_RST_SPI>;
307
308 status = "disabled";
309 };
310
311 ehci: usb@10005000 {
312 compatible = "brcm,bcm6318-ehci", "generic-ehci";
313 reg = <0x10005000 0x100>;
314 big-endian;
315 spurious-oc;
316
317 interrupt-parent = <&periph_intc>;
318 interrupts = <BCM6318_IRQ_EHCI>;
319
320 phys = <&usbh 0>;
321 phy-names = "usb";
322
323 status = "disabled";
324 };
325
326 ohci: usb@10005100 {
327 compatible = "brcm,bcm6318-ohci", "generic-ohci";
328 reg = <0x10005100 0x100>;
329 big-endian;
330 no-big-frame-no;
331
332 interrupt-parent = <&periph_intc>;
333 interrupts = <BCM6318_IRQ_OHCI>;
334
335 phys = <&usbh 0>;
336 phy-names = "usb";
337
338 status = "disabled";
339 };
340
341 usbh: usb-phy@10005200 {
342 compatible = "brcm,bcm6318-usbh-phy";
343 reg = <0x10005200 0x38>;
344
345 #phy-cells = <1>;
346
347 clocks = <&periph_clk BCM6318_CLK_USBD>,
348 <&ubus_clk BCM6318_UCLK_USB>;
349 clock-names = "usbh",
350 "usb_ref";
351
352 power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_USB>;
353 resets = <&periph_rst BCM6318_RST_USBH>;
354
355 status = "disabled";
356 };
357
358 pcie: pcie@10010000 {
359 compatible = "brcm,bcm6318-pcie";
360 reg = <0x10010000 0x10000>;
361 #address-cells = <3>;
362 #size-cells = <2>;
363
364 device_type = "pci";
365 bus-range = <0x00 0x01>;
366 ranges = <0x2000000 0 0x10200000 0x10200000 0 0x100000>;
367 linux,pci-probe-only = <1>;
368
369 interrupt-parent = <&periph_intc>;
370 interrupts = <BCM6318_IRQ_PCIE_RC>;
371
372 clocks = <&periph_clk BCM6318_CLK_PCIE>,
373 <&periph_clk BCM6318_CLK_PCIE25>,
374 <&ubus_clk BCM6318_UCLK_PCIE>;
375 clock-names = "pcie",
376 "pcie25",
377 "pcie-ubus";
378
379 resets = <&periph_rst BCM6318_RST_PCIE>,
380 <&periph_rst BCM6318_RST_PCIE_EXT>,
381 <&periph_rst BCM6318_RST_PCIE_CORE>,
382 <&periph_rst BCM6318_RST_PCIE_HARD>;
383 reset-names = "pcie",
384 "pcie-ext",
385 "pcie-core",
386 "pcie-hard";
387
388 power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_PCIE>;
389
390 status = "disabled";
391 };
392
393 switch0: switch@10080000 {
394 #address-cells = <1>;
395 #size-cells = <0>;
396 compatible = "brcm,bcm6328-switch";
397 reg = <0x10080000 0x8000>;
398 big-endian;
399
400 ports {
401 #address-cells = <1>;
402 #size-cells = <0>;
403
404 port@8 {
405 reg = <8>;
406
407 phy-mode = "internal";
408 ethernet = <&ethernet>;
409
410 fixed-link {
411 speed = <1000>;
412 full-duplex;
413 };
414 };
415 };
416 };
417
418 mdio: mdio@100800b0 {
419 #address-cells = <1>;
420 #size-cells = <0>;
421 compatible = "brcm,bcm6368-mdio-mux";
422 reg = <0x100800b0 0x8>;
423
424 mdio_int: mdio@0 {
425 #address-cells = <1>;
426 #size-cells = <0>;
427 reg = <0>;
428
429 phy1: ethernet-phy@1 {
430 compatible = "ethernet-phy-ieee802.3-c22";
431 reg = <1>;
432 };
433
434 phy2: ethernet-phy@2 {
435 compatible = "ethernet-phy-ieee802.3-c22";
436 reg = <2>;
437 };
438
439 phy3: ethernet-phy@3 {
440 compatible = "ethernet-phy-ieee802.3-c22";
441 reg = <3>;
442 };
443
444 phy4: ethernet-phy@4 {
445 compatible = "ethernet-phy-ieee802.3-c22";
446 reg = <4>;
447 };
448 };
449
450 mdio_ext: mdio@1 {
451 #address-cells = <1>;
452 #size-cells = <0>;
453 reg = <1>;
454 };
455 };
456
457 ethernet: ethernet@10088000 {
458 compatible = "brcm,bcm6318-enetsw";
459 reg = <0x10088000 0x80>,
460 <0x10088200 0x80>,
461 <0x10088400 0x80>;
462 reg-names = "dma",
463 "dma-channels",
464 "dma-sram";
465
466 interrupt-parent = <&periph_intc>;
467 interrupts = <BCM6318_IRQ_ENETSW_RX_DMA0>,
468 <BCM6318_IRQ_ENETSW_TX_DMA0>;
469 interrupt-names = "rx",
470 "tx";
471
472 clocks = <&periph_clk BCM6318_CLK_ROBOSW250>,
473 <&periph_clk BCM6318_CLK_ROBOSW025>,
474 <&ubus_clk BCM6318_UCLK_ROBOSW>;
475
476 resets = <&periph_rst BCM6318_RST_ENETSW>,
477 <&periph_rst BCM6318_RST_EPHY>;
478
479 power-domains = <&periph_pwr BCM6318_POWER_DOMAIN_EPHY0>,
480 <&periph_pwr BCM6318_POWER_DOMAIN_EPHY1>,
481 <&periph_pwr BCM6318_POWER_DOMAIN_EPHY2>,
482 <&periph_pwr BCM6318_POWER_DOMAIN_EPHY3>;
483
484 dma-rx = <0>;
485 dma-tx = <1>;
486
487 status = "disabled";
488 };
489 };
490 };