1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include <dt-bindings/clock/bcm63268-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>
9 #include <dt-bindings/reset/bcm63268-reset.h>
10 #include <dt-bindings/soc/bcm63268-pm.h>
15 compatible = "brcm,bcm63268";
27 bootargs = "earlycon";
28 stdout-path = "serial0:115200n8";
32 periph_osc: periph-osc {
33 compatible = "fixed-clock";
37 clock-frequency = <50000000>;
38 clock-output-names = "periph";
41 hsspi_osc: hsspi-osc {
42 compatible = "fixed-clock";
46 clock-frequency = <400000000>;
47 clock-output-names = "hsspi_osc";
54 mips-hpt-frequency = <200000000>;
57 compatible = "brcm,bmips4350", "mips,mips4Kc";
63 compatible = "brcm,bmips4350", "mips,mips4Kc";
69 cpu_intc: interrupt-controller {
71 compatible = "mti,cpu-interrupt-controller";
74 #interrupt-cells = <1>;
78 device_type = "memory";
86 compatible = "simple-bus";
89 periph_clk: clock-controller@10000004 {
90 compatible = "brcm,bcm63268-clocks";
91 reg = <0x10000004 0x4>;
95 pll_cntl: syscon@10000008 {
96 compatible = "syscon", "simple-mfd";
97 reg = <0x10000008 0x4>;
101 compatible = "syscon-reboot";
107 periph_rst: reset-controller@10000010 {
108 compatible = "brcm,bcm6345-reset";
109 reg = <0x10000010 0x4>;
113 ext_intc: interrupt-controller@10000018 {
114 #address-cells = <1>;
115 compatible = "brcm,bcm6345-ext-intc";
116 reg = <0x10000018 0x4>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
121 interrupts = <BCM63268_IRQ_EXT0>,
127 periph_intc: interrupt-controller@10000020 {
128 #address-cells = <1>;
129 compatible = "brcm,bcm6345-l1-intc";
130 reg = <0x10000020 0x20>,
133 interrupt-controller;
134 #interrupt-cells = <1>;
136 interrupt-parent = <&cpu_intc>;
137 interrupts = <2>, <3>;
140 wdt: watchdog@1000009c {
141 compatible = "brcm,bcm7038-wdt";
142 reg = <0x1000009c 0xc>;
144 clocks = <&periph_osc>;
149 timer_clk: clock-controller@100000ac {
150 compatible = "brcm,bcm63268-timer-clocks";
151 reg = <0x100000ac 0x4>;
156 gpio_cntl: syscon@100000c0 {
157 compatible = "brcm,bcm63268-gpio-sysctl",
158 "syscon", "simple-mfd";
159 reg = <0x100000c0 0x80>;
160 ranges = <0 0x100000c0 0x80>;
164 compatible = "brcm,bcm63268-gpio";
165 reg-names = "dirout", "dat";
166 reg = <0x0 0x8>, <0x8 0x8>;
169 gpio-ranges = <&pinctrl 0 0 52>;
173 pinctrl: pinctrl@10 {
174 compatible = "brcm,bcm63268-pinctrl";
175 reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
177 pinctrl_serial_led: serial_led-pins {
178 pinctrl_serial_led_clk: serial_led_clk-pins {
179 function = "serial_led_clk";
183 pinctrl_serial_led_data: serial_led_data-pins {
184 function = "serial_led_data";
189 pinctrl_hsspi_cs4: hsspi_cs4-pins {
190 function = "hsspi_cs4";
194 pinctrl_hsspi_cs5: hsspi_cs5-pins {
195 function = "hsspi_cs5";
199 pinctrl_hsspi_cs6: hsspi_cs6-pins {
200 function = "hsspi_cs6";
204 pinctrl_hsspi_cs7: hsspi_cs7-pins {
205 function = "hsspi_cs7";
209 pinctrl_adsl_spi: adsl_spi {
210 pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
211 function = "adsl_spi_miso";
215 pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
216 function = "adsl_spi_mosi";
221 pinctrl_vreq_clk: vreq_clk-pins {
222 function = "vreq_clk";
226 pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
227 function = "pcie_clkreq_b";
231 pinctrl_robosw_led_clk: robosw_led_clk-pins {
232 function = "robosw_led_clk";
236 pinctrl_robosw_led_data: robosw_led_data-pins {
237 function = "robosw_led_data";
241 pinctrl_nand: nand-pins {
246 pinctrl_gpio35_alt: gpio35_alt-pins {
247 function = "gpio35_alt";
251 pinctrl_dectpd: dectpd-pins {
253 group = "dectpd_grp";
256 pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
257 function = "vdsl_phy_override_0";
258 group = "vdsl_phy_override_0_grp";
261 pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
262 function = "vdsl_phy_override_1";
263 group = "vdsl_phy_override_1_grp";
266 pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
267 function = "vdsl_phy_override_2";
268 group = "vdsl_phy_override_2_grp";
271 pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
272 function = "vdsl_phy_override_3";
273 group = "vdsl_phy_override_3_grp";
276 pinctrl_dsl_gpio8: dsl_gpio8-pins {
277 function = "dsl_gpio8";
281 pinctrl_dsl_gpio9: dsl_gpio9-pins {
282 function = "dsl_gpio9";
288 uart0: serial@10000180 {
289 compatible = "brcm,bcm6345-uart";
290 reg = <0x10000180 0x18>;
292 interrupt-parent = <&periph_intc>;
293 interrupts = <BCM63268_IRQ_UART0>;
295 clocks = <&periph_osc>;
296 clock-names = "periph";
301 uart1: serial@100001a0 {
302 compatible = "brcm,bcm6345-uart";
303 reg = <0x100001a0 0x18>;
305 interrupt-parent = <&periph_intc>;
306 interrupts = <BCM63268_IRQ_UART1>;
308 clocks = <&periph_osc>;
309 clock-names = "periph";
314 nflash: nand@10000200 {
315 #address-cells = <1>;
317 compatible = "brcm,nand-bcm6368",
318 "brcm,brcmnand-v4.0",
320 reg = <0x10000200 0x180>,
327 interrupt-parent = <&periph_intc>;
328 interrupts = <BCM63268_IRQ_NAND>;
330 clocks = <&periph_clk BCM63268_CLK_NAND>;
331 clock-names = "nand";
333 pinctrl-names = "default";
334 pinctrl-0 = <&pinctrl_nand>;
339 lsspi: spi@10000800 {
340 #address-cells = <1>;
342 compatible = "brcm,bcm6358-spi";
343 reg = <0x10000800 0x70c>;
345 interrupt-parent = <&periph_intc>;
346 interrupts = <BCM63268_IRQ_LSSPI>;
348 clocks = <&periph_clk BCM63268_CLK_SPI>;
351 resets = <&periph_rst BCM63268_RST_SPI>;
356 hsspi: spi@10001000 {
357 #address-cells = <1>;
359 compatible = "brcm,bcm6328-hsspi";
360 reg = <0x10001000 0x600>;
362 interrupt-parent = <&periph_intc>;
363 interrupts = <BCM63268_IRQ_HSSPI>;
365 clocks = <&periph_clk BCM63268_CLK_HSSPI>,
367 clock-names = "hsspi",
370 resets = <&periph_rst BCM63268_RST_SPI>;
375 serdes_cntl: syscon@10001804 {
376 compatible = "syscon";
377 reg = <0x10001804 0x4>;
381 periph_pwr: power-controller@1000184c {
382 compatible = "brcm,bcm63268-power-controller";
383 reg = <0x1000184c 0x4>;
384 #power-domain-cells = <1>;
387 leds: led-controller@10001900 {
388 #address-cells = <1>;
390 compatible = "brcm,bcm6328-leds";
391 reg = <0x10001900 0x24>;
397 compatible = "brcm,bcm63268-ehci", "generic-ehci";
398 reg = <0x10002500 0x100>;
402 interrupt-parent = <&periph_intc>;
403 interrupts = <BCM63268_IRQ_EHCI>;
412 compatible = "brcm,bcm63268-ohci", "generic-ohci";
413 reg = <0x10002600 0x100>;
417 interrupt-parent = <&periph_intc>;
418 interrupts = <BCM63268_IRQ_OHCI>;
426 usbh: usb-phy@10002700 {
427 compatible = "brcm,bcm63268-usbh-phy";
428 reg = <0x10002700 0x38>;
432 clocks = <&periph_clk BCM63268_CLK_USBH>,
433 <&timer_clk BCM63268_TCLK_USB_REF>;
434 clock-names = "usbh",
437 power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
438 resets = <&periph_rst BCM63268_RST_USBH>;
443 ethernet: ethernet@1000d800 {
444 compatible = "brcm,bcm63268-enetsw";
445 reg = <0x1000d800 0x80>,
452 interrupt-parent = <&periph_intc>;
453 interrupts = <BCM63268_IRQ_ENETSW_RX_DMA0>,
454 <BCM63268_IRQ_ENETSW_TX_DMA0>;
455 interrupt-names = "rx",
458 clocks = <&periph_clk BCM63268_CLK_GMAC>,
459 <&periph_clk BCM63268_CLK_ROBOSW>,
460 <&periph_clk BCM63268_CLK_ROBOSW250>,
461 <&timer_clk BCM63268_TCLK_EPHY1>,
462 <&timer_clk BCM63268_TCLK_EPHY2>,
463 <&timer_clk BCM63268_TCLK_EPHY3>,
464 <&timer_clk BCM63268_TCLK_GPHY1>;
466 resets = <&periph_rst BCM63268_RST_ENETSW>,
467 <&periph_rst BCM63268_RST_EPHY>,
468 <&periph_rst BCM63268_RST_GPHY>;
470 power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;
478 pcie: pcie@106e0000 {
479 compatible = "brcm,bcm6328-pcie";
480 reg = <0x106e0000 0x10000>;
481 #address-cells = <3>;
485 bus-range = <0x00 0x01>;
486 ranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;
487 linux,pci-probe-only = <1>;
489 interrupt-parent = <&periph_intc>;
490 interrupts = <BCM63268_IRQ_PCIE_RC>;
492 clocks = <&periph_clk BCM63268_CLK_PCIE>;
493 clock-names = "pcie";
495 resets = <&periph_rst BCM63268_RST_PCIE>,
496 <&periph_rst BCM63268_RST_PCIE_EXT>,
497 <&periph_rst BCM63268_RST_PCIE_CORE>,
498 <&periph_rst BCM63268_RST_PCIE_HARD>;
499 reset-names = "pcie",
504 power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;
506 brcm,serdes = <&serdes_cntl>;
511 switch0: switch@10700000 {
512 #address-cells = <1>;
514 compatible = "brcm,bcm6328-switch";
515 reg = <0x10700000 0x8000>;
519 #address-cells = <1>;
525 phy-mode = "internal";
526 ethernet = <ðernet>;
536 mdio: mdio@107000b0 {
537 #address-cells = <1>;
539 compatible = "brcm,bcm6368-mdio-mux";
540 reg = <0x107000b0 0x8>;
543 #address-cells = <1>;
547 phy1: ethernet-phy@1 {
548 compatible = "ethernet-phy-ieee802.3-c22";
552 phy2: ethernet-phy@2 {
553 compatible = "ethernet-phy-ieee802.3-c22";
557 phy3: ethernet-phy@3 {
558 compatible = "ethernet-phy-ieee802.3-c22";
562 phy4: ethernet-phy@4 {
563 compatible = "ethernet-phy-ieee802.3-c22";
569 #address-cells = <1>;