1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include <dt-bindings/clock/bcm63268-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>
9 #include <dt-bindings/reset/bcm63268-reset.h>
10 #include <dt-bindings/soc/bcm63268-pm.h>
15 compatible = "brcm,bcm63268";
27 bootargs = "earlycon";
28 stdout-path = "serial0:115200n8";
32 periph_osc: periph-osc {
33 compatible = "fixed-clock";
37 clock-frequency = <50000000>;
38 clock-output-names = "periph";
41 hsspi_osc: hsspi-osc {
42 compatible = "fixed-clock";
46 clock-frequency = <400000000>;
47 clock-output-names = "hsspi_osc";
54 mips-hpt-frequency = <200000000>;
57 compatible = "brcm,bmips4350", "mips,mips4Kc";
63 compatible = "brcm,bmips4350", "mips,mips4Kc";
69 cpu_intc: interrupt-controller {
71 compatible = "mti,cpu-interrupt-controller";
74 #interrupt-cells = <1>;
78 device_type = "memory";
86 compatible = "simple-bus";
89 periph_clk: clock-controller@10000004 {
90 compatible = "brcm,bcm63268-clocks";
91 reg = <0x10000004 0x4>;
95 pll_cntl: syscon@10000008 {
96 compatible = "syscon", "simple-mfd";
97 reg = <0x10000008 0x4>;
101 compatible = "syscon-reboot";
107 periph_rst: reset-controller@10000010 {
108 compatible = "brcm,bcm6345-reset";
109 reg = <0x10000010 0x4>;
113 ext_intc: interrupt-controller@10000018 {
114 #address-cells = <1>;
115 compatible = "brcm,bcm6345-ext-intc";
116 reg = <0x10000018 0x4>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
121 interrupt-parent = <&periph_intc>;
122 interrupts = <BCM63268_IRQ_EXT0>,
128 periph_intc: interrupt-controller@10000020 {
129 #address-cells = <1>;
130 compatible = "brcm,bcm6345-l1-intc";
131 reg = <0x10000020 0x20>,
134 interrupt-controller;
135 #interrupt-cells = <1>;
137 interrupt-parent = <&cpu_intc>;
138 interrupts = <2>, <3>;
141 wdt: watchdog@1000009c {
142 compatible = "brcm,bcm7038-wdt";
143 reg = <0x1000009c 0xc>;
145 clocks = <&periph_osc>;
150 timer_clk: clock-controller@100000ac {
151 compatible = "brcm,bcm63268-timer-clocks";
152 reg = <0x100000ac 0x4>;
157 gpio_cntl: syscon@100000c0 {
158 #address-cells = <1>;
160 compatible = "brcm,bcm63268-gpio-sysctl",
161 "syscon", "simple-mfd";
162 reg = <0x100000c0 0x80>;
163 ranges = <0 0x100000c0 0x80>;
167 compatible = "brcm,bcm63268-gpio";
168 reg-names = "dirout", "dat";
169 reg = <0x0 0x8>, <0x8 0x8>;
172 gpio-ranges = <&pinctrl 0 0 52>;
176 pinctrl: pinctrl@10 {
177 compatible = "brcm,bcm63268-pinctrl";
178 reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
180 pinctrl_serial_led: serial_led-pins {
181 pinctrl_serial_led_clk: serial_led_clk-pins {
182 function = "serial_led_clk";
186 pinctrl_serial_led_data: serial_led_data-pins {
187 function = "serial_led_data";
192 pinctrl_hsspi_cs4: hsspi_cs4-pins {
193 function = "hsspi_cs4";
197 pinctrl_hsspi_cs5: hsspi_cs5-pins {
198 function = "hsspi_cs5";
202 pinctrl_hsspi_cs6: hsspi_cs6-pins {
203 function = "hsspi_cs6";
207 pinctrl_hsspi_cs7: hsspi_cs7-pins {
208 function = "hsspi_cs7";
212 pinctrl_adsl_spi: adsl_spi {
213 pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
214 function = "adsl_spi_miso";
218 pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
219 function = "adsl_spi_mosi";
224 pinctrl_vreq_clk: vreq_clk-pins {
225 function = "vreq_clk";
229 pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
230 function = "pcie_clkreq_b";
234 pinctrl_robosw_led_clk: robosw_led_clk-pins {
235 function = "robosw_led_clk";
239 pinctrl_robosw_led_data: robosw_led_data-pins {
240 function = "robosw_led_data";
244 pinctrl_nand: nand-pins {
249 pinctrl_gpio35_alt: gpio35_alt-pins {
250 function = "gpio35_alt";
254 pinctrl_dectpd: dectpd-pins {
256 group = "dectpd_grp";
259 pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
260 function = "vdsl_phy_override_0";
261 group = "vdsl_phy_override_0_grp";
264 pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
265 function = "vdsl_phy_override_1";
266 group = "vdsl_phy_override_1_grp";
269 pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
270 function = "vdsl_phy_override_2";
271 group = "vdsl_phy_override_2_grp";
274 pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
275 function = "vdsl_phy_override_3";
276 group = "vdsl_phy_override_3_grp";
279 pinctrl_dsl_gpio8: dsl_gpio8-pins {
280 function = "dsl_gpio8";
284 pinctrl_dsl_gpio9: dsl_gpio9-pins {
285 function = "dsl_gpio9";
291 uart0: serial@10000180 {
292 compatible = "brcm,bcm6345-uart";
293 reg = <0x10000180 0x18>;
295 interrupt-parent = <&periph_intc>;
296 interrupts = <BCM63268_IRQ_UART0>;
298 clocks = <&periph_osc>;
299 clock-names = "periph";
304 uart1: serial@100001a0 {
305 compatible = "brcm,bcm6345-uart";
306 reg = <0x100001a0 0x18>;
308 interrupt-parent = <&periph_intc>;
309 interrupts = <BCM63268_IRQ_UART1>;
311 clocks = <&periph_osc>;
312 clock-names = "periph";
317 nflash: nand@10000200 {
318 #address-cells = <1>;
320 compatible = "brcm,nand-bcm6368",
321 "brcm,brcmnand-v4.0",
323 reg = <0x10000200 0x180>,
330 interrupt-parent = <&periph_intc>;
331 interrupts = <BCM63268_IRQ_NAND>;
333 clocks = <&periph_clk BCM63268_CLK_NAND>;
334 clock-names = "nand";
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_nand>;
342 lsspi: spi@10000800 {
343 #address-cells = <1>;
345 compatible = "brcm,bcm6358-spi";
346 reg = <0x10000800 0x70c>;
348 interrupt-parent = <&periph_intc>;
349 interrupts = <BCM63268_IRQ_LSSPI>;
351 clocks = <&periph_clk BCM63268_CLK_SPI>;
354 resets = <&periph_rst BCM63268_RST_SPI>;
359 hsspi: spi@10001000 {
360 #address-cells = <1>;
362 compatible = "brcm,bcm6328-hsspi";
363 reg = <0x10001000 0x600>;
365 interrupt-parent = <&periph_intc>;
366 interrupts = <BCM63268_IRQ_HSSPI>;
368 clocks = <&periph_clk BCM63268_CLK_HSSPI>,
370 clock-names = "hsspi",
373 resets = <&periph_rst BCM63268_RST_SPI>;
378 serdes_cntl: syscon@10001804 {
379 compatible = "syscon";
380 reg = <0x10001804 0x4>;
384 periph_pwr: power-controller@1000184c {
385 compatible = "brcm,bcm63268-power-controller";
386 reg = <0x1000184c 0x4>;
387 #power-domain-cells = <1>;
390 leds: led-controller@10001900 {
391 #address-cells = <1>;
393 compatible = "brcm,bcm6328-leds";
394 reg = <0x10001900 0x24>;
400 compatible = "brcm,bcm63268-ehci", "generic-ehci";
401 reg = <0x10002500 0x100>;
405 interrupt-parent = <&periph_intc>;
406 interrupts = <BCM63268_IRQ_EHCI>;
415 compatible = "brcm,bcm63268-ohci", "generic-ohci";
416 reg = <0x10002600 0x100>;
420 interrupt-parent = <&periph_intc>;
421 interrupts = <BCM63268_IRQ_OHCI>;
429 usbh: usb-phy@10002700 {
430 compatible = "brcm,bcm63268-usbh-phy";
431 reg = <0x10002700 0x38>;
435 clocks = <&periph_clk BCM63268_CLK_USBH>,
436 <&timer_clk BCM63268_TCLK_USB_REF>;
437 clock-names = "usbh",
440 power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
441 resets = <&periph_rst BCM63268_RST_USBH>;
446 ethernet: ethernet@1000d800 {
447 compatible = "brcm,bcm63268-enetsw";
448 reg = <0x1000d800 0x80>,
455 interrupt-parent = <&periph_intc>;
456 interrupts = <BCM63268_IRQ_ENETSW_RX_DMA0>,
457 <BCM63268_IRQ_ENETSW_TX_DMA0>;
458 interrupt-names = "rx",
461 clocks = <&periph_clk BCM63268_CLK_GMAC>,
462 <&periph_clk BCM63268_CLK_ROBOSW>,
463 <&periph_clk BCM63268_CLK_ROBOSW250>,
464 <&timer_clk BCM63268_TCLK_EPHY1>,
465 <&timer_clk BCM63268_TCLK_EPHY2>,
466 <&timer_clk BCM63268_TCLK_EPHY3>,
467 <&timer_clk BCM63268_TCLK_GPHY1>;
469 resets = <&periph_rst BCM63268_RST_ENETSW>,
470 <&periph_rst BCM63268_RST_EPHY>,
471 <&periph_rst BCM63268_RST_GPHY>;
473 power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;
481 pcie: pcie@106e0000 {
482 compatible = "brcm,bcm6328-pcie";
483 reg = <0x106e0000 0x10000>;
484 #address-cells = <3>;
488 bus-range = <0x00 0x01>;
489 ranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;
490 linux,pci-probe-only = <1>;
492 interrupt-parent = <&periph_intc>;
493 interrupts = <BCM63268_IRQ_PCIE_RC>;
495 clocks = <&periph_clk BCM63268_CLK_PCIE>;
496 clock-names = "pcie";
498 resets = <&periph_rst BCM63268_RST_PCIE>,
499 <&periph_rst BCM63268_RST_PCIE_EXT>,
500 <&periph_rst BCM63268_RST_PCIE_CORE>,
501 <&periph_rst BCM63268_RST_PCIE_HARD>;
502 reset-names = "pcie",
507 power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;
509 brcm,serdes = <&serdes_cntl>;
514 switch0: switch@10700000 {
515 #address-cells = <1>;
517 compatible = "brcm,bcm63268-switch";
518 reg = <0x10700000 0x8000>;
522 #address-cells = <1>;
528 phy-mode = "internal";
529 ethernet = <ðernet>;
539 mdio: mdio@107000b0 {
540 #address-cells = <1>;
542 compatible = "brcm,bcm6368-mdio-mux";
543 reg = <0x107000b0 0x8>;
546 #address-cells = <1>;
550 phy1: ethernet-phy@1 {
551 compatible = "ethernet-phy-ieee802.3-c22";
555 phy2: ethernet-phy@2 {
556 compatible = "ethernet-phy-ieee802.3-c22";
560 phy3: ethernet-phy@3 {
561 compatible = "ethernet-phy-ieee802.3-c22";
565 phy4: ethernet-phy@4 {
566 compatible = "ethernet-phy-ieee802.3-c22";
572 #address-cells = <1>;