target/linux/bmips/dts/bcm63268.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 /dts-v1/;
   4
   5 #include <dt-bindings/clock/bcm63268-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/leds/common.h>
  11 #include <dt-bindings/reset/bcm63268-reset.h>
  12 #include <dt-bindings/soc/bcm63268-pm.h>
  13
  14 / {
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17         compatible = "brcm,bcm63268";
  18
  19         aliases {
  20                 nflash = &nflash;
  21                 pinctrl = &pinctrl;
  22                 serial0 = &uart0;
  23                 serial1 = &uart1;
  24                 spi0 = &lsspi;
  25                 spi1 = &hsspi;
  26         };
  27
  28         chosen {
  29                 bootargs = "earlycon";
  30                 stdout-path = "serial0:115200n8";
  31         };
  32
  33         clocks {
  34                 periph_osc: periph-osc {
  35                         compatible = "fixed-clock";
  36
  37                         #clock-cells = <0>;
  38
  39                         clock-frequency = <50000000>;
  40                         clock-output-names = "periph";
  41                 };
  42
  43                 hsspi_osc: hsspi-osc {
  44                         compatible = "fixed-clock";
  45
  46                         #clock-cells = <0>;
  47
  48                         clock-frequency = <400000000>;
  49                         clock-output-names = "hsspi_osc";
  50                 };
  51         };
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56                 mips-hpt-frequency = <200000000>;
  57
  58                 cpu@0 {
  59                         compatible = "brcm,bmips4350", "mips,mips4Kc";
  60                         device_type = "cpu";
  61                         reg = <0>;
  62                 };
  63
  64                 cpu@1 {
  65                         compatible = "brcm,bmips4350", "mips,mips4Kc";
  66                         device_type = "cpu";
  67                         reg = <1>;
  68                 };
  69         };
  70
  71         cpu_intc: interrupt-controller {
  72                 #address-cells = <0>;
  73                 compatible = "mti,cpu-interrupt-controller";
  74
  75                 interrupt-controller;
  76                 #interrupt-cells = <1>;
  77         };
  78
  79         memory@0 {
  80                 device_type = "memory";
  81                 reg = <0 0>;
  82         };
  83
  84         ubus {
  85                 #address-cells = <1>;
  86                 #size-cells = <1>;
  87
  88                 compatible = "simple-bus";
  89                 ranges;
  90
  91                 periph_clk: clock-controller@10000004 {
  92                         compatible = "brcm,bcm63268-clocks";
  93                         reg = <0x10000004 0x4>;
  94                         #clock-cells = <1>;
  95                 };
  96
  97                 pll_cntl: syscon@10000008 {
  98                         compatible = "syscon", "simple-mfd";
  99                         reg = <0x10000008 0x4>;
 100                         native-endian;
 101
 102                         syscon-reboot {
 103                                 compatible = "syscon-reboot";
 104                                 offset = <0x0>;
 105                                 mask = <0x1>;
 106                         };
 107                 };
 108
 109                 periph_rst: reset-controller@10000010 {
 110                         compatible = "brcm,bcm6345-reset";
 111                         reg = <0x10000010 0x4>;
 112                         #reset-cells = <1>;
 113                 };
 114
 115                 ext_intc: interrupt-controller@10000018 {
 116                         #address-cells = <1>;
 117                         compatible = "brcm,bcm6345-ext-intc";
 118                         reg = <0x10000018 0x4>;
 119
 120                         interrupt-controller;
 121                         #interrupt-cells = <2>;
 122
 123                         interrupt-parent = <&periph_intc>;
 124                         interrupts = <BCM63268_IRQ_EXT0>,
 125                                      <BCM63268_IRQ_EXT1>,
 126                                      <BCM63268_IRQ_EXT2>,
 127                                      <BCM63268_IRQ_EXT3>;
 128                 };
 129
 130                 periph_intc: interrupt-controller@10000020 {
 131                         #address-cells = <1>;
 132                         compatible = "brcm,bcm6345-l1-intc";
 133                         reg = <0x10000020 0x20>,
 134                               <0x10000040 0x20>;
 135
 136                         interrupt-controller;
 137                         #interrupt-cells = <1>;
 138
 139                         interrupt-parent = <&cpu_intc>;
 140                         interrupts = <2>, <3>;
 141                 };
 142
 143                 wdt: watchdog@1000009c {
 144                         compatible = "brcm,bcm7038-wdt";
 145                         reg = <0x1000009c 0xc>;
 146
 147                         clocks = <&periph_osc>;
 148
 149                         timeout-sec = <30>;
 150                 };
 151
 152                 timer_clk: clock-controller@100000ac {
 153                         compatible = "brcm,bcm63268-timer-clocks";
 154                         reg = <0x100000ac 0x4>;
 155                         #clock-cells = <1>;
 156                         #reset-cells = <1>;
 157                 };
 158
 159                 gpio_cntl: syscon@100000c0 {
 160                         #address-cells = <1>;
 161                         #size-cells = <1>;
 162                         compatible = "brcm,bcm63268-gpio-sysctl",
 163                                      "syscon", "simple-mfd";
 164                         reg = <0x100000c0 0x80>;
 165                         ranges = <0 0x100000c0 0x80>;
 166                         native-endian;
 167
 168                         gpio: gpio@0 {
 169                                 compatible = "brcm,bcm63268-gpio";
 170                                 reg-names = "dirout", "dat";
 171                                 reg = <0x0 0x8>, <0x8 0x8>;
 172
 173                                 gpio-controller;
 174                                 gpio-ranges = <&pinctrl 0 0 52>;
 175                                 #gpio-cells = <2>;
 176                         };
 177
 178                         pinctrl: pinctrl@10 {
 179                                 compatible = "brcm,bcm63268-pinctrl";
 180                                 reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
 181
 182                                 pinctrl_serial_led: serial_led-pins {
 183                                         pinctrl_serial_led_clk: serial_led_clk-pins {
 184                                                 function = "serial_led_clk";
 185                                                 pins = "gpio0";
 186                                         };
 187
 188                                         pinctrl_serial_led_data: serial_led_data-pins {
 189                                                 function = "serial_led_data";
 190                                                 pins = "gpio1";
 191                                         };
 192                                 };
 193
 194                                 pinctrl_hsspi_cs4: hsspi_cs4-pins {
 195                                         function = "hsspi_cs4";
 196                                         pins = "gpio16";
 197                                 };
 198
 199                                 pinctrl_hsspi_cs5: hsspi_cs5-pins {
 200                                         function = "hsspi_cs5";
 201                                         pins = "gpio17";
 202                                 };
 203
 204                                 pinctrl_hsspi_cs6: hsspi_cs6-pins {
 205                                         function = "hsspi_cs6";
 206                                         pins = "gpio8";
 207                                 };
 208
 209                                 pinctrl_hsspi_cs7: hsspi_cs7-pins {
 210                                         function = "hsspi_cs7";
 211                                         pins = "gpio9";
 212                                 };
 213
 214                                 pinctrl_adsl_spi: adsl_spi {
 215                                         pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
 216                                                 function = "adsl_spi_miso";
 217                                                 pins = "gpio18";
 218                                         };
 219
 220                                         pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
 221                                                 function = "adsl_spi_mosi";
 222                                                 pins = "gpio19";
 223                                         };
 224                                 };
 225
 226                                 pinctrl_vreq_clk: vreq_clk-pins {
 227                                         function = "vreq_clk";
 228                                         pins = "gpio22";
 229                                 };
 230
 231                                 pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
 232                                         function = "pcie_clkreq_b";
 233                                         pins = "gpio23";
 234                                 };
 235
 236                                 pinctrl_robosw_led_clk: robosw_led_clk-pins {
 237                                         function = "robosw_led_clk";
 238                                         pins = "gpio30";
 239                                 };
 240
 241                                 pinctrl_robosw_led_data: robosw_led_data-pins {
 242                                         function = "robosw_led_data";
 243                                         pins = "gpio31";
 244                                 };
 245
 246                                 pinctrl_nand: nand-pins {
 247                                         function = "nand";
 248                                         group = "nand_grp";
 249                                 };
 250
 251                                 pinctrl_gpio35_alt: gpio35_alt-pins {
 252                                         function = "gpio35_alt";
 253                                         pin = "gpio35";
 254                                 };
 255
 256                                 pinctrl_dectpd: dectpd-pins {
 257                                         function = "dectpd";
 258                                         group = "dectpd_grp";
 259                                 };
 260
 261                                 pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
 262                                         function = "vdsl_phy_override_0";
 263                                         group = "vdsl_phy_override_0_grp";
 264                                 };
 265
 266                                 pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
 267                                         function = "vdsl_phy_override_1";
 268                                         group = "vdsl_phy_override_1_grp";
 269                                 };
 270
 271                                 pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
 272                                         function = "vdsl_phy_override_2";
 273                                         group = "vdsl_phy_override_2_grp";
 274                                 };
 275
 276                                 pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
 277                                         function = "vdsl_phy_override_3";
 278                                         group = "vdsl_phy_override_3_grp";
 279                                 };
 280
 281                                 pinctrl_dsl_gpio8: dsl_gpio8-pins {
 282                                         function = "dsl_gpio8";
 283                                         group = "dsl_gpio8";
 284                                 };
 285
 286                                 pinctrl_dsl_gpio9: dsl_gpio9-pins {
 287                                         function = "dsl_gpio9";
 288                                         group = "dsl_gpio9";
 289                                 };
 290                         };
 291                 };
 292
 293                 uart0: serial@10000180 {
 294                         compatible = "brcm,bcm6345-uart";
 295                         reg = <0x10000180 0x18>;
 296
 297                         interrupt-parent = <&periph_intc>;
 298                         interrupts = <BCM63268_IRQ_UART0>;
 299
 300                         clocks = <&periph_osc>;
 301                         clock-names = "periph";
 302
 303                         status = "disabled";
 304                 };
 305
 306                 uart1: serial@100001a0 {
 307                         compatible = "brcm,bcm6345-uart";
 308                         reg = <0x100001a0 0x18>;
 309
 310                         interrupt-parent = <&periph_intc>;
 311                         interrupts = <BCM63268_IRQ_UART1>;
 312
 313                         clocks = <&periph_osc>;
 314                         clock-names = "periph";
 315
 316                         status = "disabled";
 317                 };
 318
 319                 nflash: nand@10000200 {
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         compatible = "brcm,nand-bcm6368",
 323                                      "brcm,brcmnand-v4.0",
 324                                      "brcm,brcmnand";
 325                         reg = <0x10000200 0x180>,
 326                               <0x10000600 0x200>,
 327                               <0x100000b0 0x10>;
 328                         reg-names = "nand",
 329                                     "nand-cache",
 330                                     "nand-int-base";
 331
 332                         interrupt-parent = <&periph_intc>;
 333                         interrupts = <BCM63268_IRQ_NAND>;
 334
 335                         clocks = <&periph_clk BCM63268_CLK_NAND>;
 336                         clock-names = "nand";
 337
 338                         pinctrl-names = "default";
 339                         pinctrl-0 = <&pinctrl_nand>;
 340
 341                         status = "disabled";
 342                 };
 343
 344                 lsspi: spi@10000800 {
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         compatible = "brcm,bcm6358-spi";
 348                         reg = <0x10000800 0x70c>;
 349
 350                         interrupt-parent = <&periph_intc>;
 351                         interrupts = <BCM63268_IRQ_LSSPI>;
 352
 353                         clocks = <&periph_clk BCM63268_CLK_SPI>;
 354                         clock-names = "spi";
 355
 356                         resets = <&periph_rst BCM63268_RST_SPI>;
 357
 358                         status = "disabled";
 359                 };
 360
 361                 hsspi: spi@10001000 {
 362                         #address-cells = <1>;
 363                         #size-cells = <0>;
 364                         compatible = "brcm,bcm6328-hsspi";
 365                         reg = <0x10001000 0x600>;
 366
 367                         interrupt-parent = <&periph_intc>;
 368                         interrupts = <BCM63268_IRQ_HSSPI>;
 369
 370                         clocks = <&periph_clk BCM63268_CLK_HSSPI>,
 371                                  <&hsspi_osc>;
 372                         clock-names = "hsspi",
 373                                       "pll";
 374
 375                         resets = <&periph_rst BCM63268_RST_SPI>;
 376
 377                         status = "disabled";
 378                 };
 379
 380                 serdes_cntl: syscon@10001804 {
 381                         compatible = "syscon";
 382                         reg = <0x10001804 0x4>;
 383                         native-endian;
 384                 };
 385
 386                 periph_pwr: power-controller@1000184c {
 387                         compatible = "brcm,bcm63268-power-controller";
 388                         reg = <0x1000184c 0x4>;
 389                         #power-domain-cells = <1>;
 390                 };
 391
 392                 leds: led-controller@10001900 {
 393                         #address-cells = <1>;
 394                         #size-cells = <0>;
 395                         compatible = "brcm,bcm6328-leds";
 396                         reg = <0x10001900 0x24>;
 397
 398                         status = "disabled";
 399                 };
 400
 401                 ehci: usb@10002500 {
 402                         compatible = "brcm,bcm63268-ehci", "generic-ehci";
 403                         reg = <0x10002500 0x100>;
 404                         big-endian;
 405                         spurious-oc;
 406
 407                         interrupt-parent = <&periph_intc>;
 408                         interrupts = <BCM63268_IRQ_EHCI>;
 409
 410                         phys = <&usbh 0>;
 411                         phy-names = "usb";
 412
 413                         status = "disabled";
 414                 };
 415
 416                 ohci: usb@10002600 {
 417                         compatible = "brcm,bcm63268-ohci", "generic-ohci";
 418                         reg = <0x10002600 0x100>;
 419                         big-endian;
 420                         no-big-frame-no;
 421
 422                         interrupt-parent = <&periph_intc>;
 423                         interrupts = <BCM63268_IRQ_OHCI>;
 424
 425                         phys = <&usbh 0>;
 426                         phy-names = "usb";
 427
 428                         status = "disabled";
 429                 };
 430
 431                 usbh: usb-phy@10002700 {
 432                         compatible = "brcm,bcm63268-usbh-phy";
 433                         reg = <0x10002700 0x38>;
 434
 435                         #phy-cells = <1>;
 436
 437                         clocks = <&periph_clk BCM63268_CLK_USBH>,
 438                                  <&timer_clk BCM63268_TCLK_USB_REF>;
 439                         clock-names = "usbh",
 440                                       "usb_ref";
 441
 442                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
 443                         resets = <&periph_rst BCM63268_RST_USBH>;
 444
 445                         status = "disabled";
 446                 };
 447
 448                 random: rng@10002880 {
 449                         compatible = "brcm,bcm6368-rng";
 450                         reg = <0x10002880 0x14>;
 451
 452                         clocks = <&periph_clk BCM63268_CLK_IPSEC>;
 453                         clock-names = "ipsec";
 454
 455                         resets = <&periph_rst BCM63268_RST_IPSEC>;
 456
 457                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_IPSEC>;
 458                 };
 459
 460                 ethernet: ethernet@1000d800 {
 461                         compatible = "brcm,bcm63268-enetsw";
 462                         reg = <0x1000d800 0x80>,
 463                               <0x1000da00 0x80>,
 464                               <0x1000dc00 0x80>;
 465                         reg-names = "dma",
 466                                     "dma-channels",
 467                                     "dma-sram";
 468
 469                         interrupt-parent = <&periph_intc>;
 470                         interrupts = <BCM63268_IRQ_ENETSW_RX_DMA0>,
 471                                      <BCM63268_IRQ_ENETSW_TX_DMA0>;
 472                         interrupt-names = "rx",
 473                                           "tx";
 474
 475                         clocks = <&periph_clk BCM63268_CLK_GMAC>,
 476                                  <&periph_clk BCM63268_CLK_ROBOSW>,
 477                                  <&periph_clk BCM63268_CLK_ROBOSW250>,
 478                                  <&timer_clk BCM63268_TCLK_EPHY1>,
 479                                  <&timer_clk BCM63268_TCLK_EPHY2>,
 480                                  <&timer_clk BCM63268_TCLK_EPHY3>,
 481                                  <&timer_clk BCM63268_TCLK_GPHY1>;
 482
 483                         resets = <&periph_rst BCM63268_RST_ENETSW>,
 484                                  <&periph_rst BCM63268_RST_EPHY>,
 485                                  <&periph_rst BCM63268_RST_GPHY>;
 486
 487                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;
 488
 489                         dma-rx = <0>;
 490                         dma-tx = <1>;
 491
 492                         status = "disabled";
 493                 };
 494
 495                 pcie: pcie@106e0000 {
 496                         compatible = "brcm,bcm6328-pcie";
 497                         reg = <0x106e0000 0x10000>;
 498                         #address-cells = <3>;
 499                         #size-cells = <2>;
 500
 501                         device_type = "pci";
 502                         bus-range = <0x00 0x01>;
 503                         ranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;
 504                         linux,pci-probe-only = <1>;
 505
 506                         interrupt-parent = <&periph_intc>;
 507                         interrupts = <BCM63268_IRQ_PCIE_RC>;
 508
 509                         clocks = <&periph_clk BCM63268_CLK_PCIE>;
 510                         clock-names = "pcie";
 511
 512                         resets = <&periph_rst BCM63268_RST_PCIE>,
 513                                  <&periph_rst BCM63268_RST_PCIE_EXT>,
 514                                  <&periph_rst BCM63268_RST_PCIE_CORE>,
 515                                  <&periph_rst BCM63268_RST_PCIE_HARD>;
 516                         reset-names = "pcie",
 517                                       "pcie-ext",
 518                                       "pcie-core",
 519                                       "pcie-hard";
 520
 521                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;
 522
 523                         brcm,serdes = <&serdes_cntl>;
 524
 525                         status = "disabled";
 526                 };
 527
 528                 switch0: switch@10700000 {
 529                         #address-cells = <1>;
 530                         #size-cells = <0>;
 531                         compatible = "brcm,bcm63268-switch";
 532                         reg = <0x10700000 0x8000>;
 533                         big-endian;
 534
 535                         ports {
 536                                 #address-cells = <1>;
 537                                 #size-cells = <0>;
 538
 539                                 port@8 {
 540                                         reg = <8>;
 541
 542                                         phy-mode = "internal";
 543                                         ethernet = <&ethernet>;
 544
 545                                         fixed-link {
 546                                                 speed = <1000>;
 547                                                 full-duplex;
 548                                         };
 549                                 };
 550                         };
 551                 };
 552
 553                 mdio: mdio@107000b0 {
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         compatible = "brcm,bcm6368-mdio-mux";
 557                         reg = <0x107000b0 0x8>;
 558
 559                         mdio_int: mdio@0 {
 560                                 #address-cells = <1>;
 561                                 #size-cells = <0>;
 562                                 reg = <0>;
 563
 564                                 phy1: ethernet-phy@1 {
 565                                         compatible = "ethernet-phy-ieee802.3-c22";
 566                                         reg = <1>;
 567                                 };
 568
 569                                 phy2: ethernet-phy@2 {
 570                                         compatible = "ethernet-phy-ieee802.3-c22";
 571                                         reg = <2>;
 572                                 };
 573
 574                                 phy3: ethernet-phy@3 {
 575                                         compatible = "ethernet-phy-ieee802.3-c22";
 576                                         reg = <3>;
 577                                 };
 578
 579                                 phy4: ethernet-phy@4 {
 580                                         compatible = "ethernet-phy-ieee802.3-c22";
 581                                         reg = <4>;
 582                                 };
 583                         };
 584
 585                         mdio_ext: mdio@1 {
 586                                 #address-cells = <1>;
 587                                 #size-cells = <0>;
 588                                 reg = <1>;
 589                         };
 590                 };
 591         };
 592 };