1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include <dt-bindings/clock/bcm63268-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>
9 #include <dt-bindings/reset/bcm63268-reset.h>
10 #include <dt-bindings/soc/bcm63268-pm.h>
15 compatible = "brcm,bcm63268";
27 bootargs = "earlycon";
28 stdout-path = "serial0:115200n8";
32 periph_osc: periph-osc {
33 compatible = "fixed-clock";
37 clock-frequency = <50000000>;
38 clock-output-names = "periph";
41 hsspi_osc: hsspi-osc {
42 compatible = "fixed-clock";
46 clock-frequency = <400000000>;
47 clock-output-names = "hsspi_osc";
54 mips-hpt-frequency = <200000000>;
57 compatible = "brcm,bmips4350", "mips,mips4Kc";
63 compatible = "brcm,bmips4350", "mips,mips4Kc";
69 cpu_intc: interrupt-controller {
71 compatible = "mti,cpu-interrupt-controller";
74 #interrupt-cells = <1>;
78 device_type = "memory";
86 compatible = "simple-bus";
89 periph_clk: clock-controller@10000004 {
90 compatible = "brcm,bcm63268-clocks";
91 reg = <0x10000004 0x4>;
95 pll_cntl: syscon@10000008 {
96 compatible = "syscon", "simple-mfd";
97 reg = <0x10000008 0x4>;
101 compatible = "syscon-reboot";
107 periph_rst: reset-controller@10000010 {
108 compatible = "brcm,bcm6345-reset";
109 reg = <0x10000010 0x4>;
113 ext_intc: interrupt-controller@10000018 {
114 #address-cells = <1>;
115 compatible = "brcm,bcm6345-ext-intc";
116 reg = <0x10000018 0x4>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
121 interrupts = <BCM63268_IRQ_EXT0>,
127 periph_intc: interrupt-controller@10000020 {
128 #address-cells = <1>;
129 compatible = "brcm,bcm6345-l1-intc";
130 reg = <0x10000020 0x20>,
133 interrupt-controller;
134 #interrupt-cells = <1>;
136 interrupt-parent = <&cpu_intc>;
137 interrupts = <2>, <3>;
140 wdt: watchdog@1000009c {
141 compatible = "brcm,bcm7038-wdt";
142 reg = <0x1000009c 0xc>;
144 clocks = <&periph_osc>;
149 timer_clk: clock-controller@100000ac {
150 compatible = "brcm,bcm63268-timer-clocks";
151 reg = <0x100000ac 0x4>;
156 gpio: syscon@100000c0 {
157 compatible = "syscon", "simple-mfd";
158 reg = <0x100000c0 0x80>;
161 pinctrl: pin-controller {
162 compatible = "brcm,bcm63268-pinctrl";
167 interrupts-extended = <&ext_intc 0 0>,
171 interrupt-names = "gpio32",
176 pinctrl_serial_led: serial_led {
177 pinctrl_serial_led_clk: serial_led_clk {
178 function = "serial_led_clk";
182 pinctrl_serial_led_data: serial_led_data {
183 function = "serial_led_data";
188 pinctrl_hsspi_cs4: hsspi_cs4 {
189 function = "hsspi_cs4";
193 pinctrl_hsspi_cs5: hsspi_cs5 {
194 function = "hsspi_cs5";
198 pinctrl_hsspi_cs6: hsspi_cs6 {
199 function = "hsspi_cs6";
203 pinctrl_hsspi_cs7: hsspi_cs7 {
204 function = "hsspi_cs7";
208 pinctrl_adsl_spi: adsl_spi {
209 pinctrl_adsl_spi_miso: adsl_spi_miso {
210 function = "adsl_spi_miso";
214 pinctrl_adsl_spi_mosi: adsl_spi_mosi {
215 function = "adsl_spi_mosi";
220 pinctrl_vreq_clk: vreq_clk {
221 function = "vreq_clk";
225 pinctrl_pcie_clkreq_b: pcie_clkreq_b {
226 function = "pcie_clkreq_b";
230 pinctrl_robosw_led_clk: robosw_led_clk {
231 function = "robosw_led_clk";
235 pinctrl_robosw_led_data: robosw_led_data {
236 function = "robosw_led_data";
245 pinctrl_gpio35_alt: gpio35_alt {
246 function = "gpio35_alt";
250 pinctrl_dectpd: dectpd {
252 group = "dectpd_grp";
255 pinctrl_vdsl_phy_override_0: vdsl_phy_override_0 {
256 function = "vdsl_phy_override_0";
257 group = "vdsl_phy_override_0_grp";
260 pinctrl_vdsl_phy_override_1: vdsl_phy_override_1 {
261 function = "vdsl_phy_override_1";
262 group = "vdsl_phy_override_1_grp";
265 pinctrl_vdsl_phy_override_2: vdsl_phy_override_2 {
266 function = "vdsl_phy_override_2";
267 group = "vdsl_phy_override_2_grp";
270 pinctrl_vdsl_phy_override_3: vdsl_phy_override_3 {
271 function = "vdsl_phy_override_3";
272 group = "vdsl_phy_override_3_grp";
275 pinctrl_dsl_gpio8: dsl_gpio8 {
276 function = "dsl_gpio8";
280 pinctrl_dsl_gpio9: dsl_gpio9 {
281 function = "dsl_gpio9";
287 uart0: serial@10000180 {
288 compatible = "brcm,bcm6345-uart";
289 reg = <0x10000180 0x18>;
291 interrupt-parent = <&periph_intc>;
292 interrupts = <BCM63268_IRQ_UART0>;
294 clocks = <&periph_osc>;
295 clock-names = "periph";
300 uart1: serial@100001a0 {
301 compatible = "brcm,bcm6345-uart";
302 reg = <0x100001a0 0x18>;
304 interrupt-parent = <&periph_intc>;
305 interrupts = <BCM63268_IRQ_UART1>;
307 clocks = <&periph_osc>;
308 clock-names = "periph";
313 nflash: nand@10000200 {
314 #address-cells = <1>;
316 compatible = "brcm,nand-bcm6368",
317 "brcm,brcmnand-v4.0",
319 reg = <0x10000200 0x180>,
326 interrupt-parent = <&periph_intc>;
327 interrupts = <BCM63268_IRQ_NAND>;
329 clocks = <&periph_clk BCM63268_CLK_NAND>;
330 clock-names = "nand";
332 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_nand>;
338 lsspi: spi@10000800 {
339 #address-cells = <1>;
341 compatible = "brcm,bcm6358-spi";
342 reg = <0x10000800 0x70c>;
344 interrupt-parent = <&periph_intc>;
345 interrupts = <BCM63268_IRQ_LSSPI>;
347 clocks = <&periph_clk BCM63268_CLK_SPI>;
350 resets = <&periph_rst BCM63268_RST_SPI>;
355 hsspi: spi@10001000 {
356 #address-cells = <1>;
358 compatible = "brcm,bcm6328-hsspi";
359 reg = <0x10001000 0x600>;
361 interrupt-parent = <&periph_intc>;
362 interrupts = <BCM63268_IRQ_HSSPI>;
364 clocks = <&periph_clk BCM63268_CLK_HSSPI>,
366 clock-names = "hsspi",
369 resets = <&periph_rst BCM63268_RST_SPI>;
374 serdes_cntl: syscon@10001804 {
375 compatible = "syscon";
376 reg = <0x10001804 0x4>;
380 periph_pwr: power-controller@1000184c {
381 compatible = "brcm,bcm63268-power-controller";
382 reg = <0x1000184c 0x4>;
383 #power-domain-cells = <1>;
386 leds: led-controller@10001900 {
387 #address-cells = <1>;
389 compatible = "brcm,bcm6328-leds";
390 reg = <0x10001900 0x24>;
396 compatible = "brcm,bcm63268-ehci", "generic-ehci";
397 reg = <0x10002500 0x100>;
401 interrupt-parent = <&periph_intc>;
402 interrupts = <BCM63268_IRQ_EHCI>;
411 compatible = "brcm,bcm63268-ohci", "generic-ohci";
412 reg = <0x10002600 0x100>;
416 interrupt-parent = <&periph_intc>;
417 interrupts = <BCM63268_IRQ_OHCI>;
425 usbh: usb-phy@10002700 {
426 compatible = "brcm,bcm63268-usbh-phy";
427 reg = <0x10002700 0x38>;
431 clocks = <&periph_clk BCM63268_CLK_USBH>,
432 <&timer_clk BCM63268_TCLK_USB_REF>;
433 clock-names = "usbh",
436 power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
437 resets = <&periph_rst BCM63268_RST_USBH>;
442 ethernet: ethernet@1000d800 {
443 compatible = "brcm,bcm63268-enetsw";
444 reg = <0x1000d800 0x80>,
451 interrupt-parent = <&periph_intc>;
452 interrupts = <BCM63268_IRQ_ENETSW_RX_DMA0>,
453 <BCM63268_IRQ_ENETSW_TX_DMA0>;
454 interrupt-names = "rx",
457 clocks = <&periph_clk BCM63268_CLK_GMAC>,
458 <&periph_clk BCM63268_CLK_ROBOSW>,
459 <&periph_clk BCM63268_CLK_ROBOSW250>,
460 <&timer_clk BCM63268_TCLK_EPHY1>,
461 <&timer_clk BCM63268_TCLK_EPHY2>,
462 <&timer_clk BCM63268_TCLK_EPHY3>,
463 <&timer_clk BCM63268_TCLK_GPHY1>;
465 resets = <&periph_rst BCM63268_RST_ENETSW>,
466 <&periph_rst BCM63268_RST_EPHY>,
467 <&periph_rst BCM63268_RST_GPHY>;
469 power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;
477 pcie: pcie@106e0000 {
478 compatible = "brcm,bcm6328-pcie";
479 reg = <0x106e0000 0x10000>;
480 #address-cells = <3>;
484 bus-range = <0x00 0x01>;
485 ranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;
486 linux,pci-probe-only = <1>;
488 interrupt-parent = <&periph_intc>;
489 interrupts = <BCM63268_IRQ_PCIE_RC>;
491 clocks = <&periph_clk BCM63268_CLK_PCIE>;
492 clock-names = "pcie";
494 resets = <&periph_rst BCM63268_RST_PCIE>,
495 <&periph_rst BCM63268_RST_PCIE_EXT>,
496 <&periph_rst BCM63268_RST_PCIE_CORE>,
497 <&periph_rst BCM63268_RST_PCIE_HARD>;
498 reset-names = "pcie",
503 power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;
505 brcm,serdes = <&serdes_cntl>;
510 switch0: switch@10700000 {
511 #address-cells = <1>;
513 compatible = "brcm,bcm6328-switch";
514 reg = <0x10700000 0x8000>;
518 #address-cells = <1>;
525 phy-mode = "internal";
526 ethernet = <ðernet>;
536 mdio: mdio@107000b0 {
537 #address-cells = <1>;
539 compatible = "brcm,bcm6368-mdio-mux";
540 reg = <0x107000b0 0x8>;
543 #address-cells = <1>;
547 phy1: ethernet-phy@1 {
548 compatible = "ethernet-phy-ieee802.3-c22";
552 phy2: ethernet-phy@2 {
553 compatible = "ethernet-phy-ieee802.3-c22";
557 phy3: ethernet-phy@3 {
558 compatible = "ethernet-phy-ieee802.3-c22";
562 phy4: ethernet-phy@4 {
563 compatible = "ethernet-phy-ieee802.3-c22";
569 #address-cells = <1>;