1 // SPDX-License-Identifier: GPL-2.0-or-later
5 #include <dt-bindings/clock/bcm6362-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/bcm6362-interrupt-controller.h>
9 #include <dt-bindings/reset/bcm6362-reset.h>
10 #include <dt-bindings/soc/bcm6362-pm.h>
15 compatible = "brcm,bcm6362";
27 bootargs = "earlycon";
28 stdout-path = "serial0:115200n8";
32 periph_osc: periph-osc {
33 compatible = "fixed-clock";
37 clock-frequency = <50000000>;
38 clock-output-names = "periph";
41 hsspi_osc: hsspi-osc {
42 compatible = "fixed-clock";
46 clock-frequency = <400000000>;
47 clock-output-names = "hsspi_osc";
54 mips-hpt-frequency = <200000000>;
57 compatible = "brcm,bmips4350", "mips,mips4Kc";
63 compatible = "brcm,bmips4350", "mips,mips4Kc";
69 cpu_intc: interrupt-controller {
71 compatible = "mti,cpu-interrupt-controller";
74 #interrupt-cells = <1>;
78 device_type = "memory";
86 compatible = "simple-bus";
89 periph_clk: clock-controller@10000004 {
90 compatible = "brcm,bcm6362-clocks";
91 reg = <0x10000004 0x4>;
95 pll_cntl: syscon@10000008 {
96 compatible = "syscon", "simple-mfd";
97 reg = <0x10000008 0x4>;
101 compatible = "syscon-reboot";
107 periph_rst: reset-controller@10000010 {
108 compatible = "brcm,bcm6345-reset";
109 reg = <0x10000010 0x4>;
113 ext_intc: interrupt-controller@10000018 {
114 #address-cells = <1>;
115 compatible = "brcm,bcm6345-ext-intc";
116 reg = <0x10000018 0x4>;
118 interrupt-controller;
119 #interrupt-cells = <2>;
121 interrupts = <BCM6362_IRQ_EXT0>,
127 periph_intc: interrupt-controller@10000020 {
128 #address-cells = <1>;
129 compatible = "brcm,bcm6345-l1-intc";
130 reg = <0x10000020 0x10>,
133 interrupt-controller;
134 #interrupt-cells = <1>;
136 interrupt-parent = <&cpu_intc>;
137 interrupts = <2>, <3>;
140 wdt: watchdog@1000005c {
141 compatible = "brcm,bcm7038-wdt";
142 reg = <0x1000005c 0xc>;
144 clocks = <&periph_osc>;
149 gpio: syscon@10000080 {
150 compatible = "syscon", "simple-mfd";
151 reg = <0x10000080 0x80>;
154 pinctrl: pin-controller {
155 compatible = "brcm,bcm6362-pinctrl";
160 interrupts-extended = <&ext_intc 0 0>,
164 interrupt-names = "gpio24",
169 pinctrl_usb_device_led: usb_device_led {
170 function = "usb_device_led";
174 pinctrl_sys_irq: sys_irq {
175 function = "sys_irq";
179 pinctrl_serial_led: serial_led {
180 pinctrl_serial_led_clk: serial_led_clk {
181 function = "serial_led_clk";
185 pinctrl_serial_led_data: serial_led_data {
186 function = "serial_led_data";
191 pinctrl_robosw_led_data: robosw_led_data {
192 function = "robosw_led_data";
196 pinctrl_robosw_led_clk: robosw_led_clk {
197 function = "robosw_led_clk";
201 pinctrl_robosw_led0: robosw_led0 {
202 function = "robosw_led0";
206 pinctrl_robosw_led1: robosw_led1 {
207 function = "robosw_led1";
211 pinctrl_inet_led: inet_led {
212 function = "inet_led";
216 pinctrl_spi_cs2: spi_cs2 {
217 function = "spi_cs2";
221 pinctrl_spi_cs3: spi_cs3 {
222 function = "spi_cs3";
226 pinctrl_ntr_pulse: ntr_pulse {
227 function = "ntr_pulse";
231 pinctrl_uart1_scts: uart1_scts {
232 function = "uart1_scts";
236 pinctrl_uart1_srts: uart1_srts {
237 function = "uart1_srts";
241 pinctrl_uart1: uart1 {
242 pinctrl_uart1_sdin: uart1_sdin {
243 function = "uart1_sdin";
247 pinctrl_uart1_sdout: uart1_sdout {
248 function = "uart1_sdout";
253 pinctrl_adsl_spi: adsl_spi {
254 pinctrl_adsl_spi_miso: adsl_spi_miso {
255 function = "adsl_spi_miso";
259 pinctrl_adsl_spi_mosi: adsl_spi_mosi {
260 function = "adsl_spi_mosi";
264 pinctrl_adsl_spi_clk: adsl_spi_clk {
265 function = "adsl_spi_clk";
269 pinctrl_adsl_spi_cs: adsl_spi_cs {
270 function = "adsl_spi_cs";
275 pinctrl_ephy0_led: ephy0_led {
276 function = "ephy0_led";
280 pinctrl_ephy1_led: ephy1_led {
281 function = "ephy1_led";
285 pinctrl_ephy2_led: ephy2_led {
286 function = "ephy2_led";
290 pinctrl_ephy3_led: ephy3_led {
291 function = "ephy3_led";
295 pinctrl_ext_irq0: ext_irq0 {
296 function = "ext_irq0";
300 pinctrl_ext_irq1: ext_irq1 {
301 function = "ext_irq1";
305 pinctrl_ext_irq2: ext_irq2 {
306 function = "ext_irq2";
310 pinctrl_ext_irq3: ext_irq3 {
311 function = "ext_irq3";
322 uart0: serial@10000100 {
323 compatible = "brcm,bcm6345-uart";
324 reg = <0x10000100 0x18>;
326 interrupt-parent = <&periph_intc>;
327 interrupts = <BCM6362_IRQ_UART0>;
329 clocks = <&periph_osc>;
330 clock-names = "periph";
335 uart1: serial@10000120 {
336 compatible = "brcm,bcm6345-uart";
337 reg = <0x10000120 0x18>;
339 interrupt-parent = <&periph_intc>;
340 interrupts = <BCM6362_IRQ_UART1>;
342 clocks = <&periph_osc>;
343 clock-names = "periph";
348 nflash: nand@10000200 {
349 #address-cells = <1>;
351 compatible = "brcm,nand-bcm6368",
352 "brcm,brcmnand-v2.2",
354 reg = <0x10000200 0x180>,
361 interrupt-parent = <&periph_intc>;
362 interrupts = <BCM6362_IRQ_NAND>;
364 clocks = <&periph_clk BCM6362_CLK_NAND>;
365 clock-names = "nand";
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_nand>;
373 lsspi: spi@10000800 {
374 #address-cells = <1>;
376 compatible = "brcm,bcm6358-spi";
377 reg = <0x10000800 0x70c>;
379 interrupt-parent = <&periph_intc>;
380 interrupts = <BCM6362_IRQ_LSSPI>;
382 clocks = <&periph_clk BCM6362_CLK_SPI>;
385 resets = <&periph_rst BCM6362_RST_SPI>;
390 hsspi: spi@10001000 {
391 #address-cells = <1>;
393 compatible = "brcm,bcm6328-hsspi";
394 reg = <0x10001000 0x600>;
396 interrupt-parent = <&periph_intc>;
397 interrupts = <BCM6362_IRQ_HSSPI>;
399 clocks = <&periph_clk BCM6362_CLK_HSSPI>,
401 clock-names = "hsspi",
404 resets = <&periph_rst BCM6362_RST_SPI>;
409 serdes_cntl: syscon@10001804 {
410 compatible = "syscon";
411 reg = <0x10001804 0x4>;
415 periph_pwr: power-controller@10001848 {
416 compatible = "brcm,bcm6362-power-controller";
417 reg = <0x10001848 0x4>;
418 #power-domain-cells = <1>;
421 leds: led-controller@10001900 {
422 #address-cells = <1>;
424 compatible = "brcm,bcm6328-leds";
425 reg = <0x10001900 0x24>;
431 compatible = "brcm,bcm6362-ehci", "generic-ehci";
432 reg = <0x10002500 0x100>;
436 interrupt-parent = <&periph_intc>;
437 interrupts = <BCM6362_IRQ_EHCI>;
446 compatible = "brcm,bcm6362-ohci", "generic-ohci";
447 reg = <0x10002600 0x100>;
451 interrupt-parent = <&periph_intc>;
452 interrupts = <BCM6362_IRQ_OHCI>;
460 usbh: usb-phy@10002700 {
461 compatible = "brcm,bcm6362-usbh-phy";
462 reg = <0x10002700 0x38>;
466 clocks = <&periph_clk BCM6362_CLK_USBH>;
467 clock-names = "usbh";
469 power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_USBH>;
470 resets = <&periph_rst BCM6362_RST_USBH>;
475 ethernet: ethernet@1000d800 {
476 compatible = "brcm,bcm6362-enetsw";
477 reg = <0x1000d800 0x80>,
484 interrupt-parent = <&periph_intc>;
485 interrupts = <BCM6362_IRQ_ENETSW_RX_DMA0>;
486 interrupt-names = "rx";
488 clocks = <&periph_clk BCM6362_CLK_SWPKT_USB>,
489 <&periph_clk BCM6362_CLK_SWPKT_SAR>,
490 <&periph_clk BCM6362_CLK_ROBOSW>;
492 resets = <&periph_rst BCM6362_RST_ENETSW>,
493 <&periph_rst BCM6362_RST_EPHY>;
495 power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_ROBOSW>,
496 <&periph_pwr BCM6362_POWER_DOMAIN_GMII_PADS>;
504 switch0: switch@10e00000 {
505 #address-cells = <1>;
507 compatible = "brcm,bcm6328-switch";
508 reg = <0x10e00000 0x8000>;
512 #address-cells = <1>;
519 phy-mode = "internal";
520 ethernet = <ðernet>;
530 mdio: mdio@10e000b0 {
531 #address-cells = <1>;
533 compatible = "brcm,bcm6368-mdio-mux";
534 reg = <0x10e000b0 0x8>;
537 #address-cells = <1>;
541 phy1: ethernet-phy@1 {
542 compatible = "ethernet-phy-ieee802.3-c22";
546 phy2: ethernet-phy@2 {
547 compatible = "ethernet-phy-ieee802.3-c22";
551 phy3: ethernet-phy@3 {
552 compatible = "ethernet-phy-ieee802.3-c22";
556 phy4: ethernet-phy@4 {
557 compatible = "ethernet-phy-ieee802.3-c22";
563 #address-cells = <1>;
569 pcie: pcie@10e40000 {
570 compatible = "brcm,bcm6328-pcie";
571 reg = <0x10e40000 0x10000>;
572 #address-cells = <3>;
576 bus-range = <0x00 0x01>;
577 ranges = <0x2000000 0 0x10f00000 0x10f00000 0 0x100000>;
578 linux,pci-probe-only = <1>;
580 interrupt-parent = <&periph_intc>;
581 interrupts = <BCM6362_IRQ_PCIE_RC>;
583 clocks = <&periph_clk BCM6362_CLK_PCIE>;
584 clock-names = "pcie";
586 resets = <&periph_rst BCM6362_RST_PCIE>,
587 <&periph_rst BCM6362_RST_PCIE_EXT>,
588 <&periph_rst BCM6362_RST_PCIE_CORE>;
589 reset-names = "pcie",
593 power-domains = <&periph_pwr BCM6362_POWER_DOMAIN_PCIE>;
595 brcm,serdes = <&serdes_cntl>;