bmips: dts: move leds dt-bindings include to SoCs
[openwrt/staging/jow.git] / target / linux / bmips / dts / bcm6368.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /dts-v1/;
4
5 #include <dt-bindings/clock/bcm6368-clock.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/bcm6368-interrupt-controller.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/reset/bcm6368-reset.h>
12
13 / {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 compatible = "brcm,bcm6368";
17
18 aliases {
19 nflash = &nflash;
20 pflash = &pflash;
21 pinctrl = &pinctrl;
22 serial0 = &uart0;
23 serial1 = &uart1;
24 spi0 = &lsspi;
25 };
26
27 chosen {
28 bootargs = "earlycon";
29 stdout-path = "serial0:115200n8";
30 };
31
32 clocks {
33 periph_osc: periph-osc {
34 compatible = "fixed-clock";
35
36 #clock-cells = <0>;
37
38 clock-frequency = <50000000>;
39 clock-output-names = "periph";
40 };
41 };
42
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 mips-hpt-frequency = <200000000>;
47
48 cpu@0 {
49 compatible = "brcm,bmips4350", "mips,mips4Kc";
50 device_type = "cpu";
51 reg = <0>;
52 };
53
54 cpu@1 {
55 compatible = "brcm,bmips4350", "mips,mips4Kc";
56 device_type = "cpu";
57 reg = <1>;
58 };
59 };
60
61 cpu_intc: interrupt-controller {
62 #address-cells = <0>;
63 compatible = "mti,cpu-interrupt-controller";
64
65 interrupt-controller;
66 #interrupt-cells = <1>;
67 };
68
69 memory@0 {
70 device_type = "memory";
71 reg = <0 0>;
72 };
73
74 ubus {
75 #address-cells = <1>;
76 #size-cells = <1>;
77
78 compatible = "simple-bus";
79 ranges;
80
81 periph_clk: clock-controller@10000004 {
82 compatible = "brcm,bcm6368-clocks";
83 reg = <0x10000004 0x4>;
84 #clock-cells = <1>;
85 };
86
87 pll_cntl: syscon@10000008 {
88 compatible = "syscon", "simple-mfd";
89 reg = <0x10000008 0x4>;
90 native-endian;
91
92 syscon-reboot {
93 compatible = "syscon-reboot";
94 offset = <0x0>;
95 mask = <0x1>;
96 };
97 };
98
99 periph_rst: reset-controller@10000010 {
100 compatible = "brcm,bcm6345-reset";
101 reg = <0x10000010 0x4>;
102 #reset-cells = <1>;
103 };
104
105 ext_intc0: interrupt-controller@10000018 {
106 #address-cells = <1>;
107 compatible = "brcm,bcm6345-ext-intc";
108 reg = <0x10000018 0x4>;
109
110 interrupt-controller;
111 #interrupt-cells = <2>;
112
113 interrupt-parent = <&periph_intc>;
114 interrupts = <BCM6368_IRQ_EXT0>,
115 <BCM6368_IRQ_EXT1>,
116 <BCM6368_IRQ_EXT2>,
117 <BCM6368_IRQ_EXT3>;
118 };
119
120 ext_intc1: interrupt-controller@1000001c {
121 #address-cells = <1>;
122 compatible = "brcm,bcm6345-ext-intc";
123 reg = <0x1000001c 0x4>;
124
125 interrupt-controller;
126 #interrupt-cells = <2>;
127
128 interrupt-parent = <&periph_intc>;
129 interrupts = <BCM6368_IRQ_EXT4>,
130 <BCM6368_IRQ_EXT5>;
131 };
132
133 periph_intc: interrupt-controller@10000020 {
134 #address-cells = <1>;
135 compatible = "brcm,bcm6345-l1-intc";
136 reg = <0x10000020 0x10>,
137 <0x10000030 0x10>;
138
139 interrupt-controller;
140 #interrupt-cells = <1>;
141
142 interrupt-parent = <&cpu_intc>;
143 interrupts = <2>, <3>;
144 };
145
146 wdt: watchdog@1000005c {
147 compatible = "brcm,bcm7038-wdt";
148 reg = <0x1000005c 0xc>;
149
150 clocks = <&periph_osc>;
151
152 timeout-sec = <30>;
153 };
154
155 gpio_cntl: syscon@10000080 {
156 #address-cells = <1>;
157 #size-cells = <1>;
158 compatible = "brcm,bcm6368-gpio-sysctl",
159 "syscon", "simple-mfd";
160 reg = <0x10000080 0x80>;
161 ranges = <0 0x10000080 0x80>;
162 native-endian;
163
164 gpio: gpio@0 {
165 compatible = "brcm,bcm6368-gpio";
166 reg-names = "dirout", "dat";
167 reg = <0x0 0x8>, <0x8 0x8>;
168
169 gpio-controller;
170 gpio-ranges = <&pinctrl 0 0 38>;
171 #gpio-cells = <2>;
172 };
173
174 pinctrl: pinctrl@18 {
175 compatible = "brcm,bcm6368-pinctrl";
176 reg = <0x18 0x4>, <0x38 0x4>;
177
178 pinctrl_analog_afe_0: analog_afe_0-pins {
179 function = "analog_afe_0";
180 pins = "gpio0";
181 };
182
183 pinctrl_analog_afe_1: analog_afe_1-pins {
184 function = "analog_afe_1";
185 pins = "gpio1";
186 };
187
188 pinctrl_sys_irq: sys_irq-pins {
189 function = "sys_irq";
190 pins = "gpio2";
191 };
192
193 pinctrl_serial_led: serial_led-pins {
194 pinctrl_serial_led_data: serial_led_data-pins {
195 function = "serial_led_data";
196 pins = "gpio3";
197 };
198
199 pinctrl_serial_led_clk: serial_led_clk-pins {
200 function = "serial_led_clk";
201 pins = "gpio4";
202 };
203 };
204
205 pinctrl_inet_led: inet_led-pins {
206 function = "inet_led";
207 pins = "gpio5";
208 };
209
210 pinctrl_ephy0_led: ephy0_led-pins {
211 function = "ephy0_led";
212 pins = "gpio6";
213 };
214
215 pinctrl_ephy1_led: ephy1_led-pins {
216 function = "ephy1_led";
217 pins = "gpio7";
218 };
219
220 pinctrl_ephy2_led: ephy2_led-pins {
221 function = "ephy2_led";
222 pins = "gpio8";
223 };
224
225 pinctrl_ephy3_led: ephy3_led-pins {
226 function = "ephy3_led";
227 pins = "gpio9";
228 };
229
230 pinctrl_robosw_led_data: robosw_led_data-pins {
231 function = "robosw_led_data";
232 pins = "gpio10";
233 };
234
235 pinctrl_robosw_led_clk: robosw_led_clk-pins {
236 function = "robosw_led_clk";
237 pins = "gpio11";
238 };
239
240 pinctrl_robosw_led0: robosw_led0-pins {
241 function = "robosw_led0";
242 pins = "gpio12";
243 };
244
245 pinctrl_robosw_led1: robosw_led1-pins {
246 function = "robosw_led1";
247 pins = "gpio13";
248 };
249
250 pinctrl_usb_device_led: usb_device_led-pins {
251 function = "usb_device_led";
252 pins = "gpio14";
253 };
254
255 pinctrl_pci: pci-pins {
256 pinctrl_pci_req1: pci_req1-pins {
257 function = "pci_req1";
258 pins = "gpio16";
259 };
260
261 pinctrl_pci_gnt1: pci_gnt1-pins {
262 function = "pci_gnt1";
263 pins = "gpio17";
264 };
265
266 pinctrl_pci_intb: pci_intb-pins {
267 function = "pci_intb";
268 pins = "gpio18";
269 };
270
271 pinctrl_pci_req0: pci_req0-pins {
272 function = "pci_req0";
273 pins = "gpio19";
274 };
275
276 pinctrl_pci_gnt0: pci_gnt0-pins {
277 function = "pci_gnt0";
278 pins = "gpio20";
279 };
280 };
281
282 pinctrl_pcmcia: pcmcia-pins {
283 pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
284 function = "pcmcia_cd1";
285 pins = "gpio22";
286 };
287
288 pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
289 function = "pcmcia_cd2";
290 pins = "gpio23";
291 };
292
293 pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
294 function = "pcmcia_vs1";
295 pins = "gpio24";
296 };
297
298 pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
299 function = "pcmcia_vs2";
300 pins = "gpio25";
301 };
302 };
303
304 pinctrl_ebi_cs2: ebi_cs2-pins {
305 function = "ebi_cs2";
306 pins = "gpio26";
307 };
308
309 pinctrl_ebi_cs3: ebi_cs3-pins {
310 function = "ebi_cs3";
311 pins = "gpio27";
312 };
313
314 pinctrl_spi_cs2: spi_cs2-pins {
315 function = "spi_cs2";
316 pins = "gpio28";
317 };
318
319 pinctrl_spi_cs3: spi_cs3-pins {
320 function = "spi_cs3";
321 pins = "gpio29";
322 };
323
324 pinctrl_spi_cs4: spi_cs4-pins {
325 function = "spi_cs4";
326 pins = "gpio30";
327 };
328
329 pinctrl_spi_cs5: spi_cs5-pins {
330 function = "spi_cs5";
331 pins = "gpio31";
332 };
333
334 pinctrl_uart1: uart1-pins {
335 function = "uart1";
336 group = "uart1_grp";
337 };
338 };
339 };
340
341 leds: led-controller@100000d0 {
342 #address-cells = <1>;
343 #size-cells = <0>;
344 compatible = "brcm,bcm6358-leds";
345 reg = <0x100000d0 0x8>;
346
347 status = "disabled";
348 };
349
350 uart0: serial@10000100 {
351 compatible = "brcm,bcm6345-uart";
352 reg = <0x10000100 0x18>;
353
354 interrupt-parent = <&periph_intc>;
355 interrupts = <BCM6368_IRQ_UART0>;
356
357 clocks = <&periph_osc>;
358 clock-names = "periph";
359
360 status = "disabled";
361 };
362
363 uart1: serial@10000120 {
364 compatible = "brcm,bcm6345-uart";
365 reg = <0x10000120 0x18>;
366
367 interrupt-parent = <&periph_intc>;
368 interrupts = <BCM6368_IRQ_UART1>;
369
370 clocks = <&periph_osc>;
371 clock-names = "periph";
372
373 status = "disabled";
374 };
375
376 nflash: nand@10000200 {
377 #address-cells = <1>;
378 #size-cells = <0>;
379 compatible = "brcm,nand-bcm6368",
380 "brcm,brcmnand-v2.1",
381 "brcm,brcmnand";
382 reg = <0x10000200 0x180>,
383 <0x10000600 0x200>,
384 <0x10000070 0x10>;
385 reg-names = "nand",
386 "nand-cache",
387 "nand-int-base";
388
389 interrupt-parent = <&periph_intc>;
390 interrupts = <BCM6368_IRQ_NAND>;
391
392 clocks = <&periph_clk BCM6368_CLK_NAND>;
393 clock-names = "nand";
394
395 status = "disabled";
396 };
397
398 lsspi: spi@10000800 {
399 #address-cells = <1>;
400 #size-cells = <0>;
401 compatible = "brcm,bcm6358-spi";
402 reg = <0x10000800 0x70c>;
403
404 interrupt-parent = <&periph_intc>;
405 interrupts = <BCM6368_IRQ_SPI>;
406
407 clocks = <&periph_clk BCM6368_CLK_SPI>;
408 clock-names = "spi";
409
410 resets = <&periph_rst BCM6368_RST_SPI>;
411
412 status = "disabled";
413 };
414
415 pci: pci@10001000 {
416 compatible = "brcm,bcm6348-pci";
417 reg = <0x10001000 0x200>;
418 #address-cells = <3>;
419 #size-cells = <2>;
420
421 device_type = "pci";
422 bus-range = <0x00 0x01>;
423 ranges = <0x2000000 0 0x30000000 0x30000000 0 0x8000000>,
424 <0x1000000 0 0x08000000 0x08000000 0 0x0010000>;
425 linux,pci-probe-only = <1>;
426
427 interrupt-parent = <&periph_intc>;
428 interrupts = <BCM6368_IRQ_MPI>;
429
430 resets = <&periph_rst BCM6368_RST_MPI>;
431 reset-names = "pci";
432
433 pinctrl-names = "default";
434 pinctrl-0 = <&pinctrl_pci>;
435
436 brcm,remap;
437
438 status = "disabled";
439 };
440
441 ehci: usb@10001500 {
442 compatible = "brcm,bcm6368-ehci", "generic-ehci";
443 reg = <0x10001500 0x100>;
444 big-endian;
445 spurious-oc;
446
447 interrupt-parent = <&periph_intc>;
448 interrupts = <BCM6368_IRQ_EHCI>;
449
450 phys = <&usbh 0>;
451 phy-names = "usb";
452
453 status = "disabled";
454 };
455
456 ohci: usb@10001600 {
457 compatible = "brcm,bcm6368-ohci", "generic-ohci";
458 reg = <0x10001600 0x100>;
459 big-endian;
460 no-big-frame-no;
461
462 interrupt-parent = <&periph_intc>;
463 interrupts = <BCM6368_IRQ_OHCI>;
464
465 phys = <&usbh 0>;
466 phy-names = "usb";
467
468 status = "disabled";
469 };
470
471 usbh: usb-phy@10001700 {
472 compatible = "brcm,bcm6368-usbh-phy";
473 reg = <0x10001700 0x38>;
474
475 #phy-cells = <1>;
476
477 clocks = <&periph_clk BCM6368_CLK_USBH>;
478 clock-names = "usbh";
479
480 resets = <&periph_rst BCM6368_RST_USBH>;
481
482 status = "disabled";
483 };
484
485 random: rng@10004180 {
486 compatible = "brcm,bcm6368-rng";
487 reg = <0x10004180 0x14>;
488
489 clocks = <&periph_clk BCM6368_CLK_IPSEC>;
490 clock-names = "ipsec";
491
492 resets = <&periph_rst BCM6368_RST_IPSEC>;
493 };
494
495 ethernet: ethernet@10006800 {
496 compatible = "brcm,bcm6368-enetsw";
497 reg = <0x10006800 0x80>,
498 <0x10006a00 0x80>,
499 <0x10006c00 0x80>;
500 reg-names = "dma",
501 "dma-channels",
502 "dma-sram";
503
504 interrupt-parent = <&periph_intc>;
505 interrupts = <BCM6368_IRQ_ENETSW_RX_DMA0>,
506 <BCM6368_IRQ_ENETSW_TX_DMA0>;
507 interrupt-names = "rx",
508 "tx";
509
510 clocks = <&periph_clk BCM6368_CLK_SWPKT_USB>,
511 <&periph_clk BCM6368_CLK_SWPKT_SAR>,
512 <&periph_clk BCM6368_CLK_ROBOSW>;
513
514 resets = <&periph_rst BCM6368_RST_SWITCH>,
515 <&periph_rst BCM6368_RST_EPHY>;
516
517 dma-rx = <0>;
518 dma-tx = <1>;
519
520 status = "disabled";
521 };
522
523 switch0: switch@10f00000 {
524 #address-cells = <1>;
525 #size-cells = <0>;
526 compatible = "brcm,bcm6368-switch";
527 reg = <0x10f00000 0x8000>;
528 big-endian;
529
530 ports {
531 #address-cells = <1>;
532 #size-cells = <0>;
533
534 port@8 {
535 reg = <8>;
536
537 phy-mode = "internal";
538 ethernet = <&ethernet>;
539
540 fixed-link {
541 speed = <1000>;
542 full-duplex;
543 };
544 };
545 };
546 };
547
548 mdio: mdio@10f000b0 {
549 #address-cells = <1>;
550 #size-cells = <0>;
551 compatible = "brcm,bcm6368-mdio-mux";
552 reg = <0x10f000b0 0x8>;
553
554 mdio_int: mdio@0 {
555 #address-cells = <1>;
556 #size-cells = <0>;
557 reg = <0>;
558
559 phy1: ethernet-phy@1 {
560 compatible = "ethernet-phy-ieee802.3-c22";
561 reg = <1>;
562 };
563
564 phy2: ethernet-phy@2 {
565 compatible = "ethernet-phy-ieee802.3-c22";
566 reg = <2>;
567 };
568
569 phy3: ethernet-phy@3 {
570 compatible = "ethernet-phy-ieee802.3-c22";
571 reg = <3>;
572 };
573
574 phy4: ethernet-phy@4 {
575 compatible = "ethernet-phy-ieee802.3-c22";
576 reg = <4>;
577 };
578 };
579
580 mdio_ext: mdio@1 {
581 #address-cells = <1>;
582 #size-cells = <0>;
583 reg = <1>;
584 };
585 };
586 };
587
588 pflash: nor@18000000 {
589 #address-cells = <1>;
590 #size-cells = <1>;
591 compatible = "cfi-flash";
592 reg = <0x18000000 0x2000000>;
593 bank-width = <2>;
594
595 status = "disabled";
596 };
597 };