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[openwrt/staging/dedeckeh.git] / target / linux / bmips / files / drivers / net / ethernet / broadcom / bcm6368-enetsw.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * BCM6368 Ethernet Switch Controller Driver
4 *
5 * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
6 * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/ethtool.h>
15 #include <linux/if_vlan.h>
16 #include <linux/interrupt.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_net.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23
24 /* MTU */
25 #define ENETSW_TAG_SIZE (6 + VLAN_HLEN)
26 #define ENETSW_MTU_OVERHEAD (VLAN_ETH_HLEN + VLAN_HLEN + \
27 ENETSW_TAG_SIZE)
28 #define ENETSW_FRAG_SIZE(x) (SKB_DATA_ALIGN(NET_SKB_PAD + x + \
29 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
30
31 /* default number of descriptor */
32 #define ENETSW_DEF_RX_DESC 64
33 #define ENETSW_DEF_TX_DESC 32
34 #define ENETSW_DEF_CPY_BREAK 128
35
36 /* maximum burst len for dma (4 bytes unit) */
37 #define ENETSW_DMA_MAXBURST 8
38
39 /* DMA channels */
40 #define DMA_CHAN_WIDTH 0x10
41
42 /* Controller Configuration Register */
43 #define DMA_CFG_REG 0x0
44 #define DMA_CFG_EN_SHIFT 0
45 #define DMA_CFG_EN_MASK (1 << DMA_CFG_EN_SHIFT)
46 #define DMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
47
48 /* Flow Control Descriptor Low Threshold register */
49 #define DMA_FLOWCL_REG(x) (0x4 + (x) * 6)
50
51 /* Flow Control Descriptor High Threshold register */
52 #define DMA_FLOWCH_REG(x) (0x8 + (x) * 6)
53
54 /* Flow Control Descriptor Buffer Alloca Threshold register */
55 #define DMA_BUFALLOC_REG(x) (0xc + (x) * 6)
56 #define DMA_BUFALLOC_FORCE_SHIFT 31
57 #define DMA_BUFALLOC_FORCE_MASK (1 << DMA_BUFALLOC_FORCE_SHIFT)
58
59 /* Channel Configuration register */
60 #define DMAC_CHANCFG_REG 0x0
61 #define DMAC_CHANCFG_EN_SHIFT 0
62 #define DMAC_CHANCFG_EN_MASK (1 << DMAC_CHANCFG_EN_SHIFT)
63 #define DMAC_CHANCFG_PKTHALT_SHIFT 1
64 #define DMAC_CHANCFG_PKTHALT_MASK (1 << DMAC_CHANCFG_PKTHALT_SHIFT)
65 #define DMAC_CHANCFG_BUFHALT_SHIFT 2
66 #define DMAC_CHANCFG_BUFHALT_MASK (1 << DMAC_CHANCFG_BUFHALT_SHIFT)
67 #define DMAC_CHANCFG_CHAINING_SHIFT 2
68 #define DMAC_CHANCFG_CHAINING_MASK (1 << DMAC_CHANCFG_CHAINING_SHIFT)
69 #define DMAC_CHANCFG_WRAP_EN_SHIFT 3
70 #define DMAC_CHANCFG_WRAP_EN_MASK (1 << DMAC_CHANCFG_WRAP_EN_SHIFT)
71 #define DMAC_CHANCFG_FLOWC_EN_SHIFT 4
72 #define DMAC_CHANCFG_FLOWC_EN_MASK (1 << DMAC_CHANCFG_FLOWC_EN_SHIFT)
73
74 /* Interrupt Control/Status register */
75 #define DMAC_IR_REG 0x4
76 #define DMAC_IR_BUFDONE_MASK (1 << 0)
77 #define DMAC_IR_PKTDONE_MASK (1 << 1)
78 #define DMAC_IR_NOTOWNER_MASK (1 << 2)
79
80 /* Interrupt Mask register */
81 #define DMAC_IRMASK_REG 0x8
82
83 /* Maximum Burst Length */
84 #define DMAC_MAXBURST_REG 0xc
85
86 /* Ring Start Address register */
87 #define DMAS_RSTART_REG 0x0
88
89 /* State Ram Word 2 */
90 #define DMAS_SRAM2_REG 0x4
91
92 /* State Ram Word 3 */
93 #define DMAS_SRAM3_REG 0x8
94
95 /* State Ram Word 4 */
96 #define DMAS_SRAM4_REG 0xc
97
98 struct bcm6368_enetsw_desc {
99 u32 len_stat;
100 u32 address;
101 };
102
103 /* control */
104 #define DMADESC_LENGTH_SHIFT 16
105 #define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT)
106 #define DMADESC_OWNER_MASK (1 << 15)
107 #define DMADESC_EOP_MASK (1 << 14)
108 #define DMADESC_SOP_MASK (1 << 13)
109 #define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
110 #define DMADESC_WRAP_MASK (1 << 12)
111 #define DMADESC_USB_NOZERO_MASK (1 << 1)
112 #define DMADESC_USB_ZERO_MASK (1 << 0)
113
114 /* status */
115 #define DMADESC_UNDER_MASK (1 << 9)
116 #define DMADESC_APPEND_CRC (1 << 8)
117 #define DMADESC_OVSIZE_MASK (1 << 4)
118 #define DMADESC_RXER_MASK (1 << 2)
119 #define DMADESC_CRC_MASK (1 << 1)
120 #define DMADESC_OV_MASK (1 << 0)
121 #define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \
122 DMADESC_OVSIZE_MASK | \
123 DMADESC_RXER_MASK | \
124 DMADESC_CRC_MASK | \
125 DMADESC_OV_MASK)
126
127 struct bcm6368_enetsw {
128 void __iomem *dma_base;
129 void __iomem *dma_chan;
130 void __iomem *dma_sram;
131
132 struct device **pm;
133 struct device_link **link_pm;
134 int num_pms;
135
136 struct clk **clock;
137 unsigned int num_clocks;
138
139 struct reset_control **reset;
140 unsigned int num_resets;
141
142 int copybreak;
143
144 int irq_rx;
145 int irq_tx;
146
147 /* hw view of rx & tx dma ring */
148 dma_addr_t rx_desc_dma;
149 dma_addr_t tx_desc_dma;
150
151 /* allocated size (in bytes) for rx & tx dma ring */
152 unsigned int rx_desc_alloc_size;
153 unsigned int tx_desc_alloc_size;
154
155 struct napi_struct napi;
156
157 /* dma channel id for rx */
158 int rx_chan;
159
160 /* number of dma desc in rx ring */
161 int rx_ring_size;
162
163 /* cpu view of rx dma ring */
164 struct bcm6368_enetsw_desc *rx_desc_cpu;
165
166 /* current number of armed descriptor given to hardware for rx */
167 int rx_desc_count;
168
169 /* next rx descriptor to fetch from hardware */
170 int rx_curr_desc;
171
172 /* next dirty rx descriptor to refill */
173 int rx_dirty_desc;
174
175 /* size of allocated rx buffer */
176 unsigned int rx_buf_size;
177
178 /* size of allocated rx frag */
179 unsigned int rx_frag_size;
180
181 /* list of buffer given to hw for rx */
182 unsigned char **rx_buf;
183
184 /* used when rx buffer allocation failed, so we defer rx queue
185 * refill */
186 struct timer_list rx_timeout;
187
188 /* lock rx_timeout against rx normal operation */
189 spinlock_t rx_lock;
190
191 /* dma channel id for tx */
192 int tx_chan;
193
194 /* number of dma desc in tx ring */
195 int tx_ring_size;
196
197 /* maximum dma burst size */
198 int dma_maxburst;
199
200 /* cpu view of rx dma ring */
201 struct bcm6368_enetsw_desc *tx_desc_cpu;
202
203 /* number of available descriptor for tx */
204 int tx_desc_count;
205
206 /* next tx descriptor avaiable */
207 int tx_curr_desc;
208
209 /* next dirty tx descriptor to reclaim */
210 int tx_dirty_desc;
211
212 /* list of skb given to hw for tx */
213 struct sk_buff **tx_skb;
214
215 /* lock used by tx reclaim and xmit */
216 spinlock_t tx_lock;
217
218 /* network device reference */
219 struct net_device *net_dev;
220
221 /* platform device reference */
222 struct platform_device *pdev;
223
224 /* dma channel enable mask */
225 u32 dma_chan_en_mask;
226
227 /* dma channel interrupt mask */
228 u32 dma_chan_int_mask;
229
230 /* dma channel width */
231 unsigned int dma_chan_width;
232 };
233
234 static inline void dma_writel(struct bcm6368_enetsw *priv, u32 val, u32 off)
235 {
236 __raw_writel(val, priv->dma_base + off);
237 }
238
239 static inline u32 dma_readl(struct bcm6368_enetsw *priv, u32 off, int chan)
240 {
241 return __raw_readl(priv->dma_chan + off + chan * priv->dma_chan_width);
242 }
243
244 static inline void dmac_writel(struct bcm6368_enetsw *priv, u32 val,
245 u32 off, int chan)
246 {
247 __raw_writel(val, priv->dma_chan + off + chan * priv->dma_chan_width);
248 }
249
250 static inline void dmas_writel(struct bcm6368_enetsw *priv, u32 val,
251 u32 off, int chan)
252 {
253 __raw_writel(val, priv->dma_sram + off + chan * priv->dma_chan_width);
254 }
255
256 /*
257 * refill rx queue
258 */
259 static int bcm6368_enetsw_refill_rx(struct net_device *ndev, bool napi_mode)
260 {
261 struct bcm6368_enetsw *priv = netdev_priv(ndev);
262 struct platform_device *pdev = priv->pdev;
263 struct device *dev = &pdev->dev;
264
265 while (priv->rx_desc_count < priv->rx_ring_size) {
266 struct bcm6368_enetsw_desc *desc;
267 int desc_idx;
268 u32 len_stat;
269
270 desc_idx = priv->rx_dirty_desc;
271 desc = &priv->rx_desc_cpu[desc_idx];
272
273 if (!priv->rx_buf[desc_idx]) {
274 unsigned char *buf;
275 dma_addr_t p;
276
277 if (likely(napi_mode))
278 buf = napi_alloc_frag(priv->rx_frag_size);
279 else
280 buf = netdev_alloc_frag(priv->rx_frag_size);
281
282 if (unlikely(!buf))
283 break;
284
285 p = dma_map_single(dev, buf + NET_SKB_PAD,
286 priv->rx_buf_size, DMA_FROM_DEVICE);
287 if (unlikely(dma_mapping_error(dev, p))) {
288 skb_free_frag(buf);
289 break;
290 }
291
292 priv->rx_buf[desc_idx] = buf;
293 desc->address = p;
294 }
295
296 len_stat = priv->rx_buf_size << DMADESC_LENGTH_SHIFT;
297 len_stat |= DMADESC_OWNER_MASK;
298 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
299 len_stat |= DMADESC_WRAP_MASK;
300 priv->rx_dirty_desc = 0;
301 } else {
302 priv->rx_dirty_desc++;
303 }
304 wmb();
305 desc->len_stat = len_stat;
306
307 priv->rx_desc_count++;
308
309 /* tell dma engine we allocated one buffer */
310 dma_writel(priv, 1, DMA_BUFALLOC_REG(priv->rx_chan));
311 }
312
313 /* If rx ring is still empty, set a timer to try allocating
314 * again at a later time. */
315 if (priv->rx_desc_count == 0 && netif_running(ndev)) {
316 dev_warn(dev, "unable to refill rx ring\n");
317 priv->rx_timeout.expires = jiffies + HZ;
318 add_timer(&priv->rx_timeout);
319 }
320
321 return 0;
322 }
323
324 /*
325 * timer callback to defer refill rx queue in case we're OOM
326 */
327 static void bcm6368_enetsw_refill_rx_timer(struct timer_list *t)
328 {
329 struct bcm6368_enetsw *priv = from_timer(priv, t, rx_timeout);
330 struct net_device *ndev = priv->net_dev;
331
332 spin_lock(&priv->rx_lock);
333 bcm6368_enetsw_refill_rx(ndev, false);
334 spin_unlock(&priv->rx_lock);
335 }
336
337 /*
338 * extract packet from rx queue
339 */
340 static int bcm6368_enetsw_receive_queue(struct net_device *ndev, int budget)
341 {
342 struct bcm6368_enetsw *priv = netdev_priv(ndev);
343 struct platform_device *pdev = priv->pdev;
344 struct device *dev = &pdev->dev;
345 struct list_head rx_list;
346 struct sk_buff *skb;
347 int processed = 0;
348
349 INIT_LIST_HEAD(&rx_list);
350
351 /* don't scan ring further than number of refilled
352 * descriptor */
353 if (budget > priv->rx_desc_count)
354 budget = priv->rx_desc_count;
355
356 do {
357 struct bcm6368_enetsw_desc *desc;
358 unsigned int frag_size;
359 unsigned char *buf;
360 int desc_idx;
361 u32 len_stat;
362 unsigned int len;
363
364 desc_idx = priv->rx_curr_desc;
365 desc = &priv->rx_desc_cpu[desc_idx];
366
367 /* make sure we actually read the descriptor status at
368 * each loop */
369 rmb();
370
371 len_stat = desc->len_stat;
372
373 /* break if dma ownership belongs to hw */
374 if (len_stat & DMADESC_OWNER_MASK)
375 break;
376
377 processed++;
378 priv->rx_curr_desc++;
379 if (priv->rx_curr_desc == priv->rx_ring_size)
380 priv->rx_curr_desc = 0;
381
382 /* if the packet does not have start of packet _and_
383 * end of packet flag set, then just recycle it */
384 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
385 ndev->stats.rx_dropped++;
386 continue;
387 }
388
389 /* valid packet */
390 buf = priv->rx_buf[desc_idx];
391 len = (len_stat & DMADESC_LENGTH_MASK)
392 >> DMADESC_LENGTH_SHIFT;
393 /* don't include FCS */
394 len -= 4;
395
396 if (len < priv->copybreak) {
397 unsigned int nfrag_size = ENETSW_FRAG_SIZE(len);
398 unsigned char *nbuf = napi_alloc_frag(nfrag_size);
399
400 if (unlikely(!nbuf)) {
401 /* forget packet, just rearm desc */
402 ndev->stats.rx_dropped++;
403 continue;
404 }
405
406 dma_sync_single_for_cpu(dev, desc->address,
407 len, DMA_FROM_DEVICE);
408 memcpy(nbuf + NET_SKB_PAD, buf + NET_SKB_PAD, len);
409 dma_sync_single_for_device(dev, desc->address,
410 len, DMA_FROM_DEVICE);
411 buf = nbuf;
412 frag_size = nfrag_size;
413 } else {
414 dma_unmap_single(dev, desc->address,
415 priv->rx_buf_size, DMA_FROM_DEVICE);
416 priv->rx_buf[desc_idx] = NULL;
417 frag_size = priv->rx_frag_size;
418 }
419
420 skb = napi_build_skb(buf, frag_size);
421 if (unlikely(!skb)) {
422 skb_free_frag(buf);
423 ndev->stats.rx_dropped++;
424 continue;
425 }
426
427 skb_reserve(skb, NET_SKB_PAD);
428 skb_put(skb, len);
429 ndev->stats.rx_packets++;
430 ndev->stats.rx_bytes += len;
431 list_add_tail(&skb->list, &rx_list);
432 } while (processed < budget);
433
434 list_for_each_entry(skb, &rx_list, list)
435 skb->protocol = eth_type_trans(skb, ndev);
436 netif_receive_skb_list(&rx_list);
437 priv->rx_desc_count -= processed;
438
439 if (processed || !priv->rx_desc_count) {
440 bcm6368_enetsw_refill_rx(ndev, true);
441
442 /* kick rx dma */
443 dmac_writel(priv, priv->dma_chan_en_mask,
444 DMAC_CHANCFG_REG, priv->rx_chan);
445 }
446
447 return processed;
448 }
449
450 /*
451 * try to or force reclaim of transmitted buffers
452 */
453 static int bcm6368_enetsw_tx_reclaim(struct net_device *ndev, int force,
454 int budget)
455 {
456 struct bcm6368_enetsw *priv = netdev_priv(ndev);
457 struct platform_device *pdev = priv->pdev;
458 struct device *dev = &pdev->dev;
459 unsigned int bytes = 0;
460 int released = 0;
461
462 while (priv->tx_desc_count < priv->tx_ring_size) {
463 struct bcm6368_enetsw_desc *desc;
464 struct sk_buff *skb;
465
466 /* We run in a bh and fight against start_xmit, which
467 * is called with bh disabled */
468 spin_lock(&priv->tx_lock);
469
470 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
471
472 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
473 spin_unlock(&priv->tx_lock);
474 break;
475 }
476
477 /* ensure other field of the descriptor were not read
478 * before we checked ownership */
479 rmb();
480
481 skb = priv->tx_skb[priv->tx_dirty_desc];
482 priv->tx_skb[priv->tx_dirty_desc] = NULL;
483 dma_unmap_single(dev, desc->address, skb->len,
484 DMA_TO_DEVICE);
485
486 priv->tx_dirty_desc++;
487 if (priv->tx_dirty_desc == priv->tx_ring_size)
488 priv->tx_dirty_desc = 0;
489 priv->tx_desc_count++;
490
491 spin_unlock(&priv->tx_lock);
492
493 if (desc->len_stat & DMADESC_UNDER_MASK)
494 ndev->stats.tx_errors++;
495
496 bytes += skb->len;
497 napi_consume_skb(skb, budget);
498 released++;
499 }
500
501 netdev_completed_queue(ndev, released, bytes);
502
503 if (netif_queue_stopped(ndev) && released)
504 netif_wake_queue(ndev);
505
506 return released;
507 }
508
509 /*
510 * poll func, called by network core
511 */
512 static int bcm6368_enetsw_poll(struct napi_struct *napi, int budget)
513 {
514 struct bcm6368_enetsw *priv = container_of(napi, struct bcm6368_enetsw, napi);
515 struct net_device *ndev = priv->net_dev;
516 int rx_work_done;
517
518 /* ack interrupts */
519 dmac_writel(priv, priv->dma_chan_int_mask,
520 DMAC_IR_REG, priv->rx_chan);
521 dmac_writel(priv, priv->dma_chan_int_mask,
522 DMAC_IR_REG, priv->tx_chan);
523
524 /* reclaim sent skb */
525 bcm6368_enetsw_tx_reclaim(ndev, 0, budget);
526
527 spin_lock(&priv->rx_lock);
528 rx_work_done = bcm6368_enetsw_receive_queue(ndev, budget);
529 spin_unlock(&priv->rx_lock);
530
531 if (rx_work_done >= budget) {
532 /* rx queue is not yet empty/clean */
533 return rx_work_done;
534 }
535
536 /* no more packet in rx/tx queue, remove device from poll
537 * queue */
538 napi_complete_done(napi, rx_work_done);
539
540 /* restore rx/tx interrupt */
541 dmac_writel(priv, priv->dma_chan_int_mask,
542 DMAC_IRMASK_REG, priv->rx_chan);
543 dmac_writel(priv, priv->dma_chan_int_mask,
544 DMAC_IRMASK_REG, priv->tx_chan);
545
546 return rx_work_done;
547 }
548
549 /*
550 * rx/tx dma interrupt handler
551 */
552 static irqreturn_t bcm6368_enetsw_isr_dma(int irq, void *dev_id)
553 {
554 struct net_device *ndev = dev_id;
555 struct bcm6368_enetsw *priv = netdev_priv(ndev);
556
557 /* mask rx/tx interrupts */
558 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
559 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
560
561 napi_schedule(&priv->napi);
562
563 return IRQ_HANDLED;
564 }
565
566 /*
567 * tx request callback
568 */
569 static netdev_tx_t
570 bcm6368_enetsw_start_xmit(struct sk_buff *skb, struct net_device *ndev)
571 {
572 struct bcm6368_enetsw *priv = netdev_priv(ndev);
573 struct platform_device *pdev = priv->pdev;
574 struct device *dev = &pdev->dev;
575 struct bcm6368_enetsw_desc *desc;
576 u32 len_stat;
577 netdev_tx_t ret;
578 dma_addr_t p;
579
580 /* lock against tx reclaim */
581 spin_lock(&priv->tx_lock);
582
583 /* make sure the tx hw queue is not full, should not happen
584 * since we stop queue before it's the case */
585 if (unlikely(!priv->tx_desc_count)) {
586 netif_stop_queue(ndev);
587 dev_err(dev, "xmit called with no tx desc available?\n");
588 ret = NETDEV_TX_BUSY;
589 goto out_unlock;
590 }
591
592 /* pad small packets */
593 if (skb->len < (ETH_ZLEN + ETH_FCS_LEN)) {
594 int needed = (ETH_ZLEN + ETH_FCS_LEN) - skb->len;
595 char *data;
596
597 if (unlikely(skb_tailroom(skb) < needed)) {
598 struct sk_buff *nskb;
599
600 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
601 if (!nskb) {
602 ret = NETDEV_TX_BUSY;
603 goto out_unlock;
604 }
605
606 dev_kfree_skb(skb);
607 skb = nskb;
608 }
609 data = skb_put_zero(skb, needed);
610 }
611
612 /* fill descriptor */
613 p = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
614 if (unlikely(dma_mapping_error(dev, p))) {
615 dev_kfree_skb(skb);
616 ret = NETDEV_TX_OK;
617 goto out_unlock;
618 }
619
620 /* point to the next available desc */
621 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
622 priv->tx_skb[priv->tx_curr_desc] = skb;
623 desc->address = p;
624
625 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
626 len_stat |= DMADESC_ESOP_MASK | DMADESC_APPEND_CRC |
627 DMADESC_OWNER_MASK;
628
629 priv->tx_curr_desc++;
630 if (priv->tx_curr_desc == priv->tx_ring_size) {
631 priv->tx_curr_desc = 0;
632 len_stat |= DMADESC_WRAP_MASK;
633 }
634 priv->tx_desc_count--;
635
636 /* dma might be already polling, make sure we update desc
637 * fields in correct order */
638 wmb();
639 desc->len_stat = len_stat;
640 wmb();
641
642 netdev_sent_queue(ndev, skb->len);
643
644 /* kick tx dma */
645 dmac_writel(priv, priv->dma_chan_en_mask, DMAC_CHANCFG_REG,
646 priv->tx_chan);
647
648 /* stop queue if no more desc available */
649 if (!priv->tx_desc_count)
650 netif_stop_queue(ndev);
651
652 ndev->stats.tx_bytes += skb->len;
653 ndev->stats.tx_packets++;
654 ret = NETDEV_TX_OK;
655
656 out_unlock:
657 spin_unlock(&priv->tx_lock);
658 return ret;
659 }
660
661 /*
662 * disable dma in given channel
663 */
664 static void bcm6368_enetsw_disable_dma(struct bcm6368_enetsw *priv, int chan)
665 {
666 int limit = 1000;
667
668 dmac_writel(priv, 0, DMAC_CHANCFG_REG, chan);
669
670 do {
671 u32 val;
672
673 val = dma_readl(priv, DMAC_CHANCFG_REG, chan);
674 if (!(val & DMAC_CHANCFG_EN_MASK))
675 break;
676
677 udelay(1);
678 } while (limit--);
679 }
680
681 static int bcm6368_enetsw_open(struct net_device *ndev)
682 {
683 struct bcm6368_enetsw *priv = netdev_priv(ndev);
684 struct platform_device *pdev = priv->pdev;
685 struct device *dev = &pdev->dev;
686 int i, ret;
687 unsigned int size;
688 void *p;
689 u32 val;
690
691 /* mask all interrupts and request them */
692 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
693 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
694
695 ret = request_irq(priv->irq_rx, bcm6368_enetsw_isr_dma,
696 0, ndev->name, ndev);
697 if (ret)
698 goto out_freeirq;
699
700 if (priv->irq_tx != -1) {
701 ret = request_irq(priv->irq_tx, bcm6368_enetsw_isr_dma,
702 0, ndev->name, ndev);
703 if (ret)
704 goto out_freeirq_rx;
705 }
706
707 /* allocate rx dma ring */
708 size = priv->rx_ring_size * sizeof(struct bcm6368_enetsw_desc);
709 p = dma_alloc_coherent(dev, size, &priv->rx_desc_dma, GFP_KERNEL);
710 if (!p) {
711 dev_err(dev, "cannot allocate rx ring %u\n", size);
712 ret = -ENOMEM;
713 goto out_freeirq_tx;
714 }
715
716 memset(p, 0, size);
717 priv->rx_desc_alloc_size = size;
718 priv->rx_desc_cpu = p;
719
720 /* allocate tx dma ring */
721 size = priv->tx_ring_size * sizeof(struct bcm6368_enetsw_desc);
722 p = dma_alloc_coherent(dev, size, &priv->tx_desc_dma, GFP_KERNEL);
723 if (!p) {
724 dev_err(dev, "cannot allocate tx ring\n");
725 ret = -ENOMEM;
726 goto out_free_rx_ring;
727 }
728
729 memset(p, 0, size);
730 priv->tx_desc_alloc_size = size;
731 priv->tx_desc_cpu = p;
732
733 priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
734 GFP_KERNEL);
735 if (!priv->tx_skb) {
736 dev_err(dev, "cannot allocate tx skb queue\n");
737 ret = -ENOMEM;
738 goto out_free_tx_ring;
739 }
740
741 priv->tx_desc_count = priv->tx_ring_size;
742 priv->tx_dirty_desc = 0;
743 priv->tx_curr_desc = 0;
744 spin_lock_init(&priv->tx_lock);
745
746 /* init & fill rx ring with buffers */
747 priv->rx_buf = kzalloc(sizeof(unsigned char *) * priv->rx_ring_size,
748 GFP_KERNEL);
749 if (!priv->rx_buf) {
750 dev_err(dev, "cannot allocate rx buffer queue\n");
751 ret = -ENOMEM;
752 goto out_free_tx_skb;
753 }
754
755 priv->rx_desc_count = 0;
756 priv->rx_dirty_desc = 0;
757 priv->rx_curr_desc = 0;
758
759 /* initialize flow control buffer allocation */
760 dma_writel(priv, DMA_BUFALLOC_FORCE_MASK | 0,
761 DMA_BUFALLOC_REG(priv->rx_chan));
762
763 if (bcm6368_enetsw_refill_rx(ndev, false)) {
764 dev_err(dev, "cannot allocate rx buffer queue\n");
765 ret = -ENOMEM;
766 goto out;
767 }
768
769 /* write rx & tx ring addresses */
770 dmas_writel(priv, priv->rx_desc_dma,
771 DMAS_RSTART_REG, priv->rx_chan);
772 dmas_writel(priv, priv->tx_desc_dma,
773 DMAS_RSTART_REG, priv->tx_chan);
774
775 /* clear remaining state ram for rx & tx channel */
776 dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->rx_chan);
777 dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->tx_chan);
778 dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->rx_chan);
779 dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->tx_chan);
780 dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->rx_chan);
781 dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->tx_chan);
782
783 /* set dma maximum burst len */
784 dmac_writel(priv, priv->dma_maxburst,
785 DMAC_MAXBURST_REG, priv->rx_chan);
786 dmac_writel(priv, priv->dma_maxburst,
787 DMAC_MAXBURST_REG, priv->tx_chan);
788
789 /* set flow control low/high threshold to 1/3 / 2/3 */
790 val = priv->rx_ring_size / 3;
791 dma_writel(priv, val, DMA_FLOWCL_REG(priv->rx_chan));
792 val = (priv->rx_ring_size * 2) / 3;
793 dma_writel(priv, val, DMA_FLOWCH_REG(priv->rx_chan));
794
795 /* all set, enable mac and interrupts, start dma engine and
796 * kick rx dma channel
797 */
798 wmb();
799 dma_writel(priv, DMA_CFG_EN_MASK, DMA_CFG_REG);
800 dmac_writel(priv, DMAC_CHANCFG_EN_MASK,
801 DMAC_CHANCFG_REG, priv->rx_chan);
802
803 /* watch "packet transferred" interrupt in rx and tx */
804 dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
805 DMAC_IR_REG, priv->rx_chan);
806 dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
807 DMAC_IR_REG, priv->tx_chan);
808
809 /* make sure we enable napi before rx interrupt */
810 napi_enable(&priv->napi);
811
812 dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
813 DMAC_IRMASK_REG, priv->rx_chan);
814 dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
815 DMAC_IRMASK_REG, priv->tx_chan);
816
817 netif_carrier_on(ndev);
818 netif_start_queue(ndev);
819
820 return 0;
821
822 out:
823 for (i = 0; i < priv->rx_ring_size; i++) {
824 struct bcm6368_enetsw_desc *desc;
825
826 if (!priv->rx_buf[i])
827 continue;
828
829 desc = &priv->rx_desc_cpu[i];
830 dma_unmap_single(dev, desc->address, priv->rx_buf_size,
831 DMA_FROM_DEVICE);
832 skb_free_frag(priv->rx_buf[i]);
833 }
834 kfree(priv->rx_buf);
835
836 out_free_tx_skb:
837 kfree(priv->tx_skb);
838
839 out_free_tx_ring:
840 dma_free_coherent(dev, priv->tx_desc_alloc_size,
841 priv->tx_desc_cpu, priv->tx_desc_dma);
842
843 out_free_rx_ring:
844 dma_free_coherent(dev, priv->rx_desc_alloc_size,
845 priv->rx_desc_cpu, priv->rx_desc_dma);
846
847 out_freeirq_tx:
848 if (priv->irq_tx != -1)
849 free_irq(priv->irq_tx, ndev);
850
851 out_freeirq_rx:
852 free_irq(priv->irq_rx, ndev);
853
854 out_freeirq:
855 return ret;
856 }
857
858 static int bcm6368_enetsw_stop(struct net_device *ndev)
859 {
860 struct bcm6368_enetsw *priv = netdev_priv(ndev);
861 struct platform_device *pdev = priv->pdev;
862 struct device *dev = &pdev->dev;
863 int i;
864
865 netif_stop_queue(ndev);
866 napi_disable(&priv->napi);
867 del_timer_sync(&priv->rx_timeout);
868
869 /* mask all interrupts */
870 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
871 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
872
873 /* disable dma & mac */
874 bcm6368_enetsw_disable_dma(priv, priv->tx_chan);
875 bcm6368_enetsw_disable_dma(priv, priv->rx_chan);
876
877 /* force reclaim of all tx buffers */
878 bcm6368_enetsw_tx_reclaim(ndev, 1, 0);
879
880 /* free the rx buffer ring */
881 for (i = 0; i < priv->rx_ring_size; i++) {
882 struct bcm6368_enetsw_desc *desc;
883
884 if (!priv->rx_buf[i])
885 continue;
886
887 desc = &priv->rx_desc_cpu[i];
888 dma_unmap_single_attrs(dev, desc->address, priv->rx_buf_size,
889 DMA_FROM_DEVICE,
890 DMA_ATTR_SKIP_CPU_SYNC);
891 skb_free_frag(priv->rx_buf[i]);
892 }
893
894 /* free remaining allocated memory */
895 kfree(priv->rx_buf);
896 kfree(priv->tx_skb);
897 dma_free_coherent(dev, priv->rx_desc_alloc_size,
898 priv->rx_desc_cpu, priv->rx_desc_dma);
899 dma_free_coherent(dev, priv->tx_desc_alloc_size,
900 priv->tx_desc_cpu, priv->tx_desc_dma);
901 if (priv->irq_tx != -1)
902 free_irq(priv->irq_tx, ndev);
903 free_irq(priv->irq_rx, ndev);
904
905 netdev_reset_queue(ndev);
906
907 return 0;
908 }
909
910 static const struct net_device_ops bcm6368_enetsw_ops = {
911 .ndo_open = bcm6368_enetsw_open,
912 .ndo_stop = bcm6368_enetsw_stop,
913 .ndo_start_xmit = bcm6368_enetsw_start_xmit,
914 };
915
916 static int bcm6368_enetsw_probe(struct platform_device *pdev)
917 {
918 struct bcm6368_enetsw *priv;
919 struct device *dev = &pdev->dev;
920 struct device_node *node = dev->of_node;
921 struct net_device *ndev;
922 struct resource *res;
923 unsigned i;
924 int ret;
925
926 ndev = alloc_etherdev(sizeof(*priv));
927 if (!ndev)
928 return -ENOMEM;
929
930 priv = netdev_priv(ndev);
931
932 priv->num_pms = of_count_phandle_with_args(node, "power-domains",
933 "#power-domain-cells");
934 if (priv->num_pms > 1) {
935 priv->pm = devm_kcalloc(dev, priv->num_pms,
936 sizeof(struct device *), GFP_KERNEL);
937 if (!priv->pm)
938 return -ENOMEM;
939
940 priv->link_pm = devm_kcalloc(dev, priv->num_pms,
941 sizeof(struct device_link *),
942 GFP_KERNEL);
943 if (!priv->link_pm)
944 return -ENOMEM;
945
946 for (i = 0; i < priv->num_pms; i++) {
947 priv->pm[i] = genpd_dev_pm_attach_by_id(dev, i);
948 if (IS_ERR(priv->pm[i])) {
949 dev_err(dev, "error getting pm %d\n", i);
950 return -EINVAL;
951 }
952
953 priv->link_pm[i] = device_link_add(dev, priv->pm[i],
954 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
955 DL_FLAG_RPM_ACTIVE);
956 }
957 }
958
959 pm_runtime_enable(dev);
960 pm_runtime_no_callbacks(dev);
961 ret = pm_runtime_get_sync(dev);
962 if (ret < 0) {
963 pm_runtime_disable(dev);
964 dev_info(dev, "PM prober defer: ret=%d\n", ret);
965 return -EPROBE_DEFER;
966 }
967
968 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
969 priv->dma_base = devm_ioremap_resource(dev, res);
970 if (IS_ERR(priv->dma_base))
971 return PTR_ERR(priv->dma_base);
972
973 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
974 "dma-channels");
975 priv->dma_chan = devm_ioremap_resource(dev, res);
976 if (IS_ERR(priv->dma_chan))
977 return PTR_ERR(priv->dma_chan);
978
979 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma-sram");
980 priv->dma_sram = devm_ioremap_resource(dev, res);
981 if (IS_ERR(priv->dma_sram))
982 return PTR_ERR(priv->dma_sram);
983
984 priv->irq_rx = platform_get_irq_byname(pdev, "rx");
985 if (!priv->irq_rx)
986 return -ENODEV;
987
988 priv->irq_tx = platform_get_irq_byname(pdev, "tx");
989 if (!priv->irq_tx)
990 return -ENODEV;
991 else if (priv->irq_tx < 0)
992 priv->irq_tx = -1;
993
994 if (device_property_read_u32(dev, "dma-rx", &priv->rx_chan))
995 return -ENODEV;
996
997 if (device_property_read_u32(dev, "dma-tx", &priv->tx_chan))
998 return -ENODEV;
999
1000 priv->rx_ring_size = ENETSW_DEF_RX_DESC;
1001 priv->tx_ring_size = ENETSW_DEF_TX_DESC;
1002
1003 priv->dma_maxburst = ENETSW_DMA_MAXBURST;
1004
1005 priv->copybreak = ENETSW_DEF_CPY_BREAK;
1006
1007 priv->dma_chan_en_mask = DMAC_CHANCFG_EN_MASK;
1008 priv->dma_chan_int_mask = DMAC_IR_PKTDONE_MASK;
1009 priv->dma_chan_width = DMA_CHAN_WIDTH;
1010
1011 of_get_mac_address(node, ndev->dev_addr);
1012 if (is_valid_ether_addr(ndev->dev_addr)) {
1013 dev_info(dev, "mtd mac %pM\n", ndev->dev_addr);
1014 } else {
1015 random_ether_addr(ndev->dev_addr);
1016 dev_info(dev, "random mac %pM\n", ndev->dev_addr);
1017 }
1018
1019 priv->rx_buf_size = ALIGN(ndev->mtu + ENETSW_MTU_OVERHEAD,
1020 priv->dma_maxburst * 4);
1021
1022 priv->rx_frag_size = ENETSW_FRAG_SIZE(priv->rx_buf_size);
1023
1024 priv->num_clocks = of_clk_get_parent_count(node);
1025 if (priv->num_clocks) {
1026 priv->clock = devm_kcalloc(dev, priv->num_clocks,
1027 sizeof(struct clk *), GFP_KERNEL);
1028 if (!priv->clock)
1029 return -ENOMEM;
1030 }
1031 for (i = 0; i < priv->num_clocks; i++) {
1032 priv->clock[i] = of_clk_get(node, i);
1033 if (IS_ERR(priv->clock[i])) {
1034 dev_err(dev, "error getting clock %d\n", i);
1035 return -EINVAL;
1036 }
1037
1038 ret = clk_prepare_enable(priv->clock[i]);
1039 if (ret) {
1040 dev_err(dev, "error enabling clock %d\n", i);
1041 return ret;
1042 }
1043 }
1044
1045 priv->num_resets = of_count_phandle_with_args(node, "resets",
1046 "#reset-cells");
1047 if (priv->num_resets) {
1048 priv->reset = devm_kcalloc(dev, priv->num_resets,
1049 sizeof(struct reset_control *),
1050 GFP_KERNEL);
1051 if (!priv->reset)
1052 return -ENOMEM;
1053 }
1054 for (i = 0; i < priv->num_resets; i++) {
1055 priv->reset[i] = devm_reset_control_get_by_index(dev, i);
1056 if (IS_ERR(priv->reset[i])) {
1057 dev_err(dev, "error getting reset %d\n", i);
1058 return -EINVAL;
1059 }
1060
1061 ret = reset_control_reset(priv->reset[i]);
1062 if (ret) {
1063 dev_err(dev, "error performing reset %d\n", i);
1064 return ret;
1065 }
1066 }
1067
1068 spin_lock_init(&priv->rx_lock);
1069
1070 timer_setup(&priv->rx_timeout, bcm6368_enetsw_refill_rx_timer, 0);
1071
1072 /* register netdevice */
1073 ndev->netdev_ops = &bcm6368_enetsw_ops;
1074 ndev->min_mtu = ETH_ZLEN;
1075 ndev->mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1076 ndev->max_mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1077 netif_napi_add(ndev, &priv->napi, bcm6368_enetsw_poll, 16);
1078 SET_NETDEV_DEV(ndev, dev);
1079
1080 ret = register_netdev(ndev);
1081 if (ret)
1082 goto out_disable_clk;
1083
1084 netif_carrier_off(ndev);
1085 platform_set_drvdata(pdev, ndev);
1086 priv->pdev = pdev;
1087 priv->net_dev = ndev;
1088
1089 return 0;
1090
1091 out_disable_clk:
1092 for (i = 0; i < priv->num_resets; i++)
1093 reset_control_assert(priv->reset[i]);
1094
1095 for (i = 0; i < priv->num_clocks; i++)
1096 clk_disable_unprepare(priv->clock[i]);
1097
1098 return ret;
1099 }
1100
1101 static int bcm6368_enetsw_remove(struct platform_device *pdev)
1102 {
1103 struct device *dev = &pdev->dev;
1104 struct net_device *ndev = platform_get_drvdata(pdev);
1105 struct bcm6368_enetsw *priv = netdev_priv(ndev);
1106 unsigned int i;
1107
1108 unregister_netdev(ndev);
1109
1110 pm_runtime_put_sync(dev);
1111 for (i = 0; priv->pm && i < priv->num_pms; i++) {
1112 dev_pm_domain_detach(priv->pm[i], true);
1113 device_link_del(priv->link_pm[i]);
1114 }
1115
1116 for (i = 0; i < priv->num_resets; i++)
1117 reset_control_assert(priv->reset[i]);
1118
1119 for (i = 0; i < priv->num_clocks; i++)
1120 clk_disable_unprepare(priv->clock[i]);
1121
1122 free_netdev(ndev);
1123
1124 return 0;
1125 }
1126
1127 static const struct of_device_id bcm6368_enetsw_of_match[] = {
1128 { .compatible = "brcm,bcm6318-enetsw", },
1129 { .compatible = "brcm,bcm6328-enetsw", },
1130 { .compatible = "brcm,bcm6362-enetsw", },
1131 { .compatible = "brcm,bcm6368-enetsw", },
1132 { .compatible = "brcm,bcm63268-enetsw", },
1133 { /* sentinel */ }
1134 };
1135 MODULE_DEVICE_TABLE(of, bcm6368_enetsw_of_match);
1136
1137 static struct platform_driver bcm6368_enetsw_driver = {
1138 .driver = {
1139 .name = "bcm6368-enetsw",
1140 .of_match_table = of_match_ptr(bcm6368_enetsw_of_match),
1141 },
1142 .probe = bcm6368_enetsw_probe,
1143 .remove = bcm6368_enetsw_remove,
1144 };
1145 module_platform_driver(bcm6368_enetsw_driver);
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