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[openwrt/staging/dedeckeh.git] / target / linux / bmips / files / drivers / net / ethernet / broadcom / bcm6368-enetsw.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * BCM6368 Ethernet Switch Controller Driver
4 *
5 * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
6 * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
8 */
9
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/ethtool.h>
15 #include <linux/if_vlan.h>
16 #include <linux/interrupt.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_net.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
23
24 /* MTU */
25 #define ENETSW_TAG_SIZE 6
26 #define ENETSW_MTU_OVERHEAD (VLAN_ETH_HLEN + VLAN_HLEN + \
27 ENETSW_TAG_SIZE)
28 #define ENETSW_FRAG_SIZE(x) (SKB_DATA_ALIGN(NET_SKB_PAD + x + \
29 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
30
31 /* default number of descriptor */
32 #define ENETSW_DEF_RX_DESC 64
33 #define ENETSW_DEF_TX_DESC 32
34 #define ENETSW_DEF_CPY_BREAK 128
35
36 /* maximum burst len for dma (4 bytes unit) */
37 #define ENETSW_DMA_MAXBURST 8
38
39 /* DMA channels */
40 #define DMA_CHAN_WIDTH 0x10
41
42 /* Controller Configuration Register */
43 #define DMA_CFG_REG 0x0
44 #define DMA_CFG_EN_SHIFT 0
45 #define DMA_CFG_EN_MASK (1 << DMA_CFG_EN_SHIFT)
46 #define DMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
47
48 /* Flow Control Descriptor Low Threshold register */
49 #define DMA_FLOWCL_REG(x) (0x4 + (x) * 6)
50
51 /* Flow Control Descriptor High Threshold register */
52 #define DMA_FLOWCH_REG(x) (0x8 + (x) * 6)
53
54 /* Flow Control Descriptor Buffer Alloca Threshold register */
55 #define DMA_BUFALLOC_REG(x) (0xc + (x) * 6)
56 #define DMA_BUFALLOC_FORCE_SHIFT 31
57 #define DMA_BUFALLOC_FORCE_MASK (1 << DMA_BUFALLOC_FORCE_SHIFT)
58
59 /* Channel Configuration register */
60 #define DMAC_CHANCFG_REG 0x0
61 #define DMAC_CHANCFG_EN_SHIFT 0
62 #define DMAC_CHANCFG_EN_MASK (1 << DMAC_CHANCFG_EN_SHIFT)
63 #define DMAC_CHANCFG_PKTHALT_SHIFT 1
64 #define DMAC_CHANCFG_PKTHALT_MASK (1 << DMAC_CHANCFG_PKTHALT_SHIFT)
65 #define DMAC_CHANCFG_BUFHALT_SHIFT 2
66 #define DMAC_CHANCFG_BUFHALT_MASK (1 << DMAC_CHANCFG_BUFHALT_SHIFT)
67 #define DMAC_CHANCFG_CHAINING_SHIFT 2
68 #define DMAC_CHANCFG_CHAINING_MASK (1 << DMAC_CHANCFG_CHAINING_SHIFT)
69 #define DMAC_CHANCFG_WRAP_EN_SHIFT 3
70 #define DMAC_CHANCFG_WRAP_EN_MASK (1 << DMAC_CHANCFG_WRAP_EN_SHIFT)
71 #define DMAC_CHANCFG_FLOWC_EN_SHIFT 4
72 #define DMAC_CHANCFG_FLOWC_EN_MASK (1 << DMAC_CHANCFG_FLOWC_EN_SHIFT)
73
74 /* Interrupt Control/Status register */
75 #define DMAC_IR_REG 0x4
76 #define DMAC_IR_BUFDONE_MASK (1 << 0)
77 #define DMAC_IR_PKTDONE_MASK (1 << 1)
78 #define DMAC_IR_NOTOWNER_MASK (1 << 2)
79
80 /* Interrupt Mask register */
81 #define DMAC_IRMASK_REG 0x8
82
83 /* Maximum Burst Length */
84 #define DMAC_MAXBURST_REG 0xc
85
86 /* Ring Start Address register */
87 #define DMAS_RSTART_REG 0x0
88
89 /* State Ram Word 2 */
90 #define DMAS_SRAM2_REG 0x4
91
92 /* State Ram Word 3 */
93 #define DMAS_SRAM3_REG 0x8
94
95 /* State Ram Word 4 */
96 #define DMAS_SRAM4_REG 0xc
97
98 struct bcm6368_enetsw_desc {
99 u32 len_stat;
100 u32 address;
101 };
102
103 /* control */
104 #define DMADESC_LENGTH_SHIFT 16
105 #define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT)
106 #define DMADESC_OWNER_MASK (1 << 15)
107 #define DMADESC_EOP_MASK (1 << 14)
108 #define DMADESC_SOP_MASK (1 << 13)
109 #define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
110 #define DMADESC_WRAP_MASK (1 << 12)
111 #define DMADESC_USB_NOZERO_MASK (1 << 1)
112 #define DMADESC_USB_ZERO_MASK (1 << 0)
113
114 /* status */
115 #define DMADESC_UNDER_MASK (1 << 9)
116 #define DMADESC_APPEND_CRC (1 << 8)
117 #define DMADESC_OVSIZE_MASK (1 << 4)
118 #define DMADESC_RXER_MASK (1 << 2)
119 #define DMADESC_CRC_MASK (1 << 1)
120 #define DMADESC_OV_MASK (1 << 0)
121 #define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \
122 DMADESC_OVSIZE_MASK | \
123 DMADESC_RXER_MASK | \
124 DMADESC_CRC_MASK | \
125 DMADESC_OV_MASK)
126
127 struct bcm6368_enetsw {
128 void __iomem *dma_base;
129 void __iomem *dma_chan;
130 void __iomem *dma_sram;
131
132 struct device **pm;
133 struct device_link **link_pm;
134 int num_pms;
135
136 struct clk **clock;
137 unsigned int num_clocks;
138
139 struct reset_control **reset;
140 unsigned int num_resets;
141
142 int copybreak;
143
144 int irq_rx;
145 int irq_tx;
146
147 /* hw view of rx & tx dma ring */
148 dma_addr_t rx_desc_dma;
149 dma_addr_t tx_desc_dma;
150
151 /* allocated size (in bytes) for rx & tx dma ring */
152 unsigned int rx_desc_alloc_size;
153 unsigned int tx_desc_alloc_size;
154
155 struct napi_struct napi;
156
157 /* dma channel id for rx */
158 int rx_chan;
159
160 /* number of dma desc in rx ring */
161 int rx_ring_size;
162
163 /* cpu view of rx dma ring */
164 struct bcm6368_enetsw_desc *rx_desc_cpu;
165
166 /* current number of armed descriptor given to hardware for rx */
167 int rx_desc_count;
168
169 /* next rx descriptor to fetch from hardware */
170 int rx_curr_desc;
171
172 /* next dirty rx descriptor to refill */
173 int rx_dirty_desc;
174
175 /* size of allocated rx buffer */
176 unsigned int rx_buf_size;
177
178 /* size of allocated rx frag */
179 unsigned int rx_frag_size;
180
181 /* list of buffer given to hw for rx */
182 unsigned char **rx_buf;
183
184 /* used when rx buffer allocation failed, so we defer rx queue
185 * refill */
186 struct timer_list rx_timeout;
187
188 /* lock rx_timeout against rx normal operation */
189 spinlock_t rx_lock;
190
191 /* dma channel id for tx */
192 int tx_chan;
193
194 /* number of dma desc in tx ring */
195 int tx_ring_size;
196
197 /* maximum dma burst size */
198 int dma_maxburst;
199
200 /* cpu view of rx dma ring */
201 struct bcm6368_enetsw_desc *tx_desc_cpu;
202
203 /* number of available descriptor for tx */
204 int tx_desc_count;
205
206 /* next tx descriptor avaiable */
207 int tx_curr_desc;
208
209 /* next dirty tx descriptor to reclaim */
210 int tx_dirty_desc;
211
212 /* list of skb given to hw for tx */
213 struct sk_buff **tx_skb;
214
215 /* lock used by tx reclaim and xmit */
216 spinlock_t tx_lock;
217
218 /* network device reference */
219 struct net_device *net_dev;
220
221 /* platform device reference */
222 struct platform_device *pdev;
223
224 /* dma channel enable mask */
225 u32 dma_chan_en_mask;
226
227 /* dma channel interrupt mask */
228 u32 dma_chan_int_mask;
229
230 /* dma channel width */
231 unsigned int dma_chan_width;
232 };
233
234 static inline void dma_writel(struct bcm6368_enetsw *priv, u32 val, u32 off)
235 {
236 __raw_writel(val, priv->dma_base + off);
237 }
238
239 static inline u32 dma_readl(struct bcm6368_enetsw *priv, u32 off, int chan)
240 {
241 return __raw_readl(priv->dma_chan + off + chan * priv->dma_chan_width);
242 }
243
244 static inline void dmac_writel(struct bcm6368_enetsw *priv, u32 val,
245 u32 off, int chan)
246 {
247 __raw_writel(val, priv->dma_chan + off + chan * priv->dma_chan_width);
248 }
249
250 static inline void dmas_writel(struct bcm6368_enetsw *priv, u32 val,
251 u32 off, int chan)
252 {
253 __raw_writel(val, priv->dma_sram + off + chan * priv->dma_chan_width);
254 }
255
256 /*
257 * refill rx queue
258 */
259 static int bcm6368_enetsw_refill_rx(struct net_device *dev)
260 {
261 struct bcm6368_enetsw *priv = netdev_priv(dev);
262
263 while (priv->rx_desc_count < priv->rx_ring_size) {
264 struct bcm6368_enetsw_desc *desc;
265 int desc_idx;
266 u32 len_stat;
267
268 desc_idx = priv->rx_dirty_desc;
269 desc = &priv->rx_desc_cpu[desc_idx];
270
271 if (!priv->rx_buf[desc_idx]) {
272 unsigned char *buf =
273 netdev_alloc_frag(priv->rx_frag_size);
274
275 if (unlikely(!buf))
276 break;
277
278 priv->rx_buf[desc_idx] = buf;
279 desc->address = dma_map_single(&priv->pdev->dev,
280 buf + NET_SKB_PAD,
281 priv->rx_buf_size,
282 DMA_FROM_DEVICE);
283 }
284
285 len_stat = priv->rx_buf_size << DMADESC_LENGTH_SHIFT;
286 len_stat |= DMADESC_OWNER_MASK;
287 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
288 len_stat |= DMADESC_WRAP_MASK;
289 priv->rx_dirty_desc = 0;
290 } else {
291 priv->rx_dirty_desc++;
292 }
293 wmb();
294 desc->len_stat = len_stat;
295
296 priv->rx_desc_count++;
297
298 /* tell dma engine we allocated one buffer */
299 dma_writel(priv, 1, DMA_BUFALLOC_REG(priv->rx_chan));
300 }
301
302 /* If rx ring is still empty, set a timer to try allocating
303 * again at a later time. */
304 if (priv->rx_desc_count == 0 && netif_running(dev)) {
305 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
306 priv->rx_timeout.expires = jiffies + HZ;
307 add_timer(&priv->rx_timeout);
308 }
309
310 return 0;
311 }
312
313 /*
314 * timer callback to defer refill rx queue in case we're OOM
315 */
316 static void bcm6368_enetsw_refill_rx_timer(struct timer_list *t)
317 {
318 struct bcm6368_enetsw *priv = from_timer(priv, t, rx_timeout);
319 struct net_device *dev = priv->net_dev;
320
321 spin_lock(&priv->rx_lock);
322 bcm6368_enetsw_refill_rx(dev);
323 spin_unlock(&priv->rx_lock);
324 }
325
326 /*
327 * extract packet from rx queue
328 */
329 static int bcm6368_enetsw_receive_queue(struct net_device *dev, int budget)
330 {
331 struct bcm6368_enetsw *priv = netdev_priv(dev);
332 struct device *kdev = &priv->pdev->dev;
333 int processed = 0;
334
335 /* don't scan ring further than number of refilled
336 * descriptor */
337 if (budget > priv->rx_desc_count)
338 budget = priv->rx_desc_count;
339
340 do {
341 struct bcm6368_enetsw_desc *desc;
342 unsigned int frag_size;
343 struct sk_buff *skb;
344 unsigned char *buf;
345 int desc_idx;
346 u32 len_stat;
347 unsigned int len;
348
349 desc_idx = priv->rx_curr_desc;
350 desc = &priv->rx_desc_cpu[desc_idx];
351
352 /* make sure we actually read the descriptor status at
353 * each loop */
354 rmb();
355
356 len_stat = desc->len_stat;
357
358 /* break if dma ownership belongs to hw */
359 if (len_stat & DMADESC_OWNER_MASK)
360 break;
361
362 processed++;
363 priv->rx_curr_desc++;
364 if (priv->rx_curr_desc == priv->rx_ring_size)
365 priv->rx_curr_desc = 0;
366 priv->rx_desc_count--;
367
368 /* if the packet does not have start of packet _and_
369 * end of packet flag set, then just recycle it */
370 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
371 dev->stats.rx_dropped++;
372 continue;
373 }
374
375 /* valid packet */
376 buf = priv->rx_buf[desc_idx];
377 len = (len_stat & DMADESC_LENGTH_MASK)
378 >> DMADESC_LENGTH_SHIFT;
379 /* don't include FCS */
380 len -= 4;
381
382 if (len < priv->copybreak) {
383 unsigned int nfrag_size = ENETSW_FRAG_SIZE(len);
384 unsigned char *nbuf = napi_alloc_frag(nfrag_size);
385
386 if (unlikely(!nbuf)) {
387 /* forget packet, just rearm desc */
388 dev->stats.rx_dropped++;
389 continue;
390 }
391
392 dma_sync_single_for_cpu(kdev, desc->address,
393 len, DMA_FROM_DEVICE);
394 memcpy(nbuf + NET_SKB_PAD, buf + NET_SKB_PAD, len);
395 dma_sync_single_for_device(kdev, desc->address,
396 len, DMA_FROM_DEVICE);
397 buf = nbuf;
398 frag_size = nfrag_size;
399 } else {
400 dma_unmap_single(kdev, desc->address,
401 priv->rx_buf_size, DMA_FROM_DEVICE);
402 priv->rx_buf[desc_idx] = NULL;
403 frag_size = priv->rx_frag_size;
404 }
405
406 skb = build_skb(buf, frag_size);
407 if (unlikely(!skb)) {
408 skb_free_frag(buf);
409 dev->stats.rx_dropped++;
410 continue;
411 }
412
413 skb_reserve(skb, NET_SKB_PAD);
414 skb_put(skb, len);
415 skb->protocol = eth_type_trans(skb, dev);
416 dev->stats.rx_packets++;
417 dev->stats.rx_bytes += len;
418 netif_receive_skb(skb);
419 } while (--budget > 0);
420
421 if (processed || !priv->rx_desc_count) {
422 bcm6368_enetsw_refill_rx(dev);
423
424 /* kick rx dma */
425 dmac_writel(priv, priv->dma_chan_en_mask,
426 DMAC_CHANCFG_REG, priv->rx_chan);
427 }
428
429 return processed;
430 }
431
432 /*
433 * try to or force reclaim of transmitted buffers
434 */
435 static int bcm6368_enetsw_tx_reclaim(struct net_device *dev, int force)
436 {
437 struct bcm6368_enetsw *priv = netdev_priv(dev);
438 int released = 0;
439
440 while (priv->tx_desc_count < priv->tx_ring_size) {
441 struct bcm6368_enetsw_desc *desc;
442 struct sk_buff *skb;
443
444 /* We run in a bh and fight against start_xmit, which
445 * is called with bh disabled */
446 spin_lock(&priv->tx_lock);
447
448 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
449
450 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
451 spin_unlock(&priv->tx_lock);
452 break;
453 }
454
455 /* ensure other field of the descriptor were not read
456 * before we checked ownership */
457 rmb();
458
459 skb = priv->tx_skb[priv->tx_dirty_desc];
460 priv->tx_skb[priv->tx_dirty_desc] = NULL;
461 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
462 DMA_TO_DEVICE);
463
464 priv->tx_dirty_desc++;
465 if (priv->tx_dirty_desc == priv->tx_ring_size)
466 priv->tx_dirty_desc = 0;
467 priv->tx_desc_count++;
468
469 spin_unlock(&priv->tx_lock);
470
471 if (desc->len_stat & DMADESC_UNDER_MASK)
472 dev->stats.tx_errors++;
473
474 dev_kfree_skb(skb);
475 released++;
476 }
477
478 if (netif_queue_stopped(dev) && released)
479 netif_wake_queue(dev);
480
481 return released;
482 }
483
484 /*
485 * poll func, called by network core
486 */
487 static int bcm6368_enetsw_poll(struct napi_struct *napi, int budget)
488 {
489 struct bcm6368_enetsw *priv = container_of(napi, struct bcm6368_enetsw, napi);
490 struct net_device *dev = priv->net_dev;
491 int rx_work_done;
492
493 /* ack interrupts */
494 dmac_writel(priv, priv->dma_chan_int_mask,
495 DMAC_IR_REG, priv->rx_chan);
496 dmac_writel(priv, priv->dma_chan_int_mask,
497 DMAC_IR_REG, priv->tx_chan);
498
499 /* reclaim sent skb */
500 bcm6368_enetsw_tx_reclaim(dev, 0);
501
502 spin_lock(&priv->rx_lock);
503 rx_work_done = bcm6368_enetsw_receive_queue(dev, budget);
504 spin_unlock(&priv->rx_lock);
505
506 if (rx_work_done >= budget) {
507 /* rx queue is not yet empty/clean */
508 return rx_work_done;
509 }
510
511 /* no more packet in rx/tx queue, remove device from poll
512 * queue */
513 napi_complete_done(napi, rx_work_done);
514
515 /* restore rx/tx interrupt */
516 dmac_writel(priv, priv->dma_chan_int_mask,
517 DMAC_IRMASK_REG, priv->rx_chan);
518 dmac_writel(priv, priv->dma_chan_int_mask,
519 DMAC_IRMASK_REG, priv->tx_chan);
520
521 return rx_work_done;
522 }
523
524 /*
525 * rx/tx dma interrupt handler
526 */
527 static irqreturn_t bcm6368_enetsw_isr_dma(int irq, void *dev_id)
528 {
529 struct net_device *dev = dev_id;
530 struct bcm6368_enetsw *priv = netdev_priv(dev);
531
532 /* mask rx/tx interrupts */
533 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
534 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
535
536 napi_schedule(&priv->napi);
537
538 return IRQ_HANDLED;
539 }
540
541 /*
542 * tx request callback
543 */
544 static netdev_tx_t
545 bcm6368_enetsw_start_xmit(struct sk_buff *skb, struct net_device *dev)
546 {
547 struct bcm6368_enetsw *priv = netdev_priv(dev);
548 struct bcm6368_enetsw_desc *desc;
549 u32 len_stat;
550 netdev_tx_t ret;
551
552 /* lock against tx reclaim */
553 spin_lock(&priv->tx_lock);
554
555 /* make sure the tx hw queue is not full, should not happen
556 * since we stop queue before it's the case */
557 if (unlikely(!priv->tx_desc_count)) {
558 netif_stop_queue(dev);
559 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
560 "available?\n");
561 ret = NETDEV_TX_BUSY;
562 goto out_unlock;
563 }
564
565 /* pad small packets */
566 if (skb->len < (ETH_ZLEN + ETH_FCS_LEN)) {
567 int needed = (ETH_ZLEN + ETH_FCS_LEN) - skb->len;
568 char *data;
569
570 if (unlikely(skb_tailroom(skb) < needed)) {
571 struct sk_buff *nskb;
572
573 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
574 if (!nskb) {
575 ret = NETDEV_TX_BUSY;
576 goto out_unlock;
577 }
578
579 dev_kfree_skb(skb);
580 skb = nskb;
581 }
582 data = skb_put_zero(skb, needed);
583 }
584
585 /* point to the next available desc */
586 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
587 priv->tx_skb[priv->tx_curr_desc] = skb;
588
589 /* fill descriptor */
590 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
591 DMA_TO_DEVICE);
592
593 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
594 len_stat |= DMADESC_ESOP_MASK | DMADESC_APPEND_CRC |
595 DMADESC_OWNER_MASK;
596
597 priv->tx_curr_desc++;
598 if (priv->tx_curr_desc == priv->tx_ring_size) {
599 priv->tx_curr_desc = 0;
600 len_stat |= DMADESC_WRAP_MASK;
601 }
602 priv->tx_desc_count--;
603
604 /* dma might be already polling, make sure we update desc
605 * fields in correct order */
606 wmb();
607 desc->len_stat = len_stat;
608 wmb();
609
610 /* kick tx dma */
611 dmac_writel(priv, priv->dma_chan_en_mask, DMAC_CHANCFG_REG,
612 priv->tx_chan);
613
614 /* stop queue if no more desc available */
615 if (!priv->tx_desc_count)
616 netif_stop_queue(dev);
617
618 dev->stats.tx_bytes += skb->len;
619 dev->stats.tx_packets++;
620 ret = NETDEV_TX_OK;
621
622 out_unlock:
623 spin_unlock(&priv->tx_lock);
624 return ret;
625 }
626
627 /*
628 * disable dma in given channel
629 */
630 static void bcm6368_enetsw_disable_dma(struct bcm6368_enetsw *priv, int chan)
631 {
632 int limit = 1000;
633
634 dmac_writel(priv, 0, DMAC_CHANCFG_REG, chan);
635
636 do {
637 u32 val;
638
639 val = dma_readl(priv, DMAC_CHANCFG_REG, chan);
640 if (!(val & DMAC_CHANCFG_EN_MASK))
641 break;
642
643 udelay(1);
644 } while (limit--);
645 }
646
647 static int bcm6368_enetsw_open(struct net_device *dev)
648 {
649 struct bcm6368_enetsw *priv = netdev_priv(dev);
650 struct device *kdev = &priv->pdev->dev;
651 int i, ret;
652 unsigned int size;
653 void *p;
654 u32 val;
655
656 /* mask all interrupts and request them */
657 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
658 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
659
660 ret = request_irq(priv->irq_rx, bcm6368_enetsw_isr_dma,
661 0, dev->name, dev);
662 if (ret)
663 goto out_freeirq;
664
665 if (priv->irq_tx != -1) {
666 ret = request_irq(priv->irq_tx, bcm6368_enetsw_isr_dma,
667 0, dev->name, dev);
668 if (ret)
669 goto out_freeirq_rx;
670 }
671
672 /* allocate rx dma ring */
673 size = priv->rx_ring_size * sizeof(struct bcm6368_enetsw_desc);
674 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
675 if (!p) {
676 dev_err(kdev, "cannot allocate rx ring %u\n", size);
677 ret = -ENOMEM;
678 goto out_freeirq_tx;
679 }
680
681 memset(p, 0, size);
682 priv->rx_desc_alloc_size = size;
683 priv->rx_desc_cpu = p;
684
685 /* allocate tx dma ring */
686 size = priv->tx_ring_size * sizeof(struct bcm6368_enetsw_desc);
687 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
688 if (!p) {
689 dev_err(kdev, "cannot allocate tx ring\n");
690 ret = -ENOMEM;
691 goto out_free_rx_ring;
692 }
693
694 memset(p, 0, size);
695 priv->tx_desc_alloc_size = size;
696 priv->tx_desc_cpu = p;
697
698 priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
699 GFP_KERNEL);
700 if (!priv->tx_skb) {
701 dev_err(kdev, "cannot allocate tx skb queue\n");
702 ret = -ENOMEM;
703 goto out_free_tx_ring;
704 }
705
706 priv->tx_desc_count = priv->tx_ring_size;
707 priv->tx_dirty_desc = 0;
708 priv->tx_curr_desc = 0;
709 spin_lock_init(&priv->tx_lock);
710
711 /* init & fill rx ring with buffers */
712 priv->rx_buf = kzalloc(sizeof(unsigned char *) * priv->rx_ring_size,
713 GFP_KERNEL);
714 if (!priv->rx_buf) {
715 dev_err(kdev, "cannot allocate rx buffer queue\n");
716 ret = -ENOMEM;
717 goto out_free_tx_skb;
718 }
719
720 priv->rx_desc_count = 0;
721 priv->rx_dirty_desc = 0;
722 priv->rx_curr_desc = 0;
723
724 /* initialize flow control buffer allocation */
725 dma_writel(priv, DMA_BUFALLOC_FORCE_MASK | 0,
726 DMA_BUFALLOC_REG(priv->rx_chan));
727
728 if (bcm6368_enetsw_refill_rx(dev)) {
729 dev_err(kdev, "cannot allocate rx buffer queue\n");
730 ret = -ENOMEM;
731 goto out;
732 }
733
734 /* write rx & tx ring addresses */
735 dmas_writel(priv, priv->rx_desc_dma,
736 DMAS_RSTART_REG, priv->rx_chan);
737 dmas_writel(priv, priv->tx_desc_dma,
738 DMAS_RSTART_REG, priv->tx_chan);
739
740 /* clear remaining state ram for rx & tx channel */
741 dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->rx_chan);
742 dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->tx_chan);
743 dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->rx_chan);
744 dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->tx_chan);
745 dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->rx_chan);
746 dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->tx_chan);
747
748 /* set dma maximum burst len */
749 dmac_writel(priv, priv->dma_maxburst,
750 DMAC_MAXBURST_REG, priv->rx_chan);
751 dmac_writel(priv, priv->dma_maxburst,
752 DMAC_MAXBURST_REG, priv->tx_chan);
753
754 /* set flow control low/high threshold to 1/3 / 2/3 */
755 val = priv->rx_ring_size / 3;
756 dma_writel(priv, val, DMA_FLOWCL_REG(priv->rx_chan));
757 val = (priv->rx_ring_size * 2) / 3;
758 dma_writel(priv, val, DMA_FLOWCH_REG(priv->rx_chan));
759
760 /* all set, enable mac and interrupts, start dma engine and
761 * kick rx dma channel
762 */
763 wmb();
764 dma_writel(priv, DMA_CFG_EN_MASK, DMA_CFG_REG);
765 dmac_writel(priv, DMAC_CHANCFG_EN_MASK,
766 DMAC_CHANCFG_REG, priv->rx_chan);
767
768 /* watch "packet transferred" interrupt in rx and tx */
769 dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
770 DMAC_IR_REG, priv->rx_chan);
771 dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
772 DMAC_IR_REG, priv->tx_chan);
773
774 /* make sure we enable napi before rx interrupt */
775 napi_enable(&priv->napi);
776
777 dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
778 DMAC_IRMASK_REG, priv->rx_chan);
779 dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
780 DMAC_IRMASK_REG, priv->tx_chan);
781
782 netif_carrier_on(dev);
783 netif_start_queue(dev);
784
785 return 0;
786
787 out:
788 for (i = 0; i < priv->rx_ring_size; i++) {
789 struct bcm6368_enetsw_desc *desc;
790
791 if (!priv->rx_buf[i])
792 continue;
793
794 desc = &priv->rx_desc_cpu[i];
795 dma_unmap_single(kdev, desc->address, priv->rx_buf_size,
796 DMA_FROM_DEVICE);
797 skb_free_frag(priv->rx_buf[i]);
798 }
799 kfree(priv->rx_buf);
800
801 out_free_tx_skb:
802 kfree(priv->tx_skb);
803
804 out_free_tx_ring:
805 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
806 priv->tx_desc_cpu, priv->tx_desc_dma);
807
808 out_free_rx_ring:
809 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
810 priv->rx_desc_cpu, priv->rx_desc_dma);
811
812 out_freeirq_tx:
813 if (priv->irq_tx != -1)
814 free_irq(priv->irq_tx, dev);
815
816 out_freeirq_rx:
817 free_irq(priv->irq_rx, dev);
818
819 out_freeirq:
820 return ret;
821 }
822
823 static int bcm6368_enetsw_stop(struct net_device *dev)
824 {
825 struct bcm6368_enetsw *priv = netdev_priv(dev);
826 struct device *kdev = &priv->pdev->dev;
827 int i;
828
829 netif_stop_queue(dev);
830 napi_disable(&priv->napi);
831 del_timer_sync(&priv->rx_timeout);
832
833 /* mask all interrupts */
834 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
835 dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
836
837 /* disable dma & mac */
838 bcm6368_enetsw_disable_dma(priv, priv->tx_chan);
839 bcm6368_enetsw_disable_dma(priv, priv->rx_chan);
840
841 /* force reclaim of all tx buffers */
842 bcm6368_enetsw_tx_reclaim(dev, 1);
843
844 /* free the rx buffer ring */
845 for (i = 0; i < priv->rx_ring_size; i++) {
846 struct bcm6368_enetsw_desc *desc;
847
848 if (!priv->rx_buf[i])
849 continue;
850
851 desc = &priv->rx_desc_cpu[i];
852 dma_unmap_single_attrs(kdev, desc->address, priv->rx_buf_size,
853 DMA_FROM_DEVICE,
854 DMA_ATTR_SKIP_CPU_SYNC);
855 skb_free_frag(priv->rx_buf[i]);
856 }
857
858 /* free remaining allocated memory */
859 kfree(priv->rx_buf);
860 kfree(priv->tx_skb);
861 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
862 priv->rx_desc_cpu, priv->rx_desc_dma);
863 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
864 priv->tx_desc_cpu, priv->tx_desc_dma);
865 if (priv->irq_tx != -1)
866 free_irq(priv->irq_tx, dev);
867 free_irq(priv->irq_rx, dev);
868
869 return 0;
870 }
871
872 static const struct net_device_ops bcm6368_enetsw_ops = {
873 .ndo_open = bcm6368_enetsw_open,
874 .ndo_stop = bcm6368_enetsw_stop,
875 .ndo_start_xmit = bcm6368_enetsw_start_xmit,
876 };
877
878 static int bcm6368_enetsw_probe(struct platform_device *pdev)
879 {
880 struct bcm6368_enetsw *priv;
881 struct device *dev = &pdev->dev;
882 struct device_node *node = dev->of_node;
883 struct net_device *ndev;
884 struct resource *res;
885 unsigned i;
886 int ret;
887
888 ndev = alloc_etherdev(sizeof(*priv));
889 if (!ndev)
890 return -ENOMEM;
891
892 priv = netdev_priv(ndev);
893
894 priv->num_pms = of_count_phandle_with_args(node, "power-domains",
895 "#power-domain-cells");
896 if (priv->num_pms > 1) {
897 priv->pm = devm_kcalloc(dev, priv->num_pms,
898 sizeof(struct device *), GFP_KERNEL);
899 if (!priv->pm)
900 return -ENOMEM;
901
902 priv->link_pm = devm_kcalloc(dev, priv->num_pms,
903 sizeof(struct device_link *),
904 GFP_KERNEL);
905 if (!priv->link_pm)
906 return -ENOMEM;
907
908 for (i = 0; i < priv->num_pms; i++) {
909 priv->pm[i] = genpd_dev_pm_attach_by_id(dev, i);
910 if (IS_ERR(priv->pm[i])) {
911 dev_err(dev, "error getting pm %d\n", i);
912 return -EINVAL;
913 }
914
915 priv->link_pm[i] = device_link_add(dev, priv->pm[i],
916 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
917 DL_FLAG_RPM_ACTIVE);
918 }
919 }
920
921 pm_runtime_enable(dev);
922 pm_runtime_no_callbacks(dev);
923 ret = pm_runtime_get_sync(dev);
924 if (ret < 0) {
925 pm_runtime_disable(dev);
926 dev_info(dev, "PM prober defer: ret=%d\n", ret);
927 return -EPROBE_DEFER;
928 }
929
930 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
931 priv->dma_base = devm_ioremap_resource(dev, res);
932 if (IS_ERR(priv->dma_base))
933 return PTR_ERR(priv->dma_base);
934
935 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
936 "dma-channels");
937 priv->dma_chan = devm_ioremap_resource(dev, res);
938 if (IS_ERR(priv->dma_chan))
939 return PTR_ERR(priv->dma_chan);
940
941 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma-sram");
942 priv->dma_sram = devm_ioremap_resource(dev, res);
943 if (IS_ERR(priv->dma_sram))
944 return PTR_ERR(priv->dma_sram);
945
946 priv->irq_rx = platform_get_irq_byname(pdev, "rx");
947 if (!priv->irq_rx)
948 return -ENODEV;
949
950 priv->irq_tx = platform_get_irq_byname(pdev, "tx");
951 if (!priv->irq_tx)
952 return -ENODEV;
953 else if (priv->irq_tx < 0)
954 priv->irq_tx = -1;
955
956 if (device_property_read_u32(dev, "dma-rx", &priv->rx_chan))
957 return -ENODEV;
958
959 if (device_property_read_u32(dev, "dma-tx", &priv->tx_chan))
960 return -ENODEV;
961
962 priv->rx_ring_size = ENETSW_DEF_RX_DESC;
963 priv->tx_ring_size = ENETSW_DEF_TX_DESC;
964
965 priv->dma_maxburst = ENETSW_DMA_MAXBURST;
966
967 priv->copybreak = ENETSW_DEF_CPY_BREAK;
968
969 priv->dma_chan_en_mask = DMAC_CHANCFG_EN_MASK;
970 priv->dma_chan_int_mask = DMAC_IR_PKTDONE_MASK;
971 priv->dma_chan_width = DMA_CHAN_WIDTH;
972
973 of_get_mac_address(node, ndev->dev_addr);
974 if (is_valid_ether_addr(ndev->dev_addr)) {
975 dev_info(dev, "mtd mac %pM\n", ndev->dev_addr);
976 } else {
977 random_ether_addr(ndev->dev_addr);
978 dev_info(dev, "random mac %pM\n", ndev->dev_addr);
979 }
980
981 priv->rx_buf_size = ALIGN(ndev->mtu + ENETSW_MTU_OVERHEAD,
982 priv->dma_maxburst * 4);
983
984 priv->rx_frag_size = ENETSW_FRAG_SIZE(priv->rx_buf_size);
985
986 priv->num_clocks = of_clk_get_parent_count(node);
987 if (priv->num_clocks) {
988 priv->clock = devm_kcalloc(dev, priv->num_clocks,
989 sizeof(struct clk *), GFP_KERNEL);
990 if (!priv->clock)
991 return -ENOMEM;
992 }
993 for (i = 0; i < priv->num_clocks; i++) {
994 priv->clock[i] = of_clk_get(node, i);
995 if (IS_ERR(priv->clock[i])) {
996 dev_err(dev, "error getting clock %d\n", i);
997 return -EINVAL;
998 }
999
1000 ret = clk_prepare_enable(priv->clock[i]);
1001 if (ret) {
1002 dev_err(dev, "error enabling clock %d\n", i);
1003 return ret;
1004 }
1005 }
1006
1007 priv->num_resets = of_count_phandle_with_args(node, "resets",
1008 "#reset-cells");
1009 if (priv->num_resets) {
1010 priv->reset = devm_kcalloc(dev, priv->num_resets,
1011 sizeof(struct reset_control *),
1012 GFP_KERNEL);
1013 if (!priv->reset)
1014 return -ENOMEM;
1015 }
1016 for (i = 0; i < priv->num_resets; i++) {
1017 priv->reset[i] = devm_reset_control_get_by_index(dev, i);
1018 if (IS_ERR(priv->reset[i])) {
1019 dev_err(dev, "error getting reset %d\n", i);
1020 return -EINVAL;
1021 }
1022
1023 ret = reset_control_reset(priv->reset[i]);
1024 if (ret) {
1025 dev_err(dev, "error performing reset %d\n", i);
1026 return ret;
1027 }
1028 }
1029
1030 spin_lock_init(&priv->rx_lock);
1031
1032 timer_setup(&priv->rx_timeout, bcm6368_enetsw_refill_rx_timer, 0);
1033
1034 /* register netdevice */
1035 ndev->netdev_ops = &bcm6368_enetsw_ops;
1036 ndev->min_mtu = ETH_ZLEN;
1037 ndev->mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1038 ndev->max_mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1039 netif_napi_add(ndev, &priv->napi, bcm6368_enetsw_poll, 16);
1040 SET_NETDEV_DEV(ndev, dev);
1041
1042 ret = register_netdev(ndev);
1043 if (ret)
1044 goto out_disable_clk;
1045
1046 netif_carrier_off(ndev);
1047 platform_set_drvdata(pdev, ndev);
1048 priv->pdev = pdev;
1049 priv->net_dev = ndev;
1050
1051 return 0;
1052
1053 out_disable_clk:
1054 for (i = 0; i < priv->num_resets; i++)
1055 reset_control_assert(priv->reset[i]);
1056
1057 for (i = 0; i < priv->num_clocks; i++)
1058 clk_disable_unprepare(priv->clock[i]);
1059
1060 return ret;
1061 }
1062
1063 static int bcm6368_enetsw_remove(struct platform_device *pdev)
1064 {
1065 struct device *dev = &pdev->dev;
1066 struct net_device *ndev = platform_get_drvdata(pdev);
1067 struct bcm6368_enetsw *priv = netdev_priv(ndev);
1068 unsigned int i;
1069
1070 unregister_netdev(ndev);
1071
1072 pm_runtime_put_sync(dev);
1073 for (i = 0; priv->pm && i < priv->num_pms; i++) {
1074 dev_pm_domain_detach(priv->pm[i], true);
1075 device_link_del(priv->link_pm[i]);
1076 }
1077
1078 for (i = 0; i < priv->num_resets; i++)
1079 reset_control_assert(priv->reset[i]);
1080
1081 for (i = 0; i < priv->num_clocks; i++)
1082 clk_disable_unprepare(priv->clock[i]);
1083
1084 free_netdev(ndev);
1085
1086 return 0;
1087 }
1088
1089 static const struct of_device_id bcm6368_enetsw_of_match[] = {
1090 { .compatible = "brcm,bcm6318-enetsw", },
1091 { .compatible = "brcm,bcm6328-enetsw", },
1092 { .compatible = "brcm,bcm6362-enetsw", },
1093 { .compatible = "brcm,bcm6368-enetsw", },
1094 { .compatible = "brcm,bcm63268-enetsw", },
1095 { /* sentinel */ }
1096 };
1097 MODULE_DEVICE_TABLE(of, bcm6368_enetsw_of_match);
1098
1099 static struct platform_driver bcm6368_enetsw_driver = {
1100 .driver = {
1101 .name = "bcm6368-enetsw",
1102 .of_match_table = of_match_ptr(bcm6368_enetsw_of_match),
1103 },
1104 .probe = bcm6368_enetsw_probe,
1105 .remove = bcm6368_enetsw_remove,
1106 };
1107 module_platform_driver(bcm6368_enetsw_driver);
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