1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * BCM6368 Ethernet Switch Controller Driver
5 * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
6 * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/ethtool.h>
15 #include <linux/if_vlan.h>
16 #include <linux/interrupt.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_net.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
25 #define ENETSW_TAG_SIZE 6
26 #define ENETSW_MTU_OVERHEAD (VLAN_ETH_HLEN + VLAN_HLEN + \
28 #define ENETSW_FRAG_SIZE(x) (SKB_DATA_ALIGN(NET_SKB_PAD + x + \
29 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
31 /* default number of descriptor */
32 #define ENETSW_DEF_RX_DESC 64
33 #define ENETSW_DEF_TX_DESC 32
34 #define ENETSW_DEF_CPY_BREAK 128
36 /* maximum burst len for dma (4 bytes unit) */
37 #define ENETSW_DMA_MAXBURST 8
40 #define DMA_CHAN_WIDTH 0x10
42 /* Controller Configuration Register */
43 #define DMA_CFG_REG 0x0
44 #define DMA_CFG_EN_SHIFT 0
45 #define DMA_CFG_EN_MASK (1 << DMA_CFG_EN_SHIFT)
46 #define DMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
48 /* Flow Control Descriptor Low Threshold register */
49 #define DMA_FLOWCL_REG(x) (0x4 + (x) * 6)
51 /* Flow Control Descriptor High Threshold register */
52 #define DMA_FLOWCH_REG(x) (0x8 + (x) * 6)
54 /* Flow Control Descriptor Buffer Alloca Threshold register */
55 #define DMA_BUFALLOC_REG(x) (0xc + (x) * 6)
56 #define DMA_BUFALLOC_FORCE_SHIFT 31
57 #define DMA_BUFALLOC_FORCE_MASK (1 << DMA_BUFALLOC_FORCE_SHIFT)
59 /* Channel Configuration register */
60 #define DMAC_CHANCFG_REG 0x0
61 #define DMAC_CHANCFG_EN_SHIFT 0
62 #define DMAC_CHANCFG_EN_MASK (1 << DMAC_CHANCFG_EN_SHIFT)
63 #define DMAC_CHANCFG_PKTHALT_SHIFT 1
64 #define DMAC_CHANCFG_PKTHALT_MASK (1 << DMAC_CHANCFG_PKTHALT_SHIFT)
65 #define DMAC_CHANCFG_BUFHALT_SHIFT 2
66 #define DMAC_CHANCFG_BUFHALT_MASK (1 << DMAC_CHANCFG_BUFHALT_SHIFT)
67 #define DMAC_CHANCFG_CHAINING_SHIFT 2
68 #define DMAC_CHANCFG_CHAINING_MASK (1 << DMAC_CHANCFG_CHAINING_SHIFT)
69 #define DMAC_CHANCFG_WRAP_EN_SHIFT 3
70 #define DMAC_CHANCFG_WRAP_EN_MASK (1 << DMAC_CHANCFG_WRAP_EN_SHIFT)
71 #define DMAC_CHANCFG_FLOWC_EN_SHIFT 4
72 #define DMAC_CHANCFG_FLOWC_EN_MASK (1 << DMAC_CHANCFG_FLOWC_EN_SHIFT)
74 /* Interrupt Control/Status register */
75 #define DMAC_IR_REG 0x4
76 #define DMAC_IR_BUFDONE_MASK (1 << 0)
77 #define DMAC_IR_PKTDONE_MASK (1 << 1)
78 #define DMAC_IR_NOTOWNER_MASK (1 << 2)
80 /* Interrupt Mask register */
81 #define DMAC_IRMASK_REG 0x8
83 /* Maximum Burst Length */
84 #define DMAC_MAXBURST_REG 0xc
86 /* Ring Start Address register */
87 #define DMAS_RSTART_REG 0x0
89 /* State Ram Word 2 */
90 #define DMAS_SRAM2_REG 0x4
92 /* State Ram Word 3 */
93 #define DMAS_SRAM3_REG 0x8
95 /* State Ram Word 4 */
96 #define DMAS_SRAM4_REG 0xc
98 struct bcm6368_enetsw_desc
{
104 #define DMADESC_LENGTH_SHIFT 16
105 #define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT)
106 #define DMADESC_OWNER_MASK (1 << 15)
107 #define DMADESC_EOP_MASK (1 << 14)
108 #define DMADESC_SOP_MASK (1 << 13)
109 #define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
110 #define DMADESC_WRAP_MASK (1 << 12)
111 #define DMADESC_USB_NOZERO_MASK (1 << 1)
112 #define DMADESC_USB_ZERO_MASK (1 << 0)
115 #define DMADESC_UNDER_MASK (1 << 9)
116 #define DMADESC_APPEND_CRC (1 << 8)
117 #define DMADESC_OVSIZE_MASK (1 << 4)
118 #define DMADESC_RXER_MASK (1 << 2)
119 #define DMADESC_CRC_MASK (1 << 1)
120 #define DMADESC_OV_MASK (1 << 0)
121 #define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \
122 DMADESC_OVSIZE_MASK | \
123 DMADESC_RXER_MASK | \
127 struct bcm6368_enetsw
{
128 void __iomem
*dma_base
;
129 void __iomem
*dma_chan
;
130 void __iomem
*dma_sram
;
133 struct device_link
**link_pm
;
137 unsigned int num_clocks
;
139 struct reset_control
**reset
;
140 unsigned int num_resets
;
147 /* hw view of rx & tx dma ring */
148 dma_addr_t rx_desc_dma
;
149 dma_addr_t tx_desc_dma
;
151 /* allocated size (in bytes) for rx & tx dma ring */
152 unsigned int rx_desc_alloc_size
;
153 unsigned int tx_desc_alloc_size
;
155 struct napi_struct napi
;
157 /* dma channel id for rx */
160 /* number of dma desc in rx ring */
163 /* cpu view of rx dma ring */
164 struct bcm6368_enetsw_desc
*rx_desc_cpu
;
166 /* current number of armed descriptor given to hardware for rx */
169 /* next rx descriptor to fetch from hardware */
172 /* next dirty rx descriptor to refill */
175 /* size of allocated rx buffer */
176 unsigned int rx_buf_size
;
178 /* size of allocated rx frag */
179 unsigned int rx_frag_size
;
181 /* list of buffer given to hw for rx */
182 unsigned char **rx_buf
;
184 /* used when rx buffer allocation failed, so we defer rx queue
186 struct timer_list rx_timeout
;
188 /* lock rx_timeout against rx normal operation */
191 /* dma channel id for tx */
194 /* number of dma desc in tx ring */
197 /* maximum dma burst size */
200 /* cpu view of rx dma ring */
201 struct bcm6368_enetsw_desc
*tx_desc_cpu
;
203 /* number of available descriptor for tx */
206 /* next tx descriptor avaiable */
209 /* next dirty tx descriptor to reclaim */
212 /* list of skb given to hw for tx */
213 struct sk_buff
**tx_skb
;
215 /* lock used by tx reclaim and xmit */
218 /* network device reference */
219 struct net_device
*net_dev
;
221 /* platform device reference */
222 struct platform_device
*pdev
;
224 /* dma channel enable mask */
225 u32 dma_chan_en_mask
;
227 /* dma channel interrupt mask */
228 u32 dma_chan_int_mask
;
230 /* dma channel width */
231 unsigned int dma_chan_width
;
234 static inline void dma_writel(struct bcm6368_enetsw
*priv
, u32 val
, u32 off
)
236 __raw_writel(val
, priv
->dma_base
+ off
);
239 static inline u32
dma_readl(struct bcm6368_enetsw
*priv
, u32 off
, int chan
)
241 return __raw_readl(priv
->dma_chan
+ off
+ chan
* priv
->dma_chan_width
);
244 static inline void dmac_writel(struct bcm6368_enetsw
*priv
, u32 val
,
247 __raw_writel(val
, priv
->dma_chan
+ off
+ chan
* priv
->dma_chan_width
);
250 static inline void dmas_writel(struct bcm6368_enetsw
*priv
, u32 val
,
253 __raw_writel(val
, priv
->dma_sram
+ off
+ chan
* priv
->dma_chan_width
);
259 static int bcm6368_enetsw_refill_rx(struct net_device
*dev
, bool napi_mode
)
261 struct bcm6368_enetsw
*priv
= netdev_priv(dev
);
263 while (priv
->rx_desc_count
< priv
->rx_ring_size
) {
264 struct bcm6368_enetsw_desc
*desc
;
268 desc_idx
= priv
->rx_dirty_desc
;
269 desc
= &priv
->rx_desc_cpu
[desc_idx
];
271 if (!priv
->rx_buf
[desc_idx
]) {
274 if (likely(napi_mode
))
275 buf
= napi_alloc_frag(priv
->rx_frag_size
);
277 buf
= netdev_alloc_frag(priv
->rx_frag_size
);
282 priv
->rx_buf
[desc_idx
] = buf
;
283 desc
->address
= dma_map_single(&priv
->pdev
->dev
,
289 len_stat
= priv
->rx_buf_size
<< DMADESC_LENGTH_SHIFT
;
290 len_stat
|= DMADESC_OWNER_MASK
;
291 if (priv
->rx_dirty_desc
== priv
->rx_ring_size
- 1) {
292 len_stat
|= DMADESC_WRAP_MASK
;
293 priv
->rx_dirty_desc
= 0;
295 priv
->rx_dirty_desc
++;
298 desc
->len_stat
= len_stat
;
300 priv
->rx_desc_count
++;
302 /* tell dma engine we allocated one buffer */
303 dma_writel(priv
, 1, DMA_BUFALLOC_REG(priv
->rx_chan
));
306 /* If rx ring is still empty, set a timer to try allocating
307 * again at a later time. */
308 if (priv
->rx_desc_count
== 0 && netif_running(dev
)) {
309 dev_warn(&priv
->pdev
->dev
, "unable to refill rx ring\n");
310 priv
->rx_timeout
.expires
= jiffies
+ HZ
;
311 add_timer(&priv
->rx_timeout
);
318 * timer callback to defer refill rx queue in case we're OOM
320 static void bcm6368_enetsw_refill_rx_timer(struct timer_list
*t
)
322 struct bcm6368_enetsw
*priv
= from_timer(priv
, t
, rx_timeout
);
323 struct net_device
*dev
= priv
->net_dev
;
325 spin_lock(&priv
->rx_lock
);
326 bcm6368_enetsw_refill_rx(dev
, false);
327 spin_unlock(&priv
->rx_lock
);
331 * extract packet from rx queue
333 static int bcm6368_enetsw_receive_queue(struct net_device
*dev
, int budget
)
335 struct bcm6368_enetsw
*priv
= netdev_priv(dev
);
336 struct device
*kdev
= &priv
->pdev
->dev
;
337 struct list_head rx_list
;
341 INIT_LIST_HEAD(&rx_list
);
343 /* don't scan ring further than number of refilled
345 if (budget
> priv
->rx_desc_count
)
346 budget
= priv
->rx_desc_count
;
349 struct bcm6368_enetsw_desc
*desc
;
350 unsigned int frag_size
;
356 desc_idx
= priv
->rx_curr_desc
;
357 desc
= &priv
->rx_desc_cpu
[desc_idx
];
359 /* make sure we actually read the descriptor status at
363 len_stat
= desc
->len_stat
;
365 /* break if dma ownership belongs to hw */
366 if (len_stat
& DMADESC_OWNER_MASK
)
370 priv
->rx_curr_desc
++;
371 if (priv
->rx_curr_desc
== priv
->rx_ring_size
)
372 priv
->rx_curr_desc
= 0;
374 /* if the packet does not have start of packet _and_
375 * end of packet flag set, then just recycle it */
376 if ((len_stat
& DMADESC_ESOP_MASK
) != DMADESC_ESOP_MASK
) {
377 dev
->stats
.rx_dropped
++;
382 buf
= priv
->rx_buf
[desc_idx
];
383 len
= (len_stat
& DMADESC_LENGTH_MASK
)
384 >> DMADESC_LENGTH_SHIFT
;
385 /* don't include FCS */
388 if (len
< priv
->copybreak
) {
389 unsigned int nfrag_size
= ENETSW_FRAG_SIZE(len
);
390 unsigned char *nbuf
= napi_alloc_frag(nfrag_size
);
392 if (unlikely(!nbuf
)) {
393 /* forget packet, just rearm desc */
394 dev
->stats
.rx_dropped
++;
398 dma_sync_single_for_cpu(kdev
, desc
->address
,
399 len
, DMA_FROM_DEVICE
);
400 memcpy(nbuf
+ NET_SKB_PAD
, buf
+ NET_SKB_PAD
, len
);
401 dma_sync_single_for_device(kdev
, desc
->address
,
402 len
, DMA_FROM_DEVICE
);
404 frag_size
= nfrag_size
;
406 dma_unmap_single(kdev
, desc
->address
,
407 priv
->rx_buf_size
, DMA_FROM_DEVICE
);
408 priv
->rx_buf
[desc_idx
] = NULL
;
409 frag_size
= priv
->rx_frag_size
;
412 skb
= napi_build_skb(buf
, frag_size
);
413 if (unlikely(!skb
)) {
415 dev
->stats
.rx_dropped
++;
419 skb_reserve(skb
, NET_SKB_PAD
);
421 dev
->stats
.rx_packets
++;
422 dev
->stats
.rx_bytes
+= len
;
423 list_add_tail(&skb
->list
, &rx_list
);
424 } while (processed
< budget
);
426 list_for_each_entry(skb
, &rx_list
, list
)
427 skb
->protocol
= eth_type_trans(skb
, dev
);
428 netif_receive_skb_list(&rx_list
);
429 priv
->rx_desc_count
-= processed
;
431 if (processed
|| !priv
->rx_desc_count
) {
432 bcm6368_enetsw_refill_rx(dev
, true);
435 dmac_writel(priv
, priv
->dma_chan_en_mask
,
436 DMAC_CHANCFG_REG
, priv
->rx_chan
);
443 * try to or force reclaim of transmitted buffers
445 static int bcm6368_enetsw_tx_reclaim(struct net_device
*dev
, int force
)
447 struct bcm6368_enetsw
*priv
= netdev_priv(dev
);
450 while (priv
->tx_desc_count
< priv
->tx_ring_size
) {
451 struct bcm6368_enetsw_desc
*desc
;
454 /* We run in a bh and fight against start_xmit, which
455 * is called with bh disabled */
456 spin_lock(&priv
->tx_lock
);
458 desc
= &priv
->tx_desc_cpu
[priv
->tx_dirty_desc
];
460 if (!force
&& (desc
->len_stat
& DMADESC_OWNER_MASK
)) {
461 spin_unlock(&priv
->tx_lock
);
465 /* ensure other field of the descriptor were not read
466 * before we checked ownership */
469 skb
= priv
->tx_skb
[priv
->tx_dirty_desc
];
470 priv
->tx_skb
[priv
->tx_dirty_desc
] = NULL
;
471 dma_unmap_single(&priv
->pdev
->dev
, desc
->address
, skb
->len
,
474 priv
->tx_dirty_desc
++;
475 if (priv
->tx_dirty_desc
== priv
->tx_ring_size
)
476 priv
->tx_dirty_desc
= 0;
477 priv
->tx_desc_count
++;
479 spin_unlock(&priv
->tx_lock
);
481 if (desc
->len_stat
& DMADESC_UNDER_MASK
)
482 dev
->stats
.tx_errors
++;
484 napi_consume_skb(skb
, !force
);
488 if (netif_queue_stopped(dev
) && released
)
489 netif_wake_queue(dev
);
495 * poll func, called by network core
497 static int bcm6368_enetsw_poll(struct napi_struct
*napi
, int budget
)
499 struct bcm6368_enetsw
*priv
= container_of(napi
, struct bcm6368_enetsw
, napi
);
500 struct net_device
*dev
= priv
->net_dev
;
504 dmac_writel(priv
, priv
->dma_chan_int_mask
,
505 DMAC_IR_REG
, priv
->rx_chan
);
506 dmac_writel(priv
, priv
->dma_chan_int_mask
,
507 DMAC_IR_REG
, priv
->tx_chan
);
509 /* reclaim sent skb */
510 bcm6368_enetsw_tx_reclaim(dev
, 0);
512 spin_lock(&priv
->rx_lock
);
513 rx_work_done
= bcm6368_enetsw_receive_queue(dev
, budget
);
514 spin_unlock(&priv
->rx_lock
);
516 if (rx_work_done
>= budget
) {
517 /* rx queue is not yet empty/clean */
521 /* no more packet in rx/tx queue, remove device from poll
523 napi_complete_done(napi
, rx_work_done
);
525 /* restore rx/tx interrupt */
526 dmac_writel(priv
, priv
->dma_chan_int_mask
,
527 DMAC_IRMASK_REG
, priv
->rx_chan
);
528 dmac_writel(priv
, priv
->dma_chan_int_mask
,
529 DMAC_IRMASK_REG
, priv
->tx_chan
);
535 * rx/tx dma interrupt handler
537 static irqreturn_t
bcm6368_enetsw_isr_dma(int irq
, void *dev_id
)
539 struct net_device
*dev
= dev_id
;
540 struct bcm6368_enetsw
*priv
= netdev_priv(dev
);
542 /* mask rx/tx interrupts */
543 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->rx_chan
);
544 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->tx_chan
);
546 napi_schedule(&priv
->napi
);
552 * tx request callback
555 bcm6368_enetsw_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
557 struct bcm6368_enetsw
*priv
= netdev_priv(dev
);
558 struct bcm6368_enetsw_desc
*desc
;
562 /* lock against tx reclaim */
563 spin_lock(&priv
->tx_lock
);
565 /* make sure the tx hw queue is not full, should not happen
566 * since we stop queue before it's the case */
567 if (unlikely(!priv
->tx_desc_count
)) {
568 netif_stop_queue(dev
);
569 dev_err(&priv
->pdev
->dev
, "xmit called with no tx desc "
571 ret
= NETDEV_TX_BUSY
;
575 /* pad small packets */
576 if (skb
->len
< (ETH_ZLEN
+ ETH_FCS_LEN
)) {
577 int needed
= (ETH_ZLEN
+ ETH_FCS_LEN
) - skb
->len
;
580 if (unlikely(skb_tailroom(skb
) < needed
)) {
581 struct sk_buff
*nskb
;
583 nskb
= skb_copy_expand(skb
, 0, needed
, GFP_ATOMIC
);
585 ret
= NETDEV_TX_BUSY
;
592 data
= skb_put_zero(skb
, needed
);
595 /* point to the next available desc */
596 desc
= &priv
->tx_desc_cpu
[priv
->tx_curr_desc
];
597 priv
->tx_skb
[priv
->tx_curr_desc
] = skb
;
599 /* fill descriptor */
600 desc
->address
= dma_map_single(&priv
->pdev
->dev
, skb
->data
, skb
->len
,
603 len_stat
= (skb
->len
<< DMADESC_LENGTH_SHIFT
) & DMADESC_LENGTH_MASK
;
604 len_stat
|= DMADESC_ESOP_MASK
| DMADESC_APPEND_CRC
|
607 priv
->tx_curr_desc
++;
608 if (priv
->tx_curr_desc
== priv
->tx_ring_size
) {
609 priv
->tx_curr_desc
= 0;
610 len_stat
|= DMADESC_WRAP_MASK
;
612 priv
->tx_desc_count
--;
614 /* dma might be already polling, make sure we update desc
615 * fields in correct order */
617 desc
->len_stat
= len_stat
;
621 dmac_writel(priv
, priv
->dma_chan_en_mask
, DMAC_CHANCFG_REG
,
624 /* stop queue if no more desc available */
625 if (!priv
->tx_desc_count
)
626 netif_stop_queue(dev
);
628 dev
->stats
.tx_bytes
+= skb
->len
;
629 dev
->stats
.tx_packets
++;
633 spin_unlock(&priv
->tx_lock
);
638 * disable dma in given channel
640 static void bcm6368_enetsw_disable_dma(struct bcm6368_enetsw
*priv
, int chan
)
644 dmac_writel(priv
, 0, DMAC_CHANCFG_REG
, chan
);
649 val
= dma_readl(priv
, DMAC_CHANCFG_REG
, chan
);
650 if (!(val
& DMAC_CHANCFG_EN_MASK
))
657 static int bcm6368_enetsw_open(struct net_device
*dev
)
659 struct bcm6368_enetsw
*priv
= netdev_priv(dev
);
660 struct device
*kdev
= &priv
->pdev
->dev
;
666 /* mask all interrupts and request them */
667 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->rx_chan
);
668 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->tx_chan
);
670 ret
= request_irq(priv
->irq_rx
, bcm6368_enetsw_isr_dma
,
675 if (priv
->irq_tx
!= -1) {
676 ret
= request_irq(priv
->irq_tx
, bcm6368_enetsw_isr_dma
,
682 /* allocate rx dma ring */
683 size
= priv
->rx_ring_size
* sizeof(struct bcm6368_enetsw_desc
);
684 p
= dma_alloc_coherent(kdev
, size
, &priv
->rx_desc_dma
, GFP_KERNEL
);
686 dev_err(kdev
, "cannot allocate rx ring %u\n", size
);
692 priv
->rx_desc_alloc_size
= size
;
693 priv
->rx_desc_cpu
= p
;
695 /* allocate tx dma ring */
696 size
= priv
->tx_ring_size
* sizeof(struct bcm6368_enetsw_desc
);
697 p
= dma_alloc_coherent(kdev
, size
, &priv
->tx_desc_dma
, GFP_KERNEL
);
699 dev_err(kdev
, "cannot allocate tx ring\n");
701 goto out_free_rx_ring
;
705 priv
->tx_desc_alloc_size
= size
;
706 priv
->tx_desc_cpu
= p
;
708 priv
->tx_skb
= kzalloc(sizeof(struct sk_buff
*) * priv
->tx_ring_size
,
711 dev_err(kdev
, "cannot allocate tx skb queue\n");
713 goto out_free_tx_ring
;
716 priv
->tx_desc_count
= priv
->tx_ring_size
;
717 priv
->tx_dirty_desc
= 0;
718 priv
->tx_curr_desc
= 0;
719 spin_lock_init(&priv
->tx_lock
);
721 /* init & fill rx ring with buffers */
722 priv
->rx_buf
= kzalloc(sizeof(unsigned char *) * priv
->rx_ring_size
,
725 dev_err(kdev
, "cannot allocate rx buffer queue\n");
727 goto out_free_tx_skb
;
730 priv
->rx_desc_count
= 0;
731 priv
->rx_dirty_desc
= 0;
732 priv
->rx_curr_desc
= 0;
734 /* initialize flow control buffer allocation */
735 dma_writel(priv
, DMA_BUFALLOC_FORCE_MASK
| 0,
736 DMA_BUFALLOC_REG(priv
->rx_chan
));
738 if (bcm6368_enetsw_refill_rx(dev
, false)) {
739 dev_err(kdev
, "cannot allocate rx buffer queue\n");
744 /* write rx & tx ring addresses */
745 dmas_writel(priv
, priv
->rx_desc_dma
,
746 DMAS_RSTART_REG
, priv
->rx_chan
);
747 dmas_writel(priv
, priv
->tx_desc_dma
,
748 DMAS_RSTART_REG
, priv
->tx_chan
);
750 /* clear remaining state ram for rx & tx channel */
751 dmas_writel(priv
, 0, DMAS_SRAM2_REG
, priv
->rx_chan
);
752 dmas_writel(priv
, 0, DMAS_SRAM2_REG
, priv
->tx_chan
);
753 dmas_writel(priv
, 0, DMAS_SRAM3_REG
, priv
->rx_chan
);
754 dmas_writel(priv
, 0, DMAS_SRAM3_REG
, priv
->tx_chan
);
755 dmas_writel(priv
, 0, DMAS_SRAM4_REG
, priv
->rx_chan
);
756 dmas_writel(priv
, 0, DMAS_SRAM4_REG
, priv
->tx_chan
);
758 /* set dma maximum burst len */
759 dmac_writel(priv
, priv
->dma_maxburst
,
760 DMAC_MAXBURST_REG
, priv
->rx_chan
);
761 dmac_writel(priv
, priv
->dma_maxburst
,
762 DMAC_MAXBURST_REG
, priv
->tx_chan
);
764 /* set flow control low/high threshold to 1/3 / 2/3 */
765 val
= priv
->rx_ring_size
/ 3;
766 dma_writel(priv
, val
, DMA_FLOWCL_REG(priv
->rx_chan
));
767 val
= (priv
->rx_ring_size
* 2) / 3;
768 dma_writel(priv
, val
, DMA_FLOWCH_REG(priv
->rx_chan
));
770 /* all set, enable mac and interrupts, start dma engine and
771 * kick rx dma channel
774 dma_writel(priv
, DMA_CFG_EN_MASK
, DMA_CFG_REG
);
775 dmac_writel(priv
, DMAC_CHANCFG_EN_MASK
,
776 DMAC_CHANCFG_REG
, priv
->rx_chan
);
778 /* watch "packet transferred" interrupt in rx and tx */
779 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
780 DMAC_IR_REG
, priv
->rx_chan
);
781 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
782 DMAC_IR_REG
, priv
->tx_chan
);
784 /* make sure we enable napi before rx interrupt */
785 napi_enable(&priv
->napi
);
787 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
788 DMAC_IRMASK_REG
, priv
->rx_chan
);
789 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
790 DMAC_IRMASK_REG
, priv
->tx_chan
);
792 netif_carrier_on(dev
);
793 netif_start_queue(dev
);
798 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
799 struct bcm6368_enetsw_desc
*desc
;
801 if (!priv
->rx_buf
[i
])
804 desc
= &priv
->rx_desc_cpu
[i
];
805 dma_unmap_single(kdev
, desc
->address
, priv
->rx_buf_size
,
807 skb_free_frag(priv
->rx_buf
[i
]);
815 dma_free_coherent(kdev
, priv
->tx_desc_alloc_size
,
816 priv
->tx_desc_cpu
, priv
->tx_desc_dma
);
819 dma_free_coherent(kdev
, priv
->rx_desc_alloc_size
,
820 priv
->rx_desc_cpu
, priv
->rx_desc_dma
);
823 if (priv
->irq_tx
!= -1)
824 free_irq(priv
->irq_tx
, dev
);
827 free_irq(priv
->irq_rx
, dev
);
833 static int bcm6368_enetsw_stop(struct net_device
*dev
)
835 struct bcm6368_enetsw
*priv
= netdev_priv(dev
);
836 struct device
*kdev
= &priv
->pdev
->dev
;
839 netif_stop_queue(dev
);
840 napi_disable(&priv
->napi
);
841 del_timer_sync(&priv
->rx_timeout
);
843 /* mask all interrupts */
844 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->rx_chan
);
845 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->tx_chan
);
847 /* disable dma & mac */
848 bcm6368_enetsw_disable_dma(priv
, priv
->tx_chan
);
849 bcm6368_enetsw_disable_dma(priv
, priv
->rx_chan
);
851 /* force reclaim of all tx buffers */
852 bcm6368_enetsw_tx_reclaim(dev
, 1);
854 /* free the rx buffer ring */
855 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
856 struct bcm6368_enetsw_desc
*desc
;
858 if (!priv
->rx_buf
[i
])
861 desc
= &priv
->rx_desc_cpu
[i
];
862 dma_unmap_single_attrs(kdev
, desc
->address
, priv
->rx_buf_size
,
864 DMA_ATTR_SKIP_CPU_SYNC
);
865 skb_free_frag(priv
->rx_buf
[i
]);
868 /* free remaining allocated memory */
871 dma_free_coherent(kdev
, priv
->rx_desc_alloc_size
,
872 priv
->rx_desc_cpu
, priv
->rx_desc_dma
);
873 dma_free_coherent(kdev
, priv
->tx_desc_alloc_size
,
874 priv
->tx_desc_cpu
, priv
->tx_desc_dma
);
875 if (priv
->irq_tx
!= -1)
876 free_irq(priv
->irq_tx
, dev
);
877 free_irq(priv
->irq_rx
, dev
);
882 static const struct net_device_ops bcm6368_enetsw_ops
= {
883 .ndo_open
= bcm6368_enetsw_open
,
884 .ndo_stop
= bcm6368_enetsw_stop
,
885 .ndo_start_xmit
= bcm6368_enetsw_start_xmit
,
888 static int bcm6368_enetsw_probe(struct platform_device
*pdev
)
890 struct bcm6368_enetsw
*priv
;
891 struct device
*dev
= &pdev
->dev
;
892 struct device_node
*node
= dev
->of_node
;
893 struct net_device
*ndev
;
894 struct resource
*res
;
898 ndev
= alloc_etherdev(sizeof(*priv
));
902 priv
= netdev_priv(ndev
);
904 priv
->num_pms
= of_count_phandle_with_args(node
, "power-domains",
905 "#power-domain-cells");
906 if (priv
->num_pms
> 1) {
907 priv
->pm
= devm_kcalloc(dev
, priv
->num_pms
,
908 sizeof(struct device
*), GFP_KERNEL
);
912 priv
->link_pm
= devm_kcalloc(dev
, priv
->num_pms
,
913 sizeof(struct device_link
*),
918 for (i
= 0; i
< priv
->num_pms
; i
++) {
919 priv
->pm
[i
] = genpd_dev_pm_attach_by_id(dev
, i
);
920 if (IS_ERR(priv
->pm
[i
])) {
921 dev_err(dev
, "error getting pm %d\n", i
);
925 priv
->link_pm
[i
] = device_link_add(dev
, priv
->pm
[i
],
926 DL_FLAG_STATELESS
| DL_FLAG_PM_RUNTIME
|
931 pm_runtime_enable(dev
);
932 pm_runtime_no_callbacks(dev
);
933 ret
= pm_runtime_get_sync(dev
);
935 pm_runtime_disable(dev
);
936 dev_info(dev
, "PM prober defer: ret=%d\n", ret
);
937 return -EPROBE_DEFER
;
940 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dma");
941 priv
->dma_base
= devm_ioremap_resource(dev
, res
);
942 if (IS_ERR(priv
->dma_base
))
943 return PTR_ERR(priv
->dma_base
);
945 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
947 priv
->dma_chan
= devm_ioremap_resource(dev
, res
);
948 if (IS_ERR(priv
->dma_chan
))
949 return PTR_ERR(priv
->dma_chan
);
951 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dma-sram");
952 priv
->dma_sram
= devm_ioremap_resource(dev
, res
);
953 if (IS_ERR(priv
->dma_sram
))
954 return PTR_ERR(priv
->dma_sram
);
956 priv
->irq_rx
= platform_get_irq_byname(pdev
, "rx");
960 priv
->irq_tx
= platform_get_irq_byname(pdev
, "tx");
963 else if (priv
->irq_tx
< 0)
966 if (device_property_read_u32(dev
, "dma-rx", &priv
->rx_chan
))
969 if (device_property_read_u32(dev
, "dma-tx", &priv
->tx_chan
))
972 priv
->rx_ring_size
= ENETSW_DEF_RX_DESC
;
973 priv
->tx_ring_size
= ENETSW_DEF_TX_DESC
;
975 priv
->dma_maxburst
= ENETSW_DMA_MAXBURST
;
977 priv
->copybreak
= ENETSW_DEF_CPY_BREAK
;
979 priv
->dma_chan_en_mask
= DMAC_CHANCFG_EN_MASK
;
980 priv
->dma_chan_int_mask
= DMAC_IR_PKTDONE_MASK
;
981 priv
->dma_chan_width
= DMA_CHAN_WIDTH
;
983 of_get_mac_address(node
, ndev
->dev_addr
);
984 if (is_valid_ether_addr(ndev
->dev_addr
)) {
985 dev_info(dev
, "mtd mac %pM\n", ndev
->dev_addr
);
987 random_ether_addr(ndev
->dev_addr
);
988 dev_info(dev
, "random mac %pM\n", ndev
->dev_addr
);
991 priv
->rx_buf_size
= ALIGN(ndev
->mtu
+ ENETSW_MTU_OVERHEAD
,
992 priv
->dma_maxburst
* 4);
994 priv
->rx_frag_size
= ENETSW_FRAG_SIZE(priv
->rx_buf_size
);
996 priv
->num_clocks
= of_clk_get_parent_count(node
);
997 if (priv
->num_clocks
) {
998 priv
->clock
= devm_kcalloc(dev
, priv
->num_clocks
,
999 sizeof(struct clk
*), GFP_KERNEL
);
1003 for (i
= 0; i
< priv
->num_clocks
; i
++) {
1004 priv
->clock
[i
] = of_clk_get(node
, i
);
1005 if (IS_ERR(priv
->clock
[i
])) {
1006 dev_err(dev
, "error getting clock %d\n", i
);
1010 ret
= clk_prepare_enable(priv
->clock
[i
]);
1012 dev_err(dev
, "error enabling clock %d\n", i
);
1017 priv
->num_resets
= of_count_phandle_with_args(node
, "resets",
1019 if (priv
->num_resets
) {
1020 priv
->reset
= devm_kcalloc(dev
, priv
->num_resets
,
1021 sizeof(struct reset_control
*),
1026 for (i
= 0; i
< priv
->num_resets
; i
++) {
1027 priv
->reset
[i
] = devm_reset_control_get_by_index(dev
, i
);
1028 if (IS_ERR(priv
->reset
[i
])) {
1029 dev_err(dev
, "error getting reset %d\n", i
);
1033 ret
= reset_control_reset(priv
->reset
[i
]);
1035 dev_err(dev
, "error performing reset %d\n", i
);
1040 spin_lock_init(&priv
->rx_lock
);
1042 timer_setup(&priv
->rx_timeout
, bcm6368_enetsw_refill_rx_timer
, 0);
1044 /* register netdevice */
1045 ndev
->netdev_ops
= &bcm6368_enetsw_ops
;
1046 ndev
->min_mtu
= ETH_ZLEN
;
1047 ndev
->mtu
= ETH_DATA_LEN
+ ENETSW_TAG_SIZE
;
1048 ndev
->max_mtu
= ETH_DATA_LEN
+ ENETSW_TAG_SIZE
;
1049 netif_napi_add(ndev
, &priv
->napi
, bcm6368_enetsw_poll
, 16);
1050 SET_NETDEV_DEV(ndev
, dev
);
1052 ret
= register_netdev(ndev
);
1054 goto out_disable_clk
;
1056 netif_carrier_off(ndev
);
1057 platform_set_drvdata(pdev
, ndev
);
1059 priv
->net_dev
= ndev
;
1064 for (i
= 0; i
< priv
->num_resets
; i
++)
1065 reset_control_assert(priv
->reset
[i
]);
1067 for (i
= 0; i
< priv
->num_clocks
; i
++)
1068 clk_disable_unprepare(priv
->clock
[i
]);
1073 static int bcm6368_enetsw_remove(struct platform_device
*pdev
)
1075 struct device
*dev
= &pdev
->dev
;
1076 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1077 struct bcm6368_enetsw
*priv
= netdev_priv(ndev
);
1080 unregister_netdev(ndev
);
1082 pm_runtime_put_sync(dev
);
1083 for (i
= 0; priv
->pm
&& i
< priv
->num_pms
; i
++) {
1084 dev_pm_domain_detach(priv
->pm
[i
], true);
1085 device_link_del(priv
->link_pm
[i
]);
1088 for (i
= 0; i
< priv
->num_resets
; i
++)
1089 reset_control_assert(priv
->reset
[i
]);
1091 for (i
= 0; i
< priv
->num_clocks
; i
++)
1092 clk_disable_unprepare(priv
->clock
[i
]);
1099 static const struct of_device_id bcm6368_enetsw_of_match
[] = {
1100 { .compatible
= "brcm,bcm6318-enetsw", },
1101 { .compatible
= "brcm,bcm6328-enetsw", },
1102 { .compatible
= "brcm,bcm6362-enetsw", },
1103 { .compatible
= "brcm,bcm6368-enetsw", },
1104 { .compatible
= "brcm,bcm63268-enetsw", },
1107 MODULE_DEVICE_TABLE(of
, bcm6368_enetsw_of_match
);
1109 static struct platform_driver bcm6368_enetsw_driver
= {
1111 .name
= "bcm6368-enetsw",
1112 .of_match_table
= of_match_ptr(bcm6368_enetsw_of_match
),
1114 .probe
= bcm6368_enetsw_probe
,
1115 .remove
= bcm6368_enetsw_remove
,
1117 module_platform_driver(bcm6368_enetsw_driver
);