1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * BCM6368 Ethernet Switch Controller Driver
5 * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
6 * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
14 #include <linux/ethtool.h>
15 #include <linux/if_vlan.h>
16 #include <linux/interrupt.h>
17 #include <linux/of_clk.h>
18 #include <linux/of_net.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_domain.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/reset.h>
25 #define ENETSW_TAG_SIZE (6 + VLAN_HLEN)
26 #define ENETSW_MTU_OVERHEAD (VLAN_ETH_HLEN + VLAN_HLEN + \
28 #define ENETSW_FRAG_SIZE(x) (SKB_DATA_ALIGN(NET_SKB_PAD + x + \
29 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
31 /* default number of descriptor */
32 #define ENETSW_DEF_RX_DESC 64
33 #define ENETSW_DEF_TX_DESC 32
34 #define ENETSW_DEF_CPY_BREAK 128
36 /* maximum burst len for dma (4 bytes unit) */
37 #define ENETSW_DMA_MAXBURST 8
40 #define DMA_CHAN_WIDTH 0x10
42 /* Controller Configuration Register */
43 #define DMA_CFG_REG 0x0
44 #define DMA_CFG_EN_SHIFT 0
45 #define DMA_CFG_EN_MASK (1 << DMA_CFG_EN_SHIFT)
46 #define DMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
48 /* Flow Control Descriptor Low Threshold register */
49 #define DMA_FLOWCL_REG(x) (0x4 + (x) * 6)
51 /* Flow Control Descriptor High Threshold register */
52 #define DMA_FLOWCH_REG(x) (0x8 + (x) * 6)
54 /* Flow Control Descriptor Buffer Alloca Threshold register */
55 #define DMA_BUFALLOC_REG(x) (0xc + (x) * 6)
56 #define DMA_BUFALLOC_FORCE_SHIFT 31
57 #define DMA_BUFALLOC_FORCE_MASK (1 << DMA_BUFALLOC_FORCE_SHIFT)
59 /* Channel Configuration register */
60 #define DMAC_CHANCFG_REG 0x0
61 #define DMAC_CHANCFG_EN_SHIFT 0
62 #define DMAC_CHANCFG_EN_MASK (1 << DMAC_CHANCFG_EN_SHIFT)
63 #define DMAC_CHANCFG_PKTHALT_SHIFT 1
64 #define DMAC_CHANCFG_PKTHALT_MASK (1 << DMAC_CHANCFG_PKTHALT_SHIFT)
65 #define DMAC_CHANCFG_BUFHALT_SHIFT 2
66 #define DMAC_CHANCFG_BUFHALT_MASK (1 << DMAC_CHANCFG_BUFHALT_SHIFT)
67 #define DMAC_CHANCFG_CHAINING_SHIFT 2
68 #define DMAC_CHANCFG_CHAINING_MASK (1 << DMAC_CHANCFG_CHAINING_SHIFT)
69 #define DMAC_CHANCFG_WRAP_EN_SHIFT 3
70 #define DMAC_CHANCFG_WRAP_EN_MASK (1 << DMAC_CHANCFG_WRAP_EN_SHIFT)
71 #define DMAC_CHANCFG_FLOWC_EN_SHIFT 4
72 #define DMAC_CHANCFG_FLOWC_EN_MASK (1 << DMAC_CHANCFG_FLOWC_EN_SHIFT)
74 /* Interrupt Control/Status register */
75 #define DMAC_IR_REG 0x4
76 #define DMAC_IR_BUFDONE_MASK (1 << 0)
77 #define DMAC_IR_PKTDONE_MASK (1 << 1)
78 #define DMAC_IR_NOTOWNER_MASK (1 << 2)
80 /* Interrupt Mask register */
81 #define DMAC_IRMASK_REG 0x8
83 /* Maximum Burst Length */
84 #define DMAC_MAXBURST_REG 0xc
86 /* Ring Start Address register */
87 #define DMAS_RSTART_REG 0x0
89 /* State Ram Word 2 */
90 #define DMAS_SRAM2_REG 0x4
92 /* State Ram Word 3 */
93 #define DMAS_SRAM3_REG 0x8
95 /* State Ram Word 4 */
96 #define DMAS_SRAM4_REG 0xc
98 struct bcm6368_enetsw_desc
{
104 #define DMADESC_LENGTH_SHIFT 16
105 #define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT)
106 #define DMADESC_OWNER_MASK (1 << 15)
107 #define DMADESC_EOP_MASK (1 << 14)
108 #define DMADESC_SOP_MASK (1 << 13)
109 #define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
110 #define DMADESC_WRAP_MASK (1 << 12)
111 #define DMADESC_USB_NOZERO_MASK (1 << 1)
112 #define DMADESC_USB_ZERO_MASK (1 << 0)
115 #define DMADESC_UNDER_MASK (1 << 9)
116 #define DMADESC_APPEND_CRC (1 << 8)
117 #define DMADESC_OVSIZE_MASK (1 << 4)
118 #define DMADESC_RXER_MASK (1 << 2)
119 #define DMADESC_CRC_MASK (1 << 1)
120 #define DMADESC_OV_MASK (1 << 0)
121 #define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \
122 DMADESC_OVSIZE_MASK | \
123 DMADESC_RXER_MASK | \
127 struct bcm6368_enetsw
{
128 void __iomem
*dma_base
;
129 void __iomem
*dma_chan
;
130 void __iomem
*dma_sram
;
133 struct device_link
**link_pm
;
137 unsigned int num_clocks
;
139 struct reset_control
**reset
;
140 unsigned int num_resets
;
147 /* hw view of rx & tx dma ring */
148 dma_addr_t rx_desc_dma
;
149 dma_addr_t tx_desc_dma
;
151 /* allocated size (in bytes) for rx & tx dma ring */
152 unsigned int rx_desc_alloc_size
;
153 unsigned int tx_desc_alloc_size
;
155 struct napi_struct napi
;
157 /* dma channel id for rx */
160 /* number of dma desc in rx ring */
163 /* cpu view of rx dma ring */
164 struct bcm6368_enetsw_desc
*rx_desc_cpu
;
166 /* current number of armed descriptor given to hardware for rx */
169 /* next rx descriptor to fetch from hardware */
172 /* next dirty rx descriptor to refill */
175 /* size of allocated rx buffer */
176 unsigned int rx_buf_size
;
178 /* size of allocated rx frag */
179 unsigned int rx_frag_size
;
181 /* list of buffer given to hw for rx */
182 unsigned char **rx_buf
;
184 /* used when rx buffer allocation failed, so we defer rx queue
186 struct timer_list rx_timeout
;
188 /* lock rx_timeout against rx normal operation */
191 /* dma channel id for tx */
194 /* number of dma desc in tx ring */
197 /* cpu view of rx dma ring */
198 struct bcm6368_enetsw_desc
*tx_desc_cpu
;
200 /* number of available descriptor for tx */
203 /* next tx descriptor avaiable */
206 /* next dirty tx descriptor to reclaim */
209 /* list of skb given to hw for tx */
210 struct sk_buff
**tx_skb
;
212 /* lock used by tx reclaim and xmit */
215 /* network device reference */
216 struct net_device
*net_dev
;
218 /* platform device reference */
219 struct platform_device
*pdev
;
222 static inline void dma_writel(struct bcm6368_enetsw
*priv
, u32 val
, u32 off
)
224 __raw_writel(val
, priv
->dma_base
+ off
);
227 static inline u32
dma_readl(struct bcm6368_enetsw
*priv
, u32 off
, int chan
)
229 return __raw_readl(priv
->dma_chan
+ off
+ chan
* DMA_CHAN_WIDTH
);
232 static inline void dmac_writel(struct bcm6368_enetsw
*priv
, u32 val
, u32 off
,
235 __raw_writel(val
, priv
->dma_chan
+ off
+ chan
* DMA_CHAN_WIDTH
);
238 static inline void dmas_writel(struct bcm6368_enetsw
*priv
, u32 val
,
241 __raw_writel(val
, priv
->dma_sram
+ off
+ chan
* DMA_CHAN_WIDTH
);
247 static int bcm6368_enetsw_refill_rx(struct net_device
*ndev
, bool napi_mode
)
249 struct bcm6368_enetsw
*priv
= netdev_priv(ndev
);
250 struct platform_device
*pdev
= priv
->pdev
;
251 struct device
*dev
= &pdev
->dev
;
253 while (priv
->rx_desc_count
< priv
->rx_ring_size
) {
254 struct bcm6368_enetsw_desc
*desc
;
258 desc_idx
= priv
->rx_dirty_desc
;
259 desc
= &priv
->rx_desc_cpu
[desc_idx
];
261 if (!priv
->rx_buf
[desc_idx
]) {
265 if (likely(napi_mode
))
266 buf
= napi_alloc_frag(priv
->rx_frag_size
);
268 buf
= netdev_alloc_frag(priv
->rx_frag_size
);
273 p
= dma_map_single(dev
, buf
+ NET_SKB_PAD
,
274 priv
->rx_buf_size
, DMA_FROM_DEVICE
);
275 if (unlikely(dma_mapping_error(dev
, p
))) {
280 priv
->rx_buf
[desc_idx
] = buf
;
284 len_stat
= priv
->rx_buf_size
<< DMADESC_LENGTH_SHIFT
;
285 len_stat
|= DMADESC_OWNER_MASK
;
286 if (priv
->rx_dirty_desc
== priv
->rx_ring_size
- 1) {
287 len_stat
|= DMADESC_WRAP_MASK
;
288 priv
->rx_dirty_desc
= 0;
290 priv
->rx_dirty_desc
++;
293 desc
->len_stat
= len_stat
;
295 priv
->rx_desc_count
++;
297 /* tell dma engine we allocated one buffer */
298 dma_writel(priv
, 1, DMA_BUFALLOC_REG(priv
->rx_chan
));
301 /* If rx ring is still empty, set a timer to try allocating
302 * again at a later time. */
303 if (priv
->rx_desc_count
== 0 && netif_running(ndev
)) {
304 dev_warn(dev
, "unable to refill rx ring\n");
305 priv
->rx_timeout
.expires
= jiffies
+ HZ
;
306 add_timer(&priv
->rx_timeout
);
313 * timer callback to defer refill rx queue in case we're OOM
315 static void bcm6368_enetsw_refill_rx_timer(struct timer_list
*t
)
317 struct bcm6368_enetsw
*priv
= from_timer(priv
, t
, rx_timeout
);
318 struct net_device
*ndev
= priv
->net_dev
;
320 spin_lock(&priv
->rx_lock
);
321 bcm6368_enetsw_refill_rx(ndev
, false);
322 spin_unlock(&priv
->rx_lock
);
326 * extract packet from rx queue
328 static int bcm6368_enetsw_receive_queue(struct net_device
*ndev
, int budget
)
330 struct bcm6368_enetsw
*priv
= netdev_priv(ndev
);
331 struct platform_device
*pdev
= priv
->pdev
;
332 struct device
*dev
= &pdev
->dev
;
333 struct list_head rx_list
;
337 INIT_LIST_HEAD(&rx_list
);
339 /* don't scan ring further than number of refilled
341 if (budget
> priv
->rx_desc_count
)
342 budget
= priv
->rx_desc_count
;
345 struct bcm6368_enetsw_desc
*desc
;
346 unsigned int frag_size
;
352 desc_idx
= priv
->rx_curr_desc
;
353 desc
= &priv
->rx_desc_cpu
[desc_idx
];
355 /* make sure we actually read the descriptor status at
359 len_stat
= desc
->len_stat
;
361 /* break if dma ownership belongs to hw */
362 if (len_stat
& DMADESC_OWNER_MASK
)
366 priv
->rx_curr_desc
++;
367 if (priv
->rx_curr_desc
== priv
->rx_ring_size
)
368 priv
->rx_curr_desc
= 0;
370 /* if the packet does not have start of packet _and_
371 * end of packet flag set, then just recycle it */
372 if ((len_stat
& DMADESC_ESOP_MASK
) != DMADESC_ESOP_MASK
) {
373 ndev
->stats
.rx_dropped
++;
378 buf
= priv
->rx_buf
[desc_idx
];
379 len
= (len_stat
& DMADESC_LENGTH_MASK
)
380 >> DMADESC_LENGTH_SHIFT
;
381 /* don't include FCS */
384 if (len
< priv
->copybreak
) {
385 unsigned int nfrag_size
= ENETSW_FRAG_SIZE(len
);
386 unsigned char *nbuf
= napi_alloc_frag(nfrag_size
);
388 if (unlikely(!nbuf
)) {
389 /* forget packet, just rearm desc */
390 ndev
->stats
.rx_dropped
++;
394 dma_sync_single_for_cpu(dev
, desc
->address
,
395 len
, DMA_FROM_DEVICE
);
396 memcpy(nbuf
+ NET_SKB_PAD
, buf
+ NET_SKB_PAD
, len
);
397 dma_sync_single_for_device(dev
, desc
->address
,
398 len
, DMA_FROM_DEVICE
);
400 frag_size
= nfrag_size
;
402 dma_unmap_single(dev
, desc
->address
,
403 priv
->rx_buf_size
, DMA_FROM_DEVICE
);
404 priv
->rx_buf
[desc_idx
] = NULL
;
405 frag_size
= priv
->rx_frag_size
;
408 skb
= napi_build_skb(buf
, frag_size
);
409 if (unlikely(!skb
)) {
411 ndev
->stats
.rx_dropped
++;
415 skb_reserve(skb
, NET_SKB_PAD
);
417 ndev
->stats
.rx_packets
++;
418 ndev
->stats
.rx_bytes
+= len
;
419 list_add_tail(&skb
->list
, &rx_list
);
420 } while (processed
< budget
);
422 list_for_each_entry(skb
, &rx_list
, list
)
423 skb
->protocol
= eth_type_trans(skb
, ndev
);
424 netif_receive_skb_list(&rx_list
);
425 priv
->rx_desc_count
-= processed
;
427 if (processed
|| !priv
->rx_desc_count
) {
428 bcm6368_enetsw_refill_rx(ndev
, true);
431 dmac_writel(priv
, DMAC_CHANCFG_EN_MASK
,
432 DMAC_CHANCFG_REG
, priv
->rx_chan
);
439 * try to or force reclaim of transmitted buffers
441 static int bcm6368_enetsw_tx_reclaim(struct net_device
*ndev
, int force
,
444 struct bcm6368_enetsw
*priv
= netdev_priv(ndev
);
445 struct platform_device
*pdev
= priv
->pdev
;
446 struct device
*dev
= &pdev
->dev
;
447 unsigned int bytes
= 0;
450 while (priv
->tx_desc_count
< priv
->tx_ring_size
) {
451 struct bcm6368_enetsw_desc
*desc
;
454 /* We run in a bh and fight against start_xmit, which
455 * is called with bh disabled */
456 spin_lock(&priv
->tx_lock
);
458 desc
= &priv
->tx_desc_cpu
[priv
->tx_dirty_desc
];
460 if (!force
&& (desc
->len_stat
& DMADESC_OWNER_MASK
)) {
461 spin_unlock(&priv
->tx_lock
);
465 /* ensure other field of the descriptor were not read
466 * before we checked ownership */
469 skb
= priv
->tx_skb
[priv
->tx_dirty_desc
];
470 priv
->tx_skb
[priv
->tx_dirty_desc
] = NULL
;
471 dma_unmap_single(dev
, desc
->address
, skb
->len
,
474 priv
->tx_dirty_desc
++;
475 if (priv
->tx_dirty_desc
== priv
->tx_ring_size
)
476 priv
->tx_dirty_desc
= 0;
477 priv
->tx_desc_count
++;
479 spin_unlock(&priv
->tx_lock
);
481 if (desc
->len_stat
& DMADESC_UNDER_MASK
)
482 ndev
->stats
.tx_errors
++;
485 napi_consume_skb(skb
, budget
);
489 netdev_completed_queue(ndev
, released
, bytes
);
491 if (netif_queue_stopped(ndev
) && released
)
492 netif_wake_queue(ndev
);
498 * poll func, called by network core
500 static int bcm6368_enetsw_poll(struct napi_struct
*napi
, int budget
)
502 struct bcm6368_enetsw
*priv
= container_of(napi
, struct bcm6368_enetsw
, napi
);
503 struct net_device
*ndev
= priv
->net_dev
;
507 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
508 DMAC_IR_REG
, priv
->rx_chan
);
509 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
510 DMAC_IR_REG
, priv
->tx_chan
);
512 /* reclaim sent skb */
513 bcm6368_enetsw_tx_reclaim(ndev
, 0, budget
);
515 spin_lock(&priv
->rx_lock
);
516 rx_work_done
= bcm6368_enetsw_receive_queue(ndev
, budget
);
517 spin_unlock(&priv
->rx_lock
);
519 if (rx_work_done
>= budget
) {
520 /* rx queue is not yet empty/clean */
524 /* no more packet in rx/tx queue, remove device from poll
526 napi_complete_done(napi
, rx_work_done
);
528 /* restore rx/tx interrupt */
529 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
530 DMAC_IRMASK_REG
, priv
->rx_chan
);
531 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
532 DMAC_IRMASK_REG
, priv
->tx_chan
);
538 * rx/tx dma interrupt handler
540 static irqreturn_t
bcm6368_enetsw_isr_dma(int irq
, void *dev_id
)
542 struct net_device
*ndev
= dev_id
;
543 struct bcm6368_enetsw
*priv
= netdev_priv(ndev
);
545 /* mask rx/tx interrupts */
546 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->rx_chan
);
547 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->tx_chan
);
549 napi_schedule(&priv
->napi
);
555 * tx request callback
558 bcm6368_enetsw_start_xmit(struct sk_buff
*skb
, struct net_device
*ndev
)
560 struct bcm6368_enetsw
*priv
= netdev_priv(ndev
);
561 struct platform_device
*pdev
= priv
->pdev
;
562 struct device
*dev
= &pdev
->dev
;
563 struct bcm6368_enetsw_desc
*desc
;
568 /* lock against tx reclaim */
569 spin_lock(&priv
->tx_lock
);
571 /* make sure the tx hw queue is not full, should not happen
572 * since we stop queue before it's the case */
573 if (unlikely(!priv
->tx_desc_count
)) {
574 netif_stop_queue(ndev
);
575 dev_err(dev
, "xmit called with no tx desc available?\n");
576 ret
= NETDEV_TX_BUSY
;
580 /* pad small packets */
581 if (skb
->len
< (ETH_ZLEN
+ ETH_FCS_LEN
)) {
582 int needed
= (ETH_ZLEN
+ ETH_FCS_LEN
) - skb
->len
;
585 if (unlikely(skb_tailroom(skb
) < needed
)) {
586 struct sk_buff
*nskb
;
588 nskb
= skb_copy_expand(skb
, 0, needed
, GFP_ATOMIC
);
590 ret
= NETDEV_TX_BUSY
;
597 data
= skb_put_zero(skb
, needed
);
600 /* fill descriptor */
601 p
= dma_map_single(dev
, skb
->data
, skb
->len
, DMA_TO_DEVICE
);
602 if (unlikely(dma_mapping_error(dev
, p
))) {
608 /* point to the next available desc */
609 desc
= &priv
->tx_desc_cpu
[priv
->tx_curr_desc
];
610 priv
->tx_skb
[priv
->tx_curr_desc
] = skb
;
613 len_stat
= (skb
->len
<< DMADESC_LENGTH_SHIFT
) & DMADESC_LENGTH_MASK
;
614 len_stat
|= DMADESC_ESOP_MASK
| DMADESC_APPEND_CRC
|
617 priv
->tx_curr_desc
++;
618 if (priv
->tx_curr_desc
== priv
->tx_ring_size
) {
619 priv
->tx_curr_desc
= 0;
620 len_stat
|= DMADESC_WRAP_MASK
;
622 priv
->tx_desc_count
--;
624 /* dma might be already polling, make sure we update desc
625 * fields in correct order */
627 desc
->len_stat
= len_stat
;
630 netdev_sent_queue(ndev
, skb
->len
);
633 dmac_writel(priv
, DMAC_CHANCFG_EN_MASK
, DMAC_CHANCFG_REG
,
636 /* stop queue if no more desc available */
637 if (!priv
->tx_desc_count
)
638 netif_stop_queue(ndev
);
640 ndev
->stats
.tx_bytes
+= skb
->len
;
641 ndev
->stats
.tx_packets
++;
645 spin_unlock(&priv
->tx_lock
);
650 * disable dma in given channel
652 static void bcm6368_enetsw_disable_dma(struct bcm6368_enetsw
*priv
, int chan
)
656 dmac_writel(priv
, 0, DMAC_CHANCFG_REG
, chan
);
661 val
= dma_readl(priv
, DMAC_CHANCFG_REG
, chan
);
662 if (!(val
& DMAC_CHANCFG_EN_MASK
))
669 static int bcm6368_enetsw_open(struct net_device
*ndev
)
671 struct bcm6368_enetsw
*priv
= netdev_priv(ndev
);
672 struct platform_device
*pdev
= priv
->pdev
;
673 struct device
*dev
= &pdev
->dev
;
679 /* mask all interrupts and request them */
680 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->rx_chan
);
681 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->tx_chan
);
683 ret
= request_irq(priv
->irq_rx
, bcm6368_enetsw_isr_dma
,
684 0, ndev
->name
, ndev
);
688 if (priv
->irq_tx
!= -1) {
689 ret
= request_irq(priv
->irq_tx
, bcm6368_enetsw_isr_dma
,
690 0, ndev
->name
, ndev
);
695 /* allocate rx dma ring */
696 size
= priv
->rx_ring_size
* sizeof(struct bcm6368_enetsw_desc
);
697 p
= dma_alloc_coherent(dev
, size
, &priv
->rx_desc_dma
, GFP_KERNEL
);
699 dev_err(dev
, "cannot allocate rx ring %u\n", size
);
705 priv
->rx_desc_alloc_size
= size
;
706 priv
->rx_desc_cpu
= p
;
708 /* allocate tx dma ring */
709 size
= priv
->tx_ring_size
* sizeof(struct bcm6368_enetsw_desc
);
710 p
= dma_alloc_coherent(dev
, size
, &priv
->tx_desc_dma
, GFP_KERNEL
);
712 dev_err(dev
, "cannot allocate tx ring\n");
714 goto out_free_rx_ring
;
718 priv
->tx_desc_alloc_size
= size
;
719 priv
->tx_desc_cpu
= p
;
721 priv
->tx_skb
= kzalloc(sizeof(struct sk_buff
*) * priv
->tx_ring_size
,
724 dev_err(dev
, "cannot allocate tx skb queue\n");
726 goto out_free_tx_ring
;
729 priv
->tx_desc_count
= priv
->tx_ring_size
;
730 priv
->tx_dirty_desc
= 0;
731 priv
->tx_curr_desc
= 0;
732 spin_lock_init(&priv
->tx_lock
);
734 /* init & fill rx ring with buffers */
735 priv
->rx_buf
= kzalloc(sizeof(unsigned char *) * priv
->rx_ring_size
,
738 dev_err(dev
, "cannot allocate rx buffer queue\n");
740 goto out_free_tx_skb
;
743 priv
->rx_desc_count
= 0;
744 priv
->rx_dirty_desc
= 0;
745 priv
->rx_curr_desc
= 0;
747 /* initialize flow control buffer allocation */
748 dma_writel(priv
, DMA_BUFALLOC_FORCE_MASK
| 0,
749 DMA_BUFALLOC_REG(priv
->rx_chan
));
751 if (bcm6368_enetsw_refill_rx(ndev
, false)) {
752 dev_err(dev
, "cannot allocate rx buffer queue\n");
757 /* write rx & tx ring addresses */
758 dmas_writel(priv
, priv
->rx_desc_dma
,
759 DMAS_RSTART_REG
, priv
->rx_chan
);
760 dmas_writel(priv
, priv
->tx_desc_dma
,
761 DMAS_RSTART_REG
, priv
->tx_chan
);
763 /* clear remaining state ram for rx & tx channel */
764 dmas_writel(priv
, 0, DMAS_SRAM2_REG
, priv
->rx_chan
);
765 dmas_writel(priv
, 0, DMAS_SRAM2_REG
, priv
->tx_chan
);
766 dmas_writel(priv
, 0, DMAS_SRAM3_REG
, priv
->rx_chan
);
767 dmas_writel(priv
, 0, DMAS_SRAM3_REG
, priv
->tx_chan
);
768 dmas_writel(priv
, 0, DMAS_SRAM4_REG
, priv
->rx_chan
);
769 dmas_writel(priv
, 0, DMAS_SRAM4_REG
, priv
->tx_chan
);
771 /* set dma maximum burst len */
772 dmac_writel(priv
, ENETSW_DMA_MAXBURST
,
773 DMAC_MAXBURST_REG
, priv
->rx_chan
);
774 dmac_writel(priv
, ENETSW_DMA_MAXBURST
,
775 DMAC_MAXBURST_REG
, priv
->tx_chan
);
777 /* set flow control low/high threshold to 1/3 / 2/3 */
778 val
= priv
->rx_ring_size
/ 3;
779 dma_writel(priv
, val
, DMA_FLOWCL_REG(priv
->rx_chan
));
780 val
= (priv
->rx_ring_size
* 2) / 3;
781 dma_writel(priv
, val
, DMA_FLOWCH_REG(priv
->rx_chan
));
783 /* all set, enable mac and interrupts, start dma engine and
784 * kick rx dma channel
787 dma_writel(priv
, DMA_CFG_EN_MASK
, DMA_CFG_REG
);
788 dmac_writel(priv
, DMAC_CHANCFG_EN_MASK
,
789 DMAC_CHANCFG_REG
, priv
->rx_chan
);
791 /* watch "packet transferred" interrupt in rx and tx */
792 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
793 DMAC_IR_REG
, priv
->rx_chan
);
794 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
795 DMAC_IR_REG
, priv
->tx_chan
);
797 /* make sure we enable napi before rx interrupt */
798 napi_enable(&priv
->napi
);
800 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
801 DMAC_IRMASK_REG
, priv
->rx_chan
);
802 dmac_writel(priv
, DMAC_IR_PKTDONE_MASK
,
803 DMAC_IRMASK_REG
, priv
->tx_chan
);
805 netif_carrier_on(ndev
);
806 netif_start_queue(ndev
);
811 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
812 struct bcm6368_enetsw_desc
*desc
;
814 if (!priv
->rx_buf
[i
])
817 desc
= &priv
->rx_desc_cpu
[i
];
818 dma_unmap_single(dev
, desc
->address
, priv
->rx_buf_size
,
820 skb_free_frag(priv
->rx_buf
[i
]);
828 dma_free_coherent(dev
, priv
->tx_desc_alloc_size
,
829 priv
->tx_desc_cpu
, priv
->tx_desc_dma
);
832 dma_free_coherent(dev
, priv
->rx_desc_alloc_size
,
833 priv
->rx_desc_cpu
, priv
->rx_desc_dma
);
836 if (priv
->irq_tx
!= -1)
837 free_irq(priv
->irq_tx
, ndev
);
840 free_irq(priv
->irq_rx
, ndev
);
846 static int bcm6368_enetsw_stop(struct net_device
*ndev
)
848 struct bcm6368_enetsw
*priv
= netdev_priv(ndev
);
849 struct platform_device
*pdev
= priv
->pdev
;
850 struct device
*dev
= &pdev
->dev
;
853 netif_stop_queue(ndev
);
854 napi_disable(&priv
->napi
);
855 del_timer_sync(&priv
->rx_timeout
);
857 /* mask all interrupts */
858 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->rx_chan
);
859 dmac_writel(priv
, 0, DMAC_IRMASK_REG
, priv
->tx_chan
);
861 /* disable dma & mac */
862 bcm6368_enetsw_disable_dma(priv
, priv
->tx_chan
);
863 bcm6368_enetsw_disable_dma(priv
, priv
->rx_chan
);
865 /* force reclaim of all tx buffers */
866 bcm6368_enetsw_tx_reclaim(ndev
, 1, 0);
868 /* free the rx buffer ring */
869 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
870 struct bcm6368_enetsw_desc
*desc
;
872 if (!priv
->rx_buf
[i
])
875 desc
= &priv
->rx_desc_cpu
[i
];
876 dma_unmap_single_attrs(dev
, desc
->address
, priv
->rx_buf_size
,
878 DMA_ATTR_SKIP_CPU_SYNC
);
879 skb_free_frag(priv
->rx_buf
[i
]);
882 /* free remaining allocated memory */
885 dma_free_coherent(dev
, priv
->rx_desc_alloc_size
,
886 priv
->rx_desc_cpu
, priv
->rx_desc_dma
);
887 dma_free_coherent(dev
, priv
->tx_desc_alloc_size
,
888 priv
->tx_desc_cpu
, priv
->tx_desc_dma
);
889 if (priv
->irq_tx
!= -1)
890 free_irq(priv
->irq_tx
, ndev
);
891 free_irq(priv
->irq_rx
, ndev
);
893 netdev_reset_queue(ndev
);
898 static const struct net_device_ops bcm6368_enetsw_ops
= {
899 .ndo_open
= bcm6368_enetsw_open
,
900 .ndo_stop
= bcm6368_enetsw_stop
,
901 .ndo_start_xmit
= bcm6368_enetsw_start_xmit
,
904 static int bcm6368_enetsw_probe(struct platform_device
*pdev
)
906 struct device
*dev
= &pdev
->dev
;
907 struct device_node
*node
= dev
->of_node
;
908 struct bcm6368_enetsw
*priv
;
909 struct net_device
*ndev
;
910 struct resource
*res
;
915 ndev
= devm_alloc_etherdev(dev
, sizeof(*priv
));
919 platform_set_drvdata(pdev
, ndev
);
920 SET_NETDEV_DEV(ndev
, dev
);
922 priv
= netdev_priv(ndev
);
924 priv
->net_dev
= ndev
;
926 priv
->num_pms
= of_count_phandle_with_args(node
, "power-domains",
927 "#power-domain-cells");
928 if (priv
->num_pms
> 1) {
929 priv
->pm
= devm_kcalloc(dev
, priv
->num_pms
,
930 sizeof(struct device
*), GFP_KERNEL
);
934 priv
->link_pm
= devm_kcalloc(dev
, priv
->num_pms
,
935 sizeof(struct device_link
*),
940 for (i
= 0; i
< priv
->num_pms
; i
++) {
941 priv
->pm
[i
] = genpd_dev_pm_attach_by_id(dev
, i
);
942 if (IS_ERR(priv
->pm
[i
])) {
943 dev_err(dev
, "error getting pm %d\n", i
);
947 priv
->link_pm
[i
] = device_link_add(dev
, priv
->pm
[i
],
948 DL_FLAG_STATELESS
| DL_FLAG_PM_RUNTIME
|
953 pm_runtime_enable(dev
);
954 pm_runtime_no_callbacks(dev
);
955 ret
= pm_runtime_get_sync(dev
);
957 pm_runtime_disable(dev
);
958 dev_info(dev
, "PM prober defer: ret=%d\n", ret
);
959 return -EPROBE_DEFER
;
962 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dma");
963 priv
->dma_base
= devm_ioremap_resource(dev
, res
);
964 if (IS_ERR_OR_NULL(priv
->dma_base
))
965 return PTR_ERR(priv
->dma_base
);
967 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
,
969 priv
->dma_chan
= devm_ioremap_resource(dev
, res
);
970 if (IS_ERR_OR_NULL(priv
->dma_chan
))
971 return PTR_ERR(priv
->dma_chan
);
973 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dma-sram");
974 priv
->dma_sram
= devm_ioremap_resource(dev
, res
);
975 if (IS_ERR_OR_NULL(priv
->dma_sram
))
976 return PTR_ERR(priv
->dma_sram
);
978 priv
->irq_rx
= platform_get_irq_byname(pdev
, "rx");
982 priv
->irq_tx
= platform_get_irq_byname(pdev
, "tx");
985 else if (priv
->irq_tx
< 0)
988 if (device_property_read_u32(dev
, "dma-rx", &priv
->rx_chan
))
991 if (device_property_read_u32(dev
, "dma-tx", &priv
->tx_chan
))
994 priv
->rx_ring_size
= ENETSW_DEF_RX_DESC
;
995 priv
->tx_ring_size
= ENETSW_DEF_TX_DESC
;
996 priv
->copybreak
= ENETSW_DEF_CPY_BREAK
;
998 of_get_mac_address(node
, ndev
->dev_addr
);
999 if (is_valid_ether_addr(ndev
->dev_addr
)) {
1000 dev_info(dev
, "mtd mac %pM\n", ndev
->dev_addr
);
1002 random_ether_addr(ndev
->dev_addr
);
1003 dev_info(dev
, "random mac %pM\n", ndev
->dev_addr
);
1006 priv
->rx_buf_size
= ALIGN(ndev
->mtu
+ ENETSW_MTU_OVERHEAD
,
1007 ENETSW_DMA_MAXBURST
* 4);
1009 priv
->rx_frag_size
= ENETSW_FRAG_SIZE(priv
->rx_buf_size
);
1011 priv
->num_clocks
= of_clk_get_parent_count(node
);
1012 if (priv
->num_clocks
) {
1013 priv
->clock
= devm_kcalloc(dev
, priv
->num_clocks
,
1014 sizeof(struct clk
*), GFP_KERNEL
);
1015 if (IS_ERR_OR_NULL(priv
->clock
))
1016 return PTR_ERR(priv
->clock
);
1018 for (i
= 0; i
< priv
->num_clocks
; i
++) {
1019 priv
->clock
[i
] = of_clk_get(node
, i
);
1020 if (IS_ERR(priv
->clock
[i
])) {
1021 dev_err(dev
, "error getting clock %d\n", i
);
1022 return PTR_ERR(priv
->clock
[i
]);
1025 ret
= clk_prepare_enable(priv
->clock
[i
]);
1027 dev_err(dev
, "error enabling clock %d\n", i
);
1032 num_resets
= of_count_phandle_with_args(node
, "resets",
1035 priv
->num_resets
= num_resets
;
1037 priv
->num_resets
= 0;
1038 if (priv
->num_resets
) {
1039 priv
->reset
= devm_kcalloc(dev
, priv
->num_resets
,
1040 sizeof(struct reset_control
*),
1042 if (IS_ERR_OR_NULL(priv
->reset
))
1043 return PTR_ERR(priv
->reset
);
1045 for (i
= 0; i
< priv
->num_resets
; i
++) {
1046 priv
->reset
[i
] = devm_reset_control_get_by_index(dev
, i
);
1047 if (IS_ERR(priv
->reset
[i
])) {
1048 dev_err(dev
, "error getting reset %d\n", i
);
1049 return PTR_ERR(priv
->reset
[i
]);
1052 ret
= reset_control_reset(priv
->reset
[i
]);
1054 dev_err(dev
, "error performing reset %d\n", i
);
1059 spin_lock_init(&priv
->rx_lock
);
1061 timer_setup(&priv
->rx_timeout
, bcm6368_enetsw_refill_rx_timer
, 0);
1063 /* register netdevice */
1064 ndev
->netdev_ops
= &bcm6368_enetsw_ops
;
1065 ndev
->min_mtu
= ETH_ZLEN
;
1066 ndev
->mtu
= ETH_DATA_LEN
+ ENETSW_TAG_SIZE
;
1067 ndev
->max_mtu
= ETH_DATA_LEN
+ ENETSW_TAG_SIZE
;
1068 netif_napi_add(ndev
, &priv
->napi
, bcm6368_enetsw_poll
, 16);
1070 ret
= devm_register_netdev(dev
, ndev
);
1072 netif_napi_del(&priv
->napi
);
1073 goto out_disable_clk
;
1076 netif_carrier_off(ndev
);
1078 dev_info(dev
, "%s at 0x%px, IRQ %d\n", ndev
->name
, priv
->dma_base
, ndev
->irq
);
1083 for (i
= 0; i
< priv
->num_resets
; i
++)
1084 reset_control_assert(priv
->reset
[i
]);
1086 for (i
= 0; i
< priv
->num_clocks
; i
++)
1087 clk_disable_unprepare(priv
->clock
[i
]);
1092 static int bcm6368_enetsw_remove(struct platform_device
*pdev
)
1094 struct device
*dev
= &pdev
->dev
;
1095 struct net_device
*ndev
= platform_get_drvdata(pdev
);
1096 struct bcm6368_enetsw
*priv
= netdev_priv(ndev
);
1099 pm_runtime_put_sync(dev
);
1100 for (i
= 0; priv
->pm
&& i
< priv
->num_pms
; i
++) {
1101 dev_pm_domain_detach(priv
->pm
[i
], true);
1102 device_link_del(priv
->link_pm
[i
]);
1105 for (i
= 0; i
< priv
->num_resets
; i
++)
1106 reset_control_assert(priv
->reset
[i
]);
1108 for (i
= 0; i
< priv
->num_clocks
; i
++)
1109 clk_disable_unprepare(priv
->clock
[i
]);
1114 static const struct of_device_id bcm6368_enetsw_of_match
[] = {
1115 { .compatible
= "brcm,bcm6318-enetsw", },
1116 { .compatible
= "brcm,bcm6328-enetsw", },
1117 { .compatible
= "brcm,bcm6362-enetsw", },
1118 { .compatible
= "brcm,bcm6368-enetsw", },
1119 { .compatible
= "brcm,bcm63268-enetsw", },
1122 MODULE_DEVICE_TABLE(of
, bcm6368_enetsw_of_match
);
1124 static struct platform_driver bcm6368_enetsw_driver
= {
1126 .name
= "bcm6368-enetsw",
1127 .of_match_table
= of_match_ptr(bcm6368_enetsw_of_match
),
1129 .probe
= bcm6368_enetsw_probe
,
1130 .remove
= bcm6368_enetsw_remove
,
1132 module_platform_driver(bcm6368_enetsw_driver
);
1134 MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>");
1135 MODULE_DESCRIPTION("BCM6368 Ethernet Switch Controller Driver");
1136 MODULE_LICENSE("GPL v2");
1137 MODULE_ALIAS("platform:bcm6368-enetsw");