target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6368-enetsw.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * BCM6368 Ethernet Switch Controller Driver
   4  *
   5  * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
   6  * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
   7  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/ethtool.h>
  15 #include <linux/if_vlan.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/of_clk.h>
  18 #include <linux/of_net.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_domain.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/reset.h>
  23
  24 /* MTU */
  25 #define ENETSW_TAG_SIZE                 6
  26 #define ENETSW_MTU_OVERHEAD             (VLAN_ETH_HLEN + VLAN_HLEN + \
  27                                          ENETSW_TAG_SIZE)
  28 #define ENETSW_FRAG_SIZE(x)             (SKB_DATA_ALIGN(NET_SKB_PAD + x + \
  29                                          SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
  30
  31 /* default number of descriptor */
  32 #define ENETSW_DEF_RX_DESC              64
  33 #define ENETSW_DEF_TX_DESC              32
  34 #define ENETSW_DEF_CPY_BREAK            128
  35
  36 /* maximum burst len for dma (4 bytes unit) */
  37 #define ENETSW_DMA_MAXBURST             8
  38
  39 /* DMA channels */
  40 #define DMA_CHAN_WIDTH                  0x10
  41
  42 /* Controller Configuration Register */
  43 #define DMA_CFG_REG                     0x0
  44 #define DMA_CFG_EN_SHIFT                0
  45 #define DMA_CFG_EN_MASK                 (1 << DMA_CFG_EN_SHIFT)
  46 #define DMA_CFG_FLOWCH_MASK(x)          (1 << ((x >> 1) + 1))
  47
  48 /* Flow Control Descriptor Low Threshold register */
  49 #define DMA_FLOWCL_REG(x)               (0x4 + (x) * 6)
  50
  51 /* Flow Control Descriptor High Threshold register */
  52 #define DMA_FLOWCH_REG(x)               (0x8 + (x) * 6)
  53
  54 /* Flow Control Descriptor Buffer Alloca Threshold register */
  55 #define DMA_BUFALLOC_REG(x)             (0xc + (x) * 6)
  56 #define DMA_BUFALLOC_FORCE_SHIFT        31
  57 #define DMA_BUFALLOC_FORCE_MASK         (1 << DMA_BUFALLOC_FORCE_SHIFT)
  58
  59 /* Channel Configuration register */
  60 #define DMAC_CHANCFG_REG                0x0
  61 #define DMAC_CHANCFG_EN_SHIFT           0
  62 #define DMAC_CHANCFG_EN_MASK            (1 << DMAC_CHANCFG_EN_SHIFT)
  63 #define DMAC_CHANCFG_PKTHALT_SHIFT      1
  64 #define DMAC_CHANCFG_PKTHALT_MASK       (1 << DMAC_CHANCFG_PKTHALT_SHIFT)
  65 #define DMAC_CHANCFG_BUFHALT_SHIFT      2
  66 #define DMAC_CHANCFG_BUFHALT_MASK       (1 << DMAC_CHANCFG_BUFHALT_SHIFT)
  67 #define DMAC_CHANCFG_CHAINING_SHIFT     2
  68 #define DMAC_CHANCFG_CHAINING_MASK      (1 << DMAC_CHANCFG_CHAINING_SHIFT)
  69 #define DMAC_CHANCFG_WRAP_EN_SHIFT      3
  70 #define DMAC_CHANCFG_WRAP_EN_MASK       (1 << DMAC_CHANCFG_WRAP_EN_SHIFT)
  71 #define DMAC_CHANCFG_FLOWC_EN_SHIFT     4
  72 #define DMAC_CHANCFG_FLOWC_EN_MASK      (1 << DMAC_CHANCFG_FLOWC_EN_SHIFT)
  73
  74 /* Interrupt Control/Status register */
  75 #define DMAC_IR_REG                     0x4
  76 #define DMAC_IR_BUFDONE_MASK            (1 << 0)
  77 #define DMAC_IR_PKTDONE_MASK            (1 << 1)
  78 #define DMAC_IR_NOTOWNER_MASK           (1 << 2)
  79
  80 /* Interrupt Mask register */
  81 #define DMAC_IRMASK_REG                 0x8
  82
  83 /* Maximum Burst Length */
  84 #define DMAC_MAXBURST_REG               0xc
  85
  86 /* Ring Start Address register */
  87 #define DMAS_RSTART_REG                 0x0
  88
  89 /* State Ram Word 2 */
  90 #define DMAS_SRAM2_REG                  0x4
  91
  92 /* State Ram Word 3 */
  93 #define DMAS_SRAM3_REG                  0x8
  94
  95 /* State Ram Word 4 */
  96 #define DMAS_SRAM4_REG                  0xc
  97
  98 struct bcm6368_enetsw_desc {
  99         u32 len_stat;
 100         u32 address;
 101 };
 102
 103 /* control */
 104 #define DMADESC_LENGTH_SHIFT            16
 105 #define DMADESC_LENGTH_MASK             (0xfff << DMADESC_LENGTH_SHIFT)
 106 #define DMADESC_OWNER_MASK              (1 << 15)
 107 #define DMADESC_EOP_MASK                (1 << 14)
 108 #define DMADESC_SOP_MASK                (1 << 13)
 109 #define DMADESC_ESOP_MASK               (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
 110 #define DMADESC_WRAP_MASK               (1 << 12)
 111 #define DMADESC_USB_NOZERO_MASK         (1 << 1)
 112 #define DMADESC_USB_ZERO_MASK           (1 << 0)
 113
 114 /* status */
 115 #define DMADESC_UNDER_MASK              (1 << 9)
 116 #define DMADESC_APPEND_CRC              (1 << 8)
 117 #define DMADESC_OVSIZE_MASK             (1 << 4)
 118 #define DMADESC_RXER_MASK               (1 << 2)
 119 #define DMADESC_CRC_MASK                (1 << 1)
 120 #define DMADESC_OV_MASK                 (1 << 0)
 121 #define DMADESC_ERR_MASK                (DMADESC_UNDER_MASK | \
 122                                          DMADESC_OVSIZE_MASK | \
 123                                          DMADESC_RXER_MASK | \
 124                                          DMADESC_CRC_MASK | \
 125                                          DMADESC_OV_MASK)
 126
 127 struct bcm6368_enetsw {
 128         void __iomem *dma_base;
 129         void __iomem *dma_chan;
 130         void __iomem *dma_sram;
 131
 132         struct device **pm;
 133         struct device_link **link_pm;
 134         int num_pms;
 135
 136         struct clk **clock;
 137         unsigned int num_clocks;
 138
 139         struct reset_control **reset;
 140         unsigned int num_resets;
 141
 142         int copybreak;
 143
 144         int irq_rx;
 145         int irq_tx;
 146
 147         /* hw view of rx & tx dma ring */
 148         dma_addr_t rx_desc_dma;
 149         dma_addr_t tx_desc_dma;
 150
 151         /* allocated size (in bytes) for rx & tx dma ring */
 152         unsigned int rx_desc_alloc_size;
 153         unsigned int tx_desc_alloc_size;
 154
 155         struct napi_struct napi;
 156
 157         /* dma channel id for rx */
 158         int rx_chan;
 159
 160         /* number of dma desc in rx ring */
 161         int rx_ring_size;
 162
 163         /* cpu view of rx dma ring */
 164         struct bcm6368_enetsw_desc *rx_desc_cpu;
 165
 166         /* current number of armed descriptor given to hardware for rx */
 167         int rx_desc_count;
 168
 169         /* next rx descriptor to fetch from hardware */
 170         int rx_curr_desc;
 171
 172         /* next dirty rx descriptor to refill */
 173         int rx_dirty_desc;
 174
 175         /* size of allocated rx buffer */
 176         unsigned int rx_buf_size;
 177
 178         /* size of allocated rx frag */
 179         unsigned int rx_frag_size;
 180
 181         /* list of buffer given to hw for rx */
 182         unsigned char **rx_buf;
 183
 184         /* used when rx buffer allocation failed, so we defer rx queue
 185          * refill */
 186         struct timer_list rx_timeout;
 187
 188         /* lock rx_timeout against rx normal operation */
 189         spinlock_t rx_lock;
 190
 191         /* dma channel id for tx */
 192         int tx_chan;
 193
 194         /* number of dma desc in tx ring */
 195         int tx_ring_size;
 196
 197         /* maximum dma burst size */
 198         int dma_maxburst;
 199
 200         /* cpu view of rx dma ring */
 201         struct bcm6368_enetsw_desc *tx_desc_cpu;
 202
 203         /* number of available descriptor for tx */
 204         int tx_desc_count;
 205
 206         /* next tx descriptor avaiable */
 207         int tx_curr_desc;
 208
 209         /* next dirty tx descriptor to reclaim */
 210         int tx_dirty_desc;
 211
 212         /* list of skb given to hw for tx */
 213         struct sk_buff **tx_skb;
 214
 215         /* lock used by tx reclaim and xmit */
 216         spinlock_t tx_lock;
 217
 218         /* network device reference */
 219         struct net_device *net_dev;
 220
 221         /* platform device reference */
 222         struct platform_device *pdev;
 223
 224         /* dma channel enable mask */
 225         u32 dma_chan_en_mask;
 226
 227         /* dma channel interrupt mask */
 228         u32 dma_chan_int_mask;
 229
 230         /* dma channel width */
 231         unsigned int dma_chan_width;
 232 };
 233
 234 static inline void dma_writel(struct bcm6368_enetsw *priv, u32 val, u32 off)
 235 {
 236         __raw_writel(val, priv->dma_base + off);
 237 }
 238
 239 static inline u32 dma_readl(struct bcm6368_enetsw *priv, u32 off, int chan)
 240 {
 241         return __raw_readl(priv->dma_chan + off + chan * priv->dma_chan_width);
 242 }
 243
 244 static inline void dmac_writel(struct bcm6368_enetsw *priv, u32 val,
 245                                     u32 off, int chan)
 246 {
 247         __raw_writel(val, priv->dma_chan + off + chan * priv->dma_chan_width);
 248 }
 249
 250 static inline void dmas_writel(struct bcm6368_enetsw *priv, u32 val,
 251                                     u32 off, int chan)
 252 {
 253         __raw_writel(val, priv->dma_sram + off + chan * priv->dma_chan_width);
 254 }
 255
 256 /*
 257  * refill rx queue
 258  */
 259 static int bcm6368_enetsw_refill_rx(struct net_device *dev, bool napi_mode)
 260 {
 261         struct bcm6368_enetsw *priv = netdev_priv(dev);
 262
 263         while (priv->rx_desc_count < priv->rx_ring_size) {
 264                 struct bcm6368_enetsw_desc *desc;
 265                 int desc_idx;
 266                 u32 len_stat;
 267
 268                 desc_idx = priv->rx_dirty_desc;
 269                 desc = &priv->rx_desc_cpu[desc_idx];
 270
 271                 if (!priv->rx_buf[desc_idx]) {
 272                         unsigned char *buf;
 273
 274                         if (likely(napi_mode))
 275                                 buf = napi_alloc_frag(priv->rx_frag_size);
 276                         else
 277                                 buf = netdev_alloc_frag(priv->rx_frag_size);
 278
 279                         if (unlikely(!buf))
 280                                 break;
 281
 282                         priv->rx_buf[desc_idx] = buf;
 283                         desc->address = dma_map_single(&priv->pdev->dev,
 284                                                        buf + NET_SKB_PAD,
 285                                                        priv->rx_buf_size,
 286                                                        DMA_FROM_DEVICE);
 287                 }
 288
 289                 len_stat = priv->rx_buf_size << DMADESC_LENGTH_SHIFT;
 290                 len_stat |= DMADESC_OWNER_MASK;
 291                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 292                         len_stat |= DMADESC_WRAP_MASK;
 293                         priv->rx_dirty_desc = 0;
 294                 } else {
 295                         priv->rx_dirty_desc++;
 296                 }
 297                 wmb();
 298                 desc->len_stat = len_stat;
 299
 300                 priv->rx_desc_count++;
 301
 302                 /* tell dma engine we allocated one buffer */
 303                 dma_writel(priv, 1, DMA_BUFALLOC_REG(priv->rx_chan));
 304         }
 305
 306         /* If rx ring is still empty, set a timer to try allocating
 307          * again at a later time. */
 308         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 309                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 310                 priv->rx_timeout.expires = jiffies + HZ;
 311                 add_timer(&priv->rx_timeout);
 312         }
 313
 314         return 0;
 315 }
 316
 317 /*
 318  * timer callback to defer refill rx queue in case we're OOM
 319  */
 320 static void bcm6368_enetsw_refill_rx_timer(struct timer_list *t)
 321 {
 322         struct bcm6368_enetsw *priv = from_timer(priv, t, rx_timeout);
 323         struct net_device *dev = priv->net_dev;
 324
 325         spin_lock(&priv->rx_lock);
 326         bcm6368_enetsw_refill_rx(dev, false);
 327         spin_unlock(&priv->rx_lock);
 328 }
 329
 330 /*
 331  * extract packet from rx queue
 332  */
 333 static int bcm6368_enetsw_receive_queue(struct net_device *dev, int budget)
 334 {
 335         struct bcm6368_enetsw *priv = netdev_priv(dev);
 336         struct device *kdev = &priv->pdev->dev;
 337         struct list_head rx_list;
 338         int processed = 0;
 339
 340         INIT_LIST_HEAD(&rx_list);
 341
 342         /* don't scan ring further than number of refilled
 343          * descriptor */
 344         if (budget > priv->rx_desc_count)
 345                 budget = priv->rx_desc_count;
 346
 347         do {
 348                 struct bcm6368_enetsw_desc *desc;
 349                 unsigned int frag_size;
 350                 struct sk_buff *skb;
 351                 unsigned char *buf;
 352                 int desc_idx;
 353                 u32 len_stat;
 354                 unsigned int len;
 355
 356                 desc_idx = priv->rx_curr_desc;
 357                 desc = &priv->rx_desc_cpu[desc_idx];
 358
 359                 /* make sure we actually read the descriptor status at
 360                  * each loop */
 361                 rmb();
 362
 363                 len_stat = desc->len_stat;
 364
 365                 /* break if dma ownership belongs to hw */
 366                 if (len_stat & DMADESC_OWNER_MASK)
 367                         break;
 368
 369                 processed++;
 370                 priv->rx_curr_desc++;
 371                 if (priv->rx_curr_desc == priv->rx_ring_size)
 372                         priv->rx_curr_desc = 0;
 373
 374                 /* if the packet does not have start of packet _and_
 375                  * end of packet flag set, then just recycle it */
 376                 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 377                         dev->stats.rx_dropped++;
 378                         continue;
 379                 }
 380
 381                 /* valid packet */
 382                 buf = priv->rx_buf[desc_idx];
 383                 len = (len_stat & DMADESC_LENGTH_MASK)
 384                       >> DMADESC_LENGTH_SHIFT;
 385                 /* don't include FCS */
 386                 len -= 4;
 387
 388                 if (len < priv->copybreak) {
 389                         unsigned int nfrag_size = ENETSW_FRAG_SIZE(len);
 390                         unsigned char *nbuf = napi_alloc_frag(nfrag_size);
 391
 392                         if (unlikely(!nbuf)) {
 393                                 /* forget packet, just rearm desc */
 394                                 dev->stats.rx_dropped++;
 395                                 continue;
 396                         }
 397
 398                         dma_sync_single_for_cpu(kdev, desc->address,
 399                                                 len, DMA_FROM_DEVICE);
 400                         memcpy(nbuf + NET_SKB_PAD, buf + NET_SKB_PAD, len);
 401                         dma_sync_single_for_device(kdev, desc->address,
 402                                                    len, DMA_FROM_DEVICE);
 403                         buf = nbuf;
 404                         frag_size = nfrag_size;
 405                 } else {
 406                         dma_unmap_single(kdev, desc->address,
 407                                          priv->rx_buf_size, DMA_FROM_DEVICE);
 408                         priv->rx_buf[desc_idx] = NULL;
 409                         frag_size = priv->rx_frag_size;
 410                 }
 411
 412                 skb = napi_build_skb(buf, frag_size);
 413                 if (unlikely(!skb)) {
 414                         skb_free_frag(buf);
 415                         dev->stats.rx_dropped++;
 416                         continue;
 417                 }
 418
 419                 skb_reserve(skb, NET_SKB_PAD);
 420                 skb_put(skb, len);
 421                 skb->protocol = eth_type_trans(skb, dev);
 422                 dev->stats.rx_packets++;
 423                 dev->stats.rx_bytes += len;
 424                 list_add_tail(&skb->list, &rx_list);
 425         } while (processed < budget);
 426
 427         netif_receive_skb_list(&rx_list);
 428         priv->rx_desc_count -= processed;
 429
 430         if (processed || !priv->rx_desc_count) {
 431                 bcm6368_enetsw_refill_rx(dev, true);
 432
 433                 /* kick rx dma */
 434                 dmac_writel(priv, priv->dma_chan_en_mask,
 435                             DMAC_CHANCFG_REG, priv->rx_chan);
 436         }
 437
 438         return processed;
 439 }
 440
 441 /*
 442  * try to or force reclaim of transmitted buffers
 443  */
 444 static int bcm6368_enetsw_tx_reclaim(struct net_device *dev, int force)
 445 {
 446         struct bcm6368_enetsw *priv = netdev_priv(dev);
 447         int released = 0;
 448
 449         while (priv->tx_desc_count < priv->tx_ring_size) {
 450                 struct bcm6368_enetsw_desc *desc;
 451                 struct sk_buff *skb;
 452
 453                 /* We run in a bh and fight against start_xmit, which
 454                  * is called with bh disabled */
 455                 spin_lock(&priv->tx_lock);
 456
 457                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 458
 459                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 460                         spin_unlock(&priv->tx_lock);
 461                         break;
 462                 }
 463
 464                 /* ensure other field of the descriptor were not read
 465                  * before we checked ownership */
 466                 rmb();
 467
 468                 skb = priv->tx_skb[priv->tx_dirty_desc];
 469                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 470                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 471                                  DMA_TO_DEVICE);
 472
 473                 priv->tx_dirty_desc++;
 474                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 475                         priv->tx_dirty_desc = 0;
 476                 priv->tx_desc_count++;
 477
 478                 spin_unlock(&priv->tx_lock);
 479
 480                 if (desc->len_stat & DMADESC_UNDER_MASK)
 481                         dev->stats.tx_errors++;
 482
 483                 napi_consume_skb(skb, !force);
 484                 released++;
 485         }
 486
 487         if (netif_queue_stopped(dev) && released)
 488                 netif_wake_queue(dev);
 489
 490         return released;
 491 }
 492
 493 /*
 494  * poll func, called by network core
 495  */
 496 static int bcm6368_enetsw_poll(struct napi_struct *napi, int budget)
 497 {
 498         struct bcm6368_enetsw *priv = container_of(napi, struct bcm6368_enetsw, napi);
 499         struct net_device *dev = priv->net_dev;
 500         int rx_work_done;
 501
 502         /* ack interrupts */
 503         dmac_writel(priv, priv->dma_chan_int_mask,
 504                          DMAC_IR_REG, priv->rx_chan);
 505         dmac_writel(priv, priv->dma_chan_int_mask,
 506                          DMAC_IR_REG, priv->tx_chan);
 507
 508         /* reclaim sent skb */
 509         bcm6368_enetsw_tx_reclaim(dev, 0);
 510
 511         spin_lock(&priv->rx_lock);
 512         rx_work_done = bcm6368_enetsw_receive_queue(dev, budget);
 513         spin_unlock(&priv->rx_lock);
 514
 515         if (rx_work_done >= budget) {
 516                 /* rx queue is not yet empty/clean */
 517                 return rx_work_done;
 518         }
 519
 520         /* no more packet in rx/tx queue, remove device from poll
 521          * queue */
 522         napi_complete_done(napi, rx_work_done);
 523
 524         /* restore rx/tx interrupt */
 525         dmac_writel(priv, priv->dma_chan_int_mask,
 526                          DMAC_IRMASK_REG, priv->rx_chan);
 527         dmac_writel(priv, priv->dma_chan_int_mask,
 528                          DMAC_IRMASK_REG, priv->tx_chan);
 529
 530         return rx_work_done;
 531 }
 532
 533 /*
 534  * rx/tx dma interrupt handler
 535  */
 536 static irqreturn_t bcm6368_enetsw_isr_dma(int irq, void *dev_id)
 537 {
 538         struct net_device *dev = dev_id;
 539         struct bcm6368_enetsw *priv = netdev_priv(dev);
 540
 541         /* mask rx/tx interrupts */
 542         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 543         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 544
 545         napi_schedule(&priv->napi);
 546
 547         return IRQ_HANDLED;
 548 }
 549
 550 /*
 551  * tx request callback
 552  */
 553 static netdev_tx_t
 554 bcm6368_enetsw_start_xmit(struct sk_buff *skb, struct net_device *dev)
 555 {
 556         struct bcm6368_enetsw *priv = netdev_priv(dev);
 557         struct bcm6368_enetsw_desc *desc;
 558         u32 len_stat;
 559         netdev_tx_t ret;
 560
 561         /* lock against tx reclaim */
 562         spin_lock(&priv->tx_lock);
 563
 564         /* make sure the tx hw queue is not full, should not happen
 565          * since we stop queue before it's the case */
 566         if (unlikely(!priv->tx_desc_count)) {
 567                 netif_stop_queue(dev);
 568                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 569                         "available?\n");
 570                 ret = NETDEV_TX_BUSY;
 571                 goto out_unlock;
 572         }
 573
 574         /* pad small packets */
 575         if (skb->len < (ETH_ZLEN + ETH_FCS_LEN)) {
 576                 int needed = (ETH_ZLEN + ETH_FCS_LEN) - skb->len;
 577                 char *data;
 578
 579                 if (unlikely(skb_tailroom(skb) < needed)) {
 580                         struct sk_buff *nskb;
 581
 582                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 583                         if (!nskb) {
 584                                 ret = NETDEV_TX_BUSY;
 585                                 goto out_unlock;
 586                         }
 587
 588                         dev_kfree_skb(skb);
 589                         skb = nskb;
 590                 }
 591                 data = skb_put_zero(skb, needed);
 592         }
 593
 594         /* point to the next available desc */
 595         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 596         priv->tx_skb[priv->tx_curr_desc] = skb;
 597
 598         /* fill descriptor */
 599         desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 600                                        DMA_TO_DEVICE);
 601
 602         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 603         len_stat |= DMADESC_ESOP_MASK | DMADESC_APPEND_CRC |
 604                     DMADESC_OWNER_MASK;
 605
 606         priv->tx_curr_desc++;
 607         if (priv->tx_curr_desc == priv->tx_ring_size) {
 608                 priv->tx_curr_desc = 0;
 609                 len_stat |= DMADESC_WRAP_MASK;
 610         }
 611         priv->tx_desc_count--;
 612
 613         /* dma might be already polling, make sure we update desc
 614          * fields in correct order */
 615         wmb();
 616         desc->len_stat = len_stat;
 617         wmb();
 618
 619         /* kick tx dma */
 620         dmac_writel(priv, priv->dma_chan_en_mask, DMAC_CHANCFG_REG,
 621                     priv->tx_chan);
 622
 623         /* stop queue if no more desc available */
 624         if (!priv->tx_desc_count)
 625                 netif_stop_queue(dev);
 626
 627         dev->stats.tx_bytes += skb->len;
 628         dev->stats.tx_packets++;
 629         ret = NETDEV_TX_OK;
 630
 631 out_unlock:
 632         spin_unlock(&priv->tx_lock);
 633         return ret;
 634 }
 635
 636 /*
 637  * disable dma in given channel
 638  */
 639 static void bcm6368_enetsw_disable_dma(struct bcm6368_enetsw *priv, int chan)
 640 {
 641         int limit = 1000;
 642
 643         dmac_writel(priv, 0, DMAC_CHANCFG_REG, chan);
 644
 645         do {
 646                 u32 val;
 647
 648                 val = dma_readl(priv, DMAC_CHANCFG_REG, chan);
 649                 if (!(val & DMAC_CHANCFG_EN_MASK))
 650                         break;
 651
 652                 udelay(1);
 653         } while (limit--);
 654 }
 655
 656 static int bcm6368_enetsw_open(struct net_device *dev)
 657 {
 658         struct bcm6368_enetsw *priv = netdev_priv(dev);
 659         struct device *kdev = &priv->pdev->dev;
 660         int i, ret;
 661         unsigned int size;
 662         void *p;
 663         u32 val;
 664
 665         /* mask all interrupts and request them */
 666         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 667         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 668
 669         ret = request_irq(priv->irq_rx, bcm6368_enetsw_isr_dma,
 670                           0, dev->name, dev);
 671         if (ret)
 672                 goto out_freeirq;
 673
 674         if (priv->irq_tx != -1) {
 675                 ret = request_irq(priv->irq_tx, bcm6368_enetsw_isr_dma,
 676                                   0, dev->name, dev);
 677                 if (ret)
 678                         goto out_freeirq_rx;
 679         }
 680
 681         /* allocate rx dma ring */
 682         size = priv->rx_ring_size * sizeof(struct bcm6368_enetsw_desc);
 683         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 684         if (!p) {
 685                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
 686                 ret = -ENOMEM;
 687                 goto out_freeirq_tx;
 688         }
 689
 690         memset(p, 0, size);
 691         priv->rx_desc_alloc_size = size;
 692         priv->rx_desc_cpu = p;
 693
 694         /* allocate tx dma ring */
 695         size = priv->tx_ring_size * sizeof(struct bcm6368_enetsw_desc);
 696         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 697         if (!p) {
 698                 dev_err(kdev, "cannot allocate tx ring\n");
 699                 ret = -ENOMEM;
 700                 goto out_free_rx_ring;
 701         }
 702
 703         memset(p, 0, size);
 704         priv->tx_desc_alloc_size = size;
 705         priv->tx_desc_cpu = p;
 706
 707         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
 708                                GFP_KERNEL);
 709         if (!priv->tx_skb) {
 710                 dev_err(kdev, "cannot allocate tx skb queue\n");
 711                 ret = -ENOMEM;
 712                 goto out_free_tx_ring;
 713         }
 714
 715         priv->tx_desc_count = priv->tx_ring_size;
 716         priv->tx_dirty_desc = 0;
 717         priv->tx_curr_desc = 0;
 718         spin_lock_init(&priv->tx_lock);
 719
 720         /* init & fill rx ring with buffers */
 721         priv->rx_buf = kzalloc(sizeof(unsigned char *) * priv->rx_ring_size,
 722                                GFP_KERNEL);
 723         if (!priv->rx_buf) {
 724                 dev_err(kdev, "cannot allocate rx buffer queue\n");
 725                 ret = -ENOMEM;
 726                 goto out_free_tx_skb;
 727         }
 728
 729         priv->rx_desc_count = 0;
 730         priv->rx_dirty_desc = 0;
 731         priv->rx_curr_desc = 0;
 732
 733         /* initialize flow control buffer allocation */
 734         dma_writel(priv, DMA_BUFALLOC_FORCE_MASK | 0,
 735                    DMA_BUFALLOC_REG(priv->rx_chan));
 736
 737         if (bcm6368_enetsw_refill_rx(dev, false)) {
 738                 dev_err(kdev, "cannot allocate rx buffer queue\n");
 739                 ret = -ENOMEM;
 740                 goto out;
 741         }
 742
 743         /* write rx & tx ring addresses */
 744         dmas_writel(priv, priv->rx_desc_dma,
 745                     DMAS_RSTART_REG, priv->rx_chan);
 746         dmas_writel(priv, priv->tx_desc_dma,
 747                     DMAS_RSTART_REG, priv->tx_chan);
 748
 749         /* clear remaining state ram for rx & tx channel */
 750         dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->rx_chan);
 751         dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->tx_chan);
 752         dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->rx_chan);
 753         dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->tx_chan);
 754         dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->rx_chan);
 755         dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->tx_chan);
 756
 757         /* set dma maximum burst len */
 758         dmac_writel(priv, priv->dma_maxburst,
 759                     DMAC_MAXBURST_REG, priv->rx_chan);
 760         dmac_writel(priv, priv->dma_maxburst,
 761                     DMAC_MAXBURST_REG, priv->tx_chan);
 762
 763         /* set flow control low/high threshold to 1/3 / 2/3 */
 764         val = priv->rx_ring_size / 3;
 765         dma_writel(priv, val, DMA_FLOWCL_REG(priv->rx_chan));
 766         val = (priv->rx_ring_size * 2) / 3;
 767         dma_writel(priv, val, DMA_FLOWCH_REG(priv->rx_chan));
 768
 769         /* all set, enable mac and interrupts, start dma engine and
 770          * kick rx dma channel
 771          */
 772         wmb();
 773         dma_writel(priv, DMA_CFG_EN_MASK, DMA_CFG_REG);
 774         dmac_writel(priv, DMAC_CHANCFG_EN_MASK,
 775                     DMAC_CHANCFG_REG, priv->rx_chan);
 776
 777         /* watch "packet transferred" interrupt in rx and tx */
 778         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 779                     DMAC_IR_REG, priv->rx_chan);
 780         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 781                     DMAC_IR_REG, priv->tx_chan);
 782
 783         /* make sure we enable napi before rx interrupt  */
 784         napi_enable(&priv->napi);
 785
 786         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 787                     DMAC_IRMASK_REG, priv->rx_chan);
 788         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 789                     DMAC_IRMASK_REG, priv->tx_chan);
 790
 791         netif_carrier_on(dev);
 792         netif_start_queue(dev);
 793
 794         return 0;
 795
 796 out:
 797         for (i = 0; i < priv->rx_ring_size; i++) {
 798                 struct bcm6368_enetsw_desc *desc;
 799
 800                 if (!priv->rx_buf[i])
 801                         continue;
 802
 803                 desc = &priv->rx_desc_cpu[i];
 804                 dma_unmap_single(kdev, desc->address, priv->rx_buf_size,
 805                                  DMA_FROM_DEVICE);
 806                 skb_free_frag(priv->rx_buf[i]);
 807         }
 808         kfree(priv->rx_buf);
 809
 810 out_free_tx_skb:
 811         kfree(priv->tx_skb);
 812
 813 out_free_tx_ring:
 814         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
 815                           priv->tx_desc_cpu, priv->tx_desc_dma);
 816
 817 out_free_rx_ring:
 818         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
 819                           priv->rx_desc_cpu, priv->rx_desc_dma);
 820
 821 out_freeirq_tx:
 822         if (priv->irq_tx != -1)
 823                 free_irq(priv->irq_tx, dev);
 824
 825 out_freeirq_rx:
 826         free_irq(priv->irq_rx, dev);
 827
 828 out_freeirq:
 829         return ret;
 830 }
 831
 832 static int bcm6368_enetsw_stop(struct net_device *dev)
 833 {
 834         struct bcm6368_enetsw *priv = netdev_priv(dev);
 835         struct device *kdev = &priv->pdev->dev;
 836         int i;
 837
 838         netif_stop_queue(dev);
 839         napi_disable(&priv->napi);
 840         del_timer_sync(&priv->rx_timeout);
 841
 842         /* mask all interrupts */
 843         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 844         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 845
 846         /* disable dma & mac */
 847         bcm6368_enetsw_disable_dma(priv, priv->tx_chan);
 848         bcm6368_enetsw_disable_dma(priv, priv->rx_chan);
 849
 850         /* force reclaim of all tx buffers */
 851         bcm6368_enetsw_tx_reclaim(dev, 1);
 852
 853         /* free the rx buffer ring */
 854         for (i = 0; i < priv->rx_ring_size; i++) {
 855                 struct bcm6368_enetsw_desc *desc;
 856
 857                 if (!priv->rx_buf[i])
 858                         continue;
 859
 860                 desc = &priv->rx_desc_cpu[i];
 861                 dma_unmap_single_attrs(kdev, desc->address, priv->rx_buf_size,
 862                                        DMA_FROM_DEVICE,
 863                                        DMA_ATTR_SKIP_CPU_SYNC);
 864                 skb_free_frag(priv->rx_buf[i]);
 865         }
 866
 867         /* free remaining allocated memory */
 868         kfree(priv->rx_buf);
 869         kfree(priv->tx_skb);
 870         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
 871                           priv->rx_desc_cpu, priv->rx_desc_dma);
 872         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
 873                           priv->tx_desc_cpu, priv->tx_desc_dma);
 874         if (priv->irq_tx != -1)
 875                 free_irq(priv->irq_tx, dev);
 876         free_irq(priv->irq_rx, dev);
 877
 878         return 0;
 879 }
 880
 881 static const struct net_device_ops bcm6368_enetsw_ops = {
 882         .ndo_open = bcm6368_enetsw_open,
 883         .ndo_stop = bcm6368_enetsw_stop,
 884         .ndo_start_xmit = bcm6368_enetsw_start_xmit,
 885 };
 886
 887 static int bcm6368_enetsw_probe(struct platform_device *pdev)
 888 {
 889         struct bcm6368_enetsw *priv;
 890         struct device *dev = &pdev->dev;
 891         struct device_node *node = dev->of_node;
 892         struct net_device *ndev;
 893         struct resource *res;
 894         unsigned i;
 895         int ret;
 896
 897         ndev = alloc_etherdev(sizeof(*priv));
 898         if (!ndev)
 899                 return -ENOMEM;
 900
 901         priv = netdev_priv(ndev);
 902
 903         priv->num_pms = of_count_phandle_with_args(node, "power-domains",
 904                                                    "#power-domain-cells");
 905         if (priv->num_pms > 1) {
 906                 priv->pm = devm_kcalloc(dev, priv->num_pms,
 907                                         sizeof(struct device *), GFP_KERNEL);
 908                 if (!priv->pm)
 909                         return -ENOMEM;
 910
 911                 priv->link_pm = devm_kcalloc(dev, priv->num_pms,
 912                                              sizeof(struct device_link *),
 913                                              GFP_KERNEL);
 914                 if (!priv->link_pm)
 915                         return -ENOMEM;
 916
 917                 for (i = 0; i < priv->num_pms; i++) {
 918                         priv->pm[i] = genpd_dev_pm_attach_by_id(dev, i);
 919                         if (IS_ERR(priv->pm[i])) {
 920                                 dev_err(dev, "error getting pm %d\n", i);
 921                                 return -EINVAL;
 922                         }
 923
 924                         priv->link_pm[i] = device_link_add(dev, priv->pm[i],
 925                                 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
 926                                 DL_FLAG_RPM_ACTIVE);
 927                 }
 928         }
 929
 930         pm_runtime_enable(dev);
 931         pm_runtime_no_callbacks(dev);
 932         ret = pm_runtime_get_sync(dev);
 933         if (ret < 0) {
 934                 pm_runtime_disable(dev);
 935                 dev_info(dev, "PM prober defer: ret=%d\n", ret);
 936                 return -EPROBE_DEFER;
 937         }
 938
 939         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 940         priv->dma_base = devm_ioremap_resource(dev, res);
 941         if (IS_ERR(priv->dma_base))
 942                 return PTR_ERR(priv->dma_base);
 943
 944         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 945                                            "dma-channels");
 946         priv->dma_chan = devm_ioremap_resource(dev, res);
 947         if (IS_ERR(priv->dma_chan))
 948                 return PTR_ERR(priv->dma_chan);
 949
 950         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma-sram");
 951         priv->dma_sram = devm_ioremap_resource(dev, res);
 952         if (IS_ERR(priv->dma_sram))
 953                 return PTR_ERR(priv->dma_sram);
 954
 955         priv->irq_rx = platform_get_irq_byname(pdev, "rx");
 956         if (!priv->irq_rx)
 957                 return -ENODEV;
 958
 959         priv->irq_tx = platform_get_irq_byname(pdev, "tx");
 960         if (!priv->irq_tx)
 961                 return -ENODEV;
 962         else if (priv->irq_tx < 0)
 963                 priv->irq_tx = -1;
 964
 965         if (device_property_read_u32(dev, "dma-rx", &priv->rx_chan))
 966                 return -ENODEV;
 967
 968         if (device_property_read_u32(dev, "dma-tx", &priv->tx_chan))
 969                 return -ENODEV;
 970
 971         priv->rx_ring_size = ENETSW_DEF_RX_DESC;
 972         priv->tx_ring_size = ENETSW_DEF_TX_DESC;
 973
 974         priv->dma_maxburst = ENETSW_DMA_MAXBURST;
 975
 976         priv->copybreak = ENETSW_DEF_CPY_BREAK;
 977
 978         priv->dma_chan_en_mask = DMAC_CHANCFG_EN_MASK;
 979         priv->dma_chan_int_mask = DMAC_IR_PKTDONE_MASK;
 980         priv->dma_chan_width = DMA_CHAN_WIDTH;
 981
 982         of_get_mac_address(node, ndev->dev_addr);
 983         if (is_valid_ether_addr(ndev->dev_addr)) {
 984                 dev_info(dev, "mtd mac %pM\n", ndev->dev_addr);
 985         } else {
 986                 random_ether_addr(ndev->dev_addr);
 987                 dev_info(dev, "random mac %pM\n", ndev->dev_addr);
 988         }
 989
 990         priv->rx_buf_size = ALIGN(ndev->mtu + ENETSW_MTU_OVERHEAD,
 991                                   priv->dma_maxburst * 4);
 992
 993         priv->rx_frag_size = ENETSW_FRAG_SIZE(priv->rx_buf_size);
 994
 995         priv->num_clocks = of_clk_get_parent_count(node);
 996         if (priv->num_clocks) {
 997                 priv->clock = devm_kcalloc(dev, priv->num_clocks,
 998                                            sizeof(struct clk *), GFP_KERNEL);
 999                 if (!priv->clock)
1000                         return -ENOMEM;
1001         }
1002         for (i = 0; i < priv->num_clocks; i++) {
1003                 priv->clock[i] = of_clk_get(node, i);
1004                 if (IS_ERR(priv->clock[i])) {
1005                         dev_err(dev, "error getting clock %d\n", i);
1006                         return -EINVAL;
1007                 }
1008
1009                 ret = clk_prepare_enable(priv->clock[i]);
1010                 if (ret) {
1011                         dev_err(dev, "error enabling clock %d\n", i);
1012                         return ret;
1013                 }
1014         }
1015
1016         priv->num_resets = of_count_phandle_with_args(node, "resets",
1017                                                       "#reset-cells");
1018         if (priv->num_resets) {
1019                 priv->reset = devm_kcalloc(dev, priv->num_resets,
1020                                            sizeof(struct reset_control *),
1021                                            GFP_KERNEL);
1022                 if (!priv->reset)
1023                         return -ENOMEM;
1024         }
1025         for (i = 0; i < priv->num_resets; i++) {
1026                 priv->reset[i] = devm_reset_control_get_by_index(dev, i);
1027                 if (IS_ERR(priv->reset[i])) {
1028                         dev_err(dev, "error getting reset %d\n", i);
1029                         return -EINVAL;
1030                 }
1031
1032                 ret = reset_control_reset(priv->reset[i]);
1033                 if (ret) {
1034                         dev_err(dev, "error performing reset %d\n", i);
1035                         return ret;
1036                 }
1037         }
1038
1039         spin_lock_init(&priv->rx_lock);
1040
1041         timer_setup(&priv->rx_timeout, bcm6368_enetsw_refill_rx_timer, 0);
1042
1043         /* register netdevice */
1044         ndev->netdev_ops = &bcm6368_enetsw_ops;
1045         ndev->min_mtu = ETH_ZLEN;
1046         ndev->mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1047         ndev->max_mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1048         netif_napi_add(ndev, &priv->napi, bcm6368_enetsw_poll, 16);
1049         SET_NETDEV_DEV(ndev, dev);
1050
1051         ret = register_netdev(ndev);
1052         if (ret)
1053                 goto out_disable_clk;
1054
1055         netif_carrier_off(ndev);
1056         platform_set_drvdata(pdev, ndev);
1057         priv->pdev = pdev;
1058         priv->net_dev = ndev;
1059
1060         return 0;
1061
1062 out_disable_clk:
1063         for (i = 0; i < priv->num_resets; i++)
1064                 reset_control_assert(priv->reset[i]);
1065
1066         for (i = 0; i < priv->num_clocks; i++)
1067                 clk_disable_unprepare(priv->clock[i]);
1068
1069         return ret;
1070 }
1071
1072 static int bcm6368_enetsw_remove(struct platform_device *pdev)
1073 {
1074         struct device *dev = &pdev->dev;
1075         struct net_device *ndev = platform_get_drvdata(pdev);
1076         struct bcm6368_enetsw *priv = netdev_priv(ndev);
1077         unsigned int i;
1078
1079         unregister_netdev(ndev);
1080
1081         pm_runtime_put_sync(dev);
1082         for (i = 0; priv->pm && i < priv->num_pms; i++) {
1083                 dev_pm_domain_detach(priv->pm[i], true);
1084                 device_link_del(priv->link_pm[i]);
1085         }
1086
1087         for (i = 0; i < priv->num_resets; i++)
1088                 reset_control_assert(priv->reset[i]);
1089
1090         for (i = 0; i < priv->num_clocks; i++)
1091                 clk_disable_unprepare(priv->clock[i]);
1092
1093         free_netdev(ndev);
1094
1095         return 0;
1096 }
1097
1098 static const struct of_device_id bcm6368_enetsw_of_match[] = {
1099         { .compatible = "brcm,bcm6318-enetsw", },
1100         { .compatible = "brcm,bcm6328-enetsw", },
1101         { .compatible = "brcm,bcm6362-enetsw", },
1102         { .compatible = "brcm,bcm6368-enetsw", },
1103         { .compatible = "brcm,bcm63268-enetsw", },
1104         { /* sentinel */ }
1105 };
1106 MODULE_DEVICE_TABLE(of, bcm6368_enetsw_of_match);
1107
1108 static struct platform_driver bcm6368_enetsw_driver = {
1109         .driver = {
1110                 .name = "bcm6368-enetsw",
1111                 .of_match_table = of_match_ptr(bcm6368_enetsw_of_match),
1112         },
1113         .probe  = bcm6368_enetsw_probe,
1114         .remove = bcm6368_enetsw_remove,
1115 };
1116 module_platform_driver(bcm6368_enetsw_driver);