target/linux/bmips/files/drivers/pci/controller/pci-bcm6348.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * BCM6348 PCI Controller Driver
   4  *
   5  * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
   6  * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
   7  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/kernel.h>
  14 #include <linux/memblock.h>
  15 #include <linux/mm.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_pci.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/pci.h>
  22 #include <linux/reset.h>
  23 #include <linux/types.h>
  24 #include <linux/vmalloc.h>
  25
  26 #include "../pci.h"
  27
  28 #define CARDBUS_DUMMY_ID                0x6348
  29 #define CARDBUS_PCI_IDSEL               0x8
  30 #define FAKE_CB_BRIDGE_SLOT             0x1e
  31
  32 #define BCMPCI_REG_TIMERS               0x40
  33 #define REG_TIMER_TRDY_SHIFT            0
  34 #define REG_TIMER_TRDY_MASK             (0xff << REG_TIMER_TRDY_SHIFT)
  35 #define REG_TIMER_RETRY_SHIFT           8
  36 #define REG_TIMER_RETRY_MASK            (0xff << REG_TIMER_RETRY_SHIFT)
  37
  38 #define MPI_SP0_RANGE_REG               0x100
  39 #define MPI_SP0_REMAP_REG               0x104
  40 #define MPI_SP0_REMAP_ENABLE_MASK       (1 << 0)
  41 #define MPI_SP1_RANGE_REG               0x10C
  42 #define MPI_SP1_REMAP_REG               0x110
  43 #define MPI_SP1_REMAP_ENABLE_MASK       (1 << 0)
  44
  45 #define MPI_L2PCFG_REG                  0x11c
  46 #define MPI_L2PCFG_CFG_TYPE_SHIFT       0
  47 #define MPI_L2PCFG_CFG_TYPE_MASK        (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
  48 #define MPI_L2PCFG_REG_SHIFT            2
  49 #define MPI_L2PCFG_REG_MASK             (0x3f << MPI_L2PCFG_REG_SHIFT)
  50 #define MPI_L2PCFG_FUNC_SHIFT           8
  51 #define MPI_L2PCFG_FUNC_MASK            (0x7 << MPI_L2PCFG_FUNC_SHIFT)
  52 #define MPI_L2PCFG_DEVNUM_SHIFT         11
  53 #define MPI_L2PCFG_DEVNUM_MASK          (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
  54 #define MPI_L2PCFG_CFG_USEREG_MASK      (1 << 30)
  55 #define MPI_L2PCFG_CFG_SEL_MASK         (1 << 31)
  56
  57 #define MPI_L2PMEMRANGE1_REG            0x120
  58 #define MPI_L2PMEMBASE1_REG             0x124
  59 #define MPI_L2PMEMREMAP1_REG            0x128
  60 #define MPI_L2PMEMRANGE2_REG            0x12C
  61 #define MPI_L2PMEMBASE2_REG             0x130
  62 #define MPI_L2PMEMREMAP2_REG            0x134
  63 #define MPI_L2PIORANGE_REG              0x138
  64 #define MPI_L2PIOBASE_REG               0x13C
  65 #define MPI_L2PIOREMAP_REG              0x140
  66 #define MPI_L2P_BASE_MASK               (0xffff8000)
  67 #define MPI_L2PREMAP_ENABLED_MASK       (1 << 0)
  68 #define MPI_L2PREMAP_IS_CARDBUS_MASK    (1 << 2)
  69
  70 #define MPI_PCIMODESEL_REG              0x144
  71 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
  72 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
  73 #define MPI_PCIMODESEL_EXT_ARB_MASK     (1 << 2)
  74 #define MPI_PCIMODESEL_PREFETCH_SHIFT   4
  75 #define MPI_PCIMODESEL_PREFETCH_MASK    (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
  76
  77 #define MPI_LOCBUSCTL_REG               0x14c
  78 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK  (1 << 0)
  79 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK   (1 << 1)
  80
  81 #define MPI_LOCINT_REG                  0x150
  82 #define MPI_LOCINT_MASK(x)              (1 << (x + 16))
  83 #define MPI_LOCINT_STAT(x)              (1 << (x))
  84 #define MPI_LOCINT_DIR_FAILED           6
  85 #define MPI_LOCINT_EXT_PCI_INT          7
  86 #define MPI_LOCINT_SERR                 8
  87 #define MPI_LOCINT_CSERR                9
  88
  89 #define MPI_PCICFGCTL_REG               0x178
  90 #define MPI_PCICFGCTL_CFGADDR_SHIFT     2
  91 #define MPI_PCICFGCTL_CFGADDR_MASK      (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
  92 #define MPI_PCICFGCTL_WRITEEN_MASK      (1 << 7)
  93
  94 #define MPI_PCICFGDATA_REG              0x17c
  95
  96 #define PCMCIA_OFFSET                   0x54
  97
  98 #define PCMCIA_C1_REG                   0x0
  99 #define PCMCIA_C1_CD1_MASK              (1 << 0)
 100 #define PCMCIA_C1_CD2_MASK              (1 << 1)
 101 #define PCMCIA_C1_VS1_MASK              (1 << 2)
 102 #define PCMCIA_C1_VS2_MASK              (1 << 3)
 103 #define PCMCIA_C1_VS1OE_MASK            (1 << 6)
 104 #define PCMCIA_C1_VS2OE_MASK            (1 << 7)
 105 #define PCMCIA_C1_CBIDSEL_SHIFT         (8)
 106 #define PCMCIA_C1_CBIDSEL_MASK          (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
 107 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK   (1 << 13)
 108 #define PCMCIA_C1_EN_PCMCIA_MASK        (1 << 14)
 109 #define PCMCIA_C1_EN_CARDBUS_MASK       (1 << 15)
 110 #define PCMCIA_C1_RESET_MASK            (1 << 18)
 111
 112 #ifdef CONFIG_CARDBUS
 113 struct bcm6348_cb {
 114         u16 pci_command;
 115         u8 cb_latency;
 116         u8 subordinate_busn;
 117         u8 cardbus_busn;
 118         u8 pci_busn;
 119         int bus_assigned;
 120         u16 bridge_control;
 121
 122         u32 mem_base0;
 123         u32 mem_limit0;
 124         u32 mem_base1;
 125         u32 mem_limit1;
 126
 127         u32 io_base0;
 128         u32 io_limit0;
 129         u32 io_base1;
 130         u32 io_limit1;
 131 };
 132 #endif /* CONFIG_CARDBUS */
 133
 134 struct bcm6348_pci {
 135         void __iomem *pci;
 136         void __iomem *pcmcia;
 137         void __iomem *io;
 138         int irq;
 139         struct reset_control *reset;
 140         bool remap;
 141 #ifdef CONFIG_CARDBUS
 142         struct bcm6348_cb cb;
 143         int cb_bus;
 144 #endif /* CONFIG_CARDBUS */
 145 };
 146
 147 static struct bcm6348_pci bcm6348_pci;
 148
 149 extern int bmips_pci_irq;
 150
 151 static u32 bcm6348_int_cfg_readl(u32 reg)
 152 {
 153         struct bcm6348_pci *priv = &bcm6348_pci;
 154         u32 tmp;
 155
 156         tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
 157         tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
 158         __raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
 159         iob();
 160         return __raw_readl(priv->pci + MPI_PCICFGDATA_REG);
 161 }
 162
 163 static void bcm6348_int_cfg_writel(u32 val, u32 reg)
 164 {
 165         struct bcm6348_pci *priv = &bcm6348_pci;
 166         u32 tmp;
 167
 168         tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
 169         tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
 170         __raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
 171         __raw_writel(val, priv->pci + MPI_PCICFGDATA_REG);
 172 }
 173
 174 /*
 175  * swizzle 32bits data to return only the needed part
 176  */
 177 static int postprocess_read(u32 data, int where, unsigned int size)
 178 {
 179         u32 ret = 0;
 180
 181         switch (size) {
 182         case 1:
 183                 ret = (data >> ((where & 3) << 3)) & 0xff;
 184                 break;
 185         case 2:
 186                 ret = (data >> ((where & 3) << 3)) & 0xffff;
 187                 break;
 188         case 4:
 189                 ret = data;
 190                 break;
 191         }
 192
 193         return ret;
 194 }
 195
 196 static int preprocess_write(u32 orig_data, u32 val, int where,
 197                             unsigned int size)
 198 {
 199         u32 ret = 0;
 200
 201         switch (size) {
 202         case 1:
 203                 ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
 204                         (val << ((where & 3) << 3));
 205                 break;
 206         case 2:
 207                 ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
 208                         (val << ((where & 3) << 3));
 209                 break;
 210         case 4:
 211                 ret = val;
 212                 break;
 213         }
 214
 215         return ret;
 216 }
 217
 218 static int bcm6348_setup_cfg_access(int type, unsigned int busn,
 219                                     unsigned int devfn, int where)
 220 {
 221         struct bcm6348_pci *priv = &bcm6348_pci;
 222         unsigned int slot, func, reg;
 223         u32 val;
 224
 225         slot = PCI_SLOT(devfn);
 226         func = PCI_FUNC(devfn);
 227         reg = where >> 2;
 228
 229         /* sanity check */
 230         if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
 231                 return 1;
 232
 233         if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
 234                 return 1;
 235
 236         if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
 237                 return 1;
 238
 239         /* ok, setup config access */
 240         val = (reg << MPI_L2PCFG_REG_SHIFT);
 241         val |= (func << MPI_L2PCFG_FUNC_SHIFT);
 242         val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
 243         val |= MPI_L2PCFG_CFG_USEREG_MASK;
 244         val |= MPI_L2PCFG_CFG_SEL_MASK;
 245         /* type 0 cycle for local bus, type 1 cycle for anything else */
 246         if (type != 0) {
 247                 /* FIXME: how to specify bus ??? */
 248                 val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
 249         }
 250         __raw_writel(val, priv->pci + MPI_L2PCFG_REG);
 251
 252         return 0;
 253 }
 254
 255
 256 static int bcm6348_do_cfg_read(int type, unsigned int busn,
 257                                unsigned int devfn, int where, int size,
 258                                u32 *val)
 259 {
 260         struct bcm6348_pci *priv = &bcm6348_pci;
 261         u32 data;
 262
 263         /* two phase cycle, first we write address, then read data at
 264          * another location, caller already has a spinlock so no need
 265          * to add one here */
 266         if (bcm6348_setup_cfg_access(type, busn, devfn, where))
 267                 return PCIBIOS_DEVICE_NOT_FOUND;
 268         iob();
 269         data = le32_to_cpu(__raw_readl(priv->io));
 270         /* restore IO space normal behaviour */
 271         __raw_writel(0, priv->pci + MPI_L2PCFG_REG);
 272
 273         *val = postprocess_read(data, where, size);
 274
 275         return PCIBIOS_SUCCESSFUL;
 276 }
 277
 278 static int bcm6348_do_cfg_write(int type, unsigned int busn,
 279                                 unsigned int devfn, int where, int size,
 280                                 u32 val)
 281 {
 282         struct bcm6348_pci *priv = &bcm6348_pci;
 283         u32 data;
 284
 285         /* two phase cycle, first we write address, then write data to
 286          * another location, caller already has a spinlock so no need
 287          * to add one here */
 288         if (bcm6348_setup_cfg_access(type, busn, devfn, where))
 289                 return PCIBIOS_DEVICE_NOT_FOUND;
 290         iob();
 291
 292         data = le32_to_cpu(__raw_readl(priv->io));
 293         data = preprocess_write(data, val, where, size);
 294
 295         __raw_writel(cpu_to_le32(data), priv->io);
 296         wmb();
 297         /* no way to know the access is done, we have to wait */
 298         udelay(500);
 299         /* restore IO space normal behaviour */
 300         __raw_writel(0, priv->pci + MPI_L2PCFG_REG);
 301
 302         return PCIBIOS_SUCCESSFUL;
 303 }
 304
 305 static int bcm6348_pci_read(struct pci_bus *bus, unsigned int devfn,
 306                              int where, int size, u32 *val)
 307 {
 308         int type;
 309
 310         type = bus->parent ? 1 : 0;
 311
 312         if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
 313                 return PCIBIOS_DEVICE_NOT_FOUND;
 314
 315         return bcm6348_do_cfg_read(type, bus->number, devfn,
 316                                    where, size, val);
 317 }
 318
 319 static int bcm6348_pci_write(struct pci_bus *bus, unsigned int devfn,
 320                               int where, int size, u32 val)
 321 {
 322         int type;
 323
 324         type = bus->parent ? 1 : 0;
 325
 326         if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
 327                 return PCIBIOS_DEVICE_NOT_FOUND;
 328
 329         return bcm6348_do_cfg_write(type, bus->number, devfn,
 330                                     where, size, val);
 331 }
 332
 333 static struct pci_ops bcm6348_pci_ops = {
 334         .read = bcm6348_pci_read,
 335         .write = bcm6348_pci_write,
 336 };
 337
 338 static struct resource bcm6348_pci_io_resource;
 339 static struct resource bcm6348_pci_mem_resource;
 340 static struct resource bcm6348_pci_busn_resource;
 341
 342 static struct pci_controller bcm6348_pci_controller = {
 343         .pci_ops = &bcm6348_pci_ops,
 344         .io_resource = &bcm6348_pci_io_resource,
 345         .mem_resource = &bcm6348_pci_mem_resource,
 346 };
 347
 348 #ifdef CONFIG_CARDBUS
 349 static int bcm6348_cb_bridge_read(int where, int size, u32 *val)
 350 {
 351         struct bcm6348_cb *cb = &bcm6348_pci.cb;
 352         unsigned int reg;
 353         u32 data;
 354
 355         data = 0;
 356         reg = where >> 2;
 357         switch (reg) {
 358         case (PCI_VENDOR_ID >> 2):
 359         case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
 360                 /* create dummy vendor/device id from our cpu id */
 361                 data = (CARDBUS_DUMMY_ID << 16) | PCI_VENDOR_ID_BROADCOM;
 362                 break;
 363
 364         case (PCI_COMMAND >> 2):
 365                 data = (PCI_STATUS_DEVSEL_SLOW << 16);
 366                 data |= cb->pci_command;
 367                 break;
 368
 369         case (PCI_CLASS_REVISION >> 2):
 370                 data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
 371                 break;
 372
 373         case (PCI_CACHE_LINE_SIZE >> 2):
 374                 data = (PCI_HEADER_TYPE_CARDBUS << 16);
 375                 break;
 376
 377         case (PCI_INTERRUPT_LINE >> 2):
 378                 /* bridge control */
 379                 data = (cb->bridge_control << 16);
 380                 /* pin:intA line:0xff */
 381                 data |= (0x1 << 8) | 0xff;
 382                 break;
 383
 384         case (PCI_CB_PRIMARY_BUS >> 2):
 385                 data = (cb->cb_latency << 24);
 386                 data |= (cb->subordinate_busn << 16);
 387                 data |= (cb->cardbus_busn << 8);
 388                 data |= cb->pci_busn;
 389                 break;
 390
 391         case (PCI_CB_MEMORY_BASE_0 >> 2):
 392                 data = cb->mem_base0;
 393                 break;
 394
 395         case (PCI_CB_MEMORY_LIMIT_0 >> 2):
 396                 data = cb->mem_limit0;
 397                 break;
 398
 399         case (PCI_CB_MEMORY_BASE_1 >> 2):
 400                 data = cb->mem_base1;
 401                 break;
 402
 403         case (PCI_CB_MEMORY_LIMIT_1 >> 2):
 404                 data = cb->mem_limit1;
 405                 break;
 406
 407         case (PCI_CB_IO_BASE_0 >> 2):
 408                 /* | 1 for 32bits io support */
 409                 data = cb->io_base0 | 0x1;
 410                 break;
 411
 412         case (PCI_CB_IO_LIMIT_0 >> 2):
 413                 data = cb->io_limit0;
 414                 break;
 415
 416         case (PCI_CB_IO_BASE_1 >> 2):
 417                 /* | 1 for 32bits io support */
 418                 data = cb->io_base1 | 0x1;
 419                 break;
 420
 421         case (PCI_CB_IO_LIMIT_1 >> 2):
 422                 data = cb->io_limit1;
 423                 break;
 424         }
 425
 426         *val = postprocess_read(data, where, size);
 427         return PCIBIOS_SUCCESSFUL;
 428 }
 429
 430 /*
 431  * emulate configuration write access on a cardbus bridge
 432  */
 433 static int bcm6348_cb_bridge_write(int where, int size, u32 val)
 434 {
 435         struct bcm6348_cb *cb = &bcm6348_pci.cb;
 436         unsigned int reg;
 437         u32 data, tmp;
 438         int ret;
 439
 440         ret = bcm6348_cb_bridge_read((where & ~0x3), 4, &data);
 441         if (ret != PCIBIOS_SUCCESSFUL)
 442                 return ret;
 443
 444         data = preprocess_write(data, val, where, size);
 445
 446         reg = where >> 2;
 447         switch (reg) {
 448         case (PCI_COMMAND >> 2):
 449                 cb->pci_command = (data & 0xffff);
 450                 break;
 451
 452         case (PCI_CB_PRIMARY_BUS >> 2):
 453                 cb->cb_latency = (data >> 24) & 0xff;
 454                 cb->subordinate_busn = (data >> 16) & 0xff;
 455                 cb->cardbus_busn = (data >> 8) & 0xff;
 456                 cb->pci_busn = data & 0xff;
 457                 if (cb->cardbus_busn)
 458                         cb->bus_assigned = 1;
 459                 break;
 460
 461         case (PCI_INTERRUPT_LINE >> 2):
 462                 tmp = (data >> 16) & 0xffff;
 463                 /* Disable memory prefetch support */
 464                 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
 465                 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
 466                 cb->bridge_control = tmp;
 467                 break;
 468
 469         case (PCI_CB_MEMORY_BASE_0 >> 2):
 470                 cb->mem_base0 = data;
 471                 break;
 472
 473         case (PCI_CB_MEMORY_LIMIT_0 >> 2):
 474                 cb->mem_limit0 = data;
 475                 break;
 476
 477         case (PCI_CB_MEMORY_BASE_1 >> 2):
 478                 cb->mem_base1 = data;
 479                 break;
 480
 481         case (PCI_CB_MEMORY_LIMIT_1 >> 2):
 482                 cb->mem_limit1 = data;
 483                 break;
 484
 485         case (PCI_CB_IO_BASE_0 >> 2):
 486                 cb->io_base0 = data;
 487                 break;
 488
 489         case (PCI_CB_IO_LIMIT_0 >> 2):
 490                 cb->io_limit0 = data;
 491                 break;
 492
 493         case (PCI_CB_IO_BASE_1 >> 2):
 494                 cb->io_base1 = data;
 495                 break;
 496
 497         case (PCI_CB_IO_LIMIT_1 >> 2):
 498                 cb->io_limit1 = data;
 499                 break;
 500         }
 501
 502         return PCIBIOS_SUCCESSFUL;
 503 }
 504
 505 static int bcm6348_cb_read(struct pci_bus *bus, unsigned int devfn,
 506                            int where, int size, u32 *val)
 507 {
 508         struct bcm6348_pci *priv = &bcm6348_pci;
 509         struct bcm6348_cb *cb = &priv->cb;
 510
 511         /* Snoop access to slot 0x1e on root bus, we fake a cardbus
 512          * bridge at this location */
 513         if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
 514                 priv->cb_bus = bus->number;
 515                 return bcm6348_cb_bridge_read(where, size, val);
 516         }
 517
 518         /* A configuration cycle for the device behind the cardbus
 519          * bridge is actually done as a type 0 cycle on the primary
 520          * bus. This means that only one device can be on the cardbus
 521          * bus */
 522         if (cb->bus_assigned &&
 523             bus->number == cb->cardbus_busn &&
 524             PCI_SLOT(devfn) == 0)
 525                 return bcm6348_do_cfg_read(0, 0,
 526                                            PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
 527                                            where, size, val);
 528
 529         return PCIBIOS_DEVICE_NOT_FOUND;
 530 }
 531
 532 static int bcm6348_cb_write(struct pci_bus *bus, unsigned int devfn,
 533                             int where, int size, u32 val)
 534 {
 535         struct bcm6348_pci *priv = &bcm6348_pci;
 536         struct bcm6348_cb *cb = &priv->cb;
 537
 538         if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
 539                 priv->cb_bus = bus->number;
 540                 return bcm6348_cb_bridge_write(where, size, val);
 541         }
 542
 543         if (cb->bus_assigned &&
 544             bus->number == cb->cardbus_busn &&
 545             PCI_SLOT(devfn) == 0)
 546                 return bcm6348_do_cfg_write(0, 0,
 547                                             PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
 548                                             where, size, val);
 549
 550         return PCIBIOS_DEVICE_NOT_FOUND;
 551 }
 552
 553 static struct pci_ops bcm6348_cb_ops = {
 554         .read = bcm6348_cb_read,
 555         .write = bcm6348_cb_write,
 556 };
 557
 558 /*
 559  * only one IO window, so it  cannot be shared by PCI and cardbus, use
 560  * fixup to choose and detect unhandled configuration
 561  */
 562 static void bcm6348_pci_fixup(struct pci_dev *dev)
 563 {
 564         struct bcm6348_pci *priv = &bcm6348_pci;
 565         struct bcm6348_cb *cb = &priv->cb;
 566         static int io_window = -1;
 567         int i, found, new_io_window;
 568         u32 val;
 569
 570         /* look for any io resource */
 571         found = 0;
 572         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 573                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
 574                         found = 1;
 575                         break;
 576                 }
 577         }
 578
 579         if (!found)
 580                 return;
 581
 582         /* skip our fake bus with only cardbus bridge on it */
 583         if (dev->bus->number == priv->cb_bus)
 584                 return;
 585
 586         /* find on which bus the device is */
 587         if (cb->bus_assigned &&
 588             dev->bus->number == cb->cardbus_busn &&
 589             PCI_SLOT(dev->devfn) == 0)
 590                 new_io_window = 1;
 591         else
 592                 new_io_window = 0;
 593
 594         if (new_io_window == io_window)
 595                 return;
 596
 597         if (io_window != -1) {
 598                 pr_err("bcm63xx: both PCI and cardbus devices "
 599                        "need IO, which hardware cannot do\n");
 600                 return;
 601         }
 602
 603         pr_info("bcm63xx: PCI IO window assigned to %s\n",
 604                (new_io_window == 0) ? "PCI" : "cardbus");
 605
 606         val = __raw_readl(priv->pci + MPI_L2PIOREMAP_REG);
 607         if (io_window)
 608                 val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
 609         else
 610                 val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
 611         __raw_writel(val, priv->pci + MPI_L2PIOREMAP_REG);
 612
 613         io_window = new_io_window;
 614 }
 615 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm6348_pci_fixup);
 616
 617 static struct resource bcm6348_cb_io_resource = {
 618         .name = "bcm6348 CB IO space",
 619         .flags = IORESOURCE_IO,
 620 };
 621 static struct resource bcm6348_cb_mem_resource;
 622
 623 static struct pci_controller bcm6348_cb_controller = {
 624         .pci_ops = &bcm6348_cb_ops,
 625         .io_resource = &bcm6348_cb_io_resource,
 626         .mem_resource = &bcm6348_cb_mem_resource,
 627 };
 628 #endif /* CONFIG_CARDBUS */
 629
 630 static void bcm6348_pci_setup(struct bcm6348_pci *priv)
 631 {
 632         u32 val;
 633
 634         /* Setup local bus to PCI access (PCI memory) */
 635         val = bcm6348_pci_mem_resource.start & MPI_L2P_BASE_MASK;
 636         __raw_writel(val, priv->pci + MPI_L2PMEMBASE1_REG);
 637         __raw_writel(~(resource_size(&bcm6348_pci_mem_resource) - 1),
 638                      priv->pci + MPI_L2PMEMRANGE1_REG);
 639         __raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
 640                      priv->pci + MPI_L2PMEMREMAP1_REG);
 641
 642         /* Set Cardbus IDSEL (type 0 cfg access on primary bus for
 643          * this IDSEL will be done on Cardbus instead) */
 644         val = __raw_readl(priv->pcmcia + PCMCIA_C1_REG);
 645         val &= ~PCMCIA_C1_CBIDSEL_MASK;
 646         val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
 647         __raw_writel(val, priv->pcmcia + PCMCIA_C1_REG);
 648
 649 #ifdef CONFIG_CARDBUS
 650         /* setup local bus to PCI access (Cardbus memory) */
 651         val = bcm6348_cb_mem_resource.start & MPI_L2P_BASE_MASK;
 652         __raw_writel(val, priv->pci + MPI_L2PMEMBASE2_REG);
 653         __raw_writel(~(resource_size(&bcm6348_cb_mem_resource) - 1),
 654                      priv->pci + MPI_L2PMEMRANGE2_REG);
 655         val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
 656         __raw_writel(val, priv->pci + MPI_L2PMEMREMAP2_REG);
 657 #else
 658         /* disable second access windows */
 659         __raw_writel(0, priv->pci + MPI_L2PMEMREMAP2_REG);
 660 #endif
 661
 662         /* setup local bus to PCI access (IO memory), we have only 1
 663          * IO window for both PCI and cardbus, but it cannot handle
 664          * both at the same time, assume standard PCI for now, if
 665          * cardbus card has IO zone, PCI fixup will change window to
 666          * cardbus */
 667         val = bcm6348_pci_io_resource.start & MPI_L2P_BASE_MASK;
 668         __raw_writel(val, priv->pci + MPI_L2PIOBASE_REG);
 669         __raw_writel(~(resource_size(&bcm6348_pci_io_resource) - 1),
 670                      priv->pci + MPI_L2PIORANGE_REG);
 671         __raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
 672                      priv->pci + MPI_L2PIOREMAP_REG);
 673
 674         /* Enable PCI related GPIO pins */
 675         __raw_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK,
 676                      priv->pci + MPI_LOCBUSCTL_REG);
 677
 678         /* Setup PCI to local bus access, used by PCI device to target
 679          * local RAM while bus mastering */
 680         bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
 681         if (priv->remap)
 682                 val = MPI_SP0_REMAP_ENABLE_MASK;
 683         else
 684                 val = 0;
 685         __raw_writel(val, priv->pci + MPI_SP0_REMAP_REG);
 686
 687         bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_4);
 688         __raw_writel(0, priv->pci + MPI_SP1_REMAP_REG);
 689
 690         /* Setup sp0 range to local RAM size */
 691         __raw_writel(~(memblock_phys_mem_size() - 1),
 692                      priv->pci + MPI_SP0_RANGE_REG);
 693         __raw_writel(0, priv->pci + MPI_SP1_RANGE_REG);
 694
 695         /* Change host bridge retry counter to infinite number of
 696          * retries, needed for some broadcom wifi cards with Silicon
 697          * Backplane bus where access to srom seems very slow */
 698         val = bcm6348_int_cfg_readl(BCMPCI_REG_TIMERS);
 699         val &= ~REG_TIMER_RETRY_MASK;
 700         bcm6348_int_cfg_writel(val, BCMPCI_REG_TIMERS);
 701
 702         /* EEnable memory decoder and bus mastering */
 703         val = bcm6348_int_cfg_readl(PCI_COMMAND);
 704         val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 705         bcm6348_int_cfg_writel(val, PCI_COMMAND);
 706
 707         /* Enable read prefetching & disable byte swapping for bus
 708          * mastering transfers */
 709         val = __raw_readl(priv->pci + MPI_PCIMODESEL_REG);
 710         val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
 711         val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
 712         val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
 713         val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
 714         __raw_writel(val, priv->pci + MPI_PCIMODESEL_REG);
 715
 716         /* Enable pci interrupt */
 717         val = __raw_readl(priv->pci + MPI_LOCINT_REG);
 718         val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
 719         __raw_writel(val, priv->pci + MPI_LOCINT_REG);
 720 }
 721
 722 static int bcm6348_pci_probe(struct platform_device *pdev)
 723 {
 724         struct device *dev = &pdev->dev;
 725         struct device_node *np = dev->of_node;
 726         struct bcm6348_pci *priv = &bcm6348_pci;
 727         struct resource *res;
 728         LIST_HEAD(resources);
 729
 730         of_pci_check_probe_only();
 731
 732         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 733         priv->pci = devm_ioremap_resource(dev, res);
 734         if (IS_ERR(priv->pci))
 735                 return PTR_ERR(priv->pci);
 736
 737         priv->pcmcia = priv->pci + PCMCIA_OFFSET;
 738
 739         priv->irq = platform_get_irq(pdev, 0);
 740         if (!priv->irq)
 741                 return -ENODEV;
 742
 743         bmips_pci_irq = priv->irq;
 744
 745         priv->reset = devm_reset_control_get(dev, "pci");
 746         if (IS_ERR(priv->reset))
 747                 return PTR_ERR(priv->reset);
 748
 749         priv->remap = of_property_read_bool(np, "brcm,remap");
 750
 751         reset_control_reset(priv->reset);
 752
 753         pci_load_of_ranges(&bcm6348_pci_controller, np);
 754         if (!bcm6348_pci_mem_resource.start)
 755                 return -EINVAL;
 756
 757         of_pci_parse_bus_range(np, &bcm6348_pci_busn_resource);
 758         pci_add_resource(&resources, &bcm6348_pci_busn_resource);
 759
 760 #ifdef CONFIG_CARDBUS
 761         bcm6348_cb_io_resource.start = bcm6348_pci_io_resource.start + (resource_size(&bcm6348_pci_io_resource) >> 1);
 762         bcm6348_cb_io_resource.end = bcm6348_pci_io_resource.end;
 763         bcm6348_pci_io_resource.end = bcm6348_pci_io_resource.end - (resource_size(&bcm6348_pci_io_resource) >> 1);
 764 #endif
 765
 766         /*
 767          * Configuration accesses are done through IO space, remap 4
 768          * first bytes to access it from CPU.
 769          *
 770          * This means that no IO access from CPU should happen while
 771          * we do a configuration cycle, but there's no way we can add
 772          * a spinlock for each io access, so this is currently kind of
 773          * broken on SMP.
 774          */
 775         priv->io = ioremap(bcm6348_pci_io_resource.start, sizeof(u32));
 776         if (!priv->io)
 777                 return -ENOMEM;
 778
 779         bcm6348_pci_setup(priv);
 780
 781         register_pci_controller(&bcm6348_pci_controller);
 782
 783 #ifdef CONFIG_CARDBUS
 784         priv->cb_bus = -1;
 785         register_pci_controller(&bcm6348_cb_controller);
 786 #endif /* CONFIG_CARDBUS */
 787
 788         /* Mark memory space used for IO mapping as reserved */
 789         request_mem_region(bcm6348_pci_io_resource.start,
 790                            resource_size(&bcm6348_pci_io_resource),
 791                            "BCM6348 PCI IO space");
 792
 793         return 0;
 794 }
 795
 796 static const struct of_device_id bcm6348_pci_of_match[] = {
 797         { .compatible = "brcm,bcm6348-pci", },
 798         { /* sentinel */ }
 799 };
 800
 801 static struct platform_driver bcm6348_pci_driver = {
 802         .probe = bcm6348_pci_probe,
 803         .driver = {
 804                 .name = "bcm6348-pci",
 805                 .of_match_table = bcm6348_pci_of_match,
 806         },
 807 };
 808
 809 int __init bcm6348_pci_init(void)
 810 {
 811         int ret = platform_driver_register(&bcm6348_pci_driver);
 812         if (ret)
 813                 pr_err("pci-bcm6348: Error registering platform driver!\n");
 814         return ret;
 815 }
 816 late_initcall_sync(bcm6348_pci_init);