target/linux/bmips/files/drivers/pci/controller/pci-bcm6348.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * BCM6348 PCI Controller Driver
   4  *
   5  * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
   6  * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
   7  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/kernel.h>
  14 #include <linux/memblock.h>
  15 #include <linux/mm.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_pci.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/pci.h>
  22 #include <linux/reset.h>
  23 #include <linux/types.h>
  24 #include <linux/version.h>
  25 #include <linux/vmalloc.h>
  26
  27 #include "../pci.h"
  28
  29 #define CARDBUS_DUMMY_ID                0x6348
  30 #define CARDBUS_PCI_IDSEL               0x8
  31 #define FAKE_CB_BRIDGE_SLOT             0x1e
  32
  33 #define BCMPCI_REG_TIMERS               0x40
  34 #define REG_TIMER_TRDY_SHIFT            0
  35 #define REG_TIMER_TRDY_MASK             (0xff << REG_TIMER_TRDY_SHIFT)
  36 #define REG_TIMER_RETRY_SHIFT           8
  37 #define REG_TIMER_RETRY_MASK            (0xff << REG_TIMER_RETRY_SHIFT)
  38
  39 #define MPI_SP0_RANGE_REG               0x100
  40 #define MPI_SP0_REMAP_REG               0x104
  41 #define MPI_SP0_REMAP_ENABLE_MASK       (1 << 0)
  42 #define MPI_SP1_RANGE_REG               0x10C
  43 #define MPI_SP1_REMAP_REG               0x110
  44 #define MPI_SP1_REMAP_ENABLE_MASK       (1 << 0)
  45
  46 #define MPI_L2PCFG_REG                  0x11c
  47 #define MPI_L2PCFG_CFG_TYPE_SHIFT       0
  48 #define MPI_L2PCFG_CFG_TYPE_MASK        (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
  49 #define MPI_L2PCFG_REG_SHIFT            2
  50 #define MPI_L2PCFG_REG_MASK             (0x3f << MPI_L2PCFG_REG_SHIFT)
  51 #define MPI_L2PCFG_FUNC_SHIFT           8
  52 #define MPI_L2PCFG_FUNC_MASK            (0x7 << MPI_L2PCFG_FUNC_SHIFT)
  53 #define MPI_L2PCFG_DEVNUM_SHIFT         11
  54 #define MPI_L2PCFG_DEVNUM_MASK          (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
  55 #define MPI_L2PCFG_CFG_USEREG_MASK      (1 << 30)
  56 #define MPI_L2PCFG_CFG_SEL_MASK         (1 << 31)
  57
  58 #define MPI_L2PMEMRANGE1_REG            0x120
  59 #define MPI_L2PMEMBASE1_REG             0x124
  60 #define MPI_L2PMEMREMAP1_REG            0x128
  61 #define MPI_L2PMEMRANGE2_REG            0x12C
  62 #define MPI_L2PMEMBASE2_REG             0x130
  63 #define MPI_L2PMEMREMAP2_REG            0x134
  64 #define MPI_L2PIORANGE_REG              0x138
  65 #define MPI_L2PIOBASE_REG               0x13C
  66 #define MPI_L2PIOREMAP_REG              0x140
  67 #define MPI_L2P_BASE_MASK               (0xffff8000)
  68 #define MPI_L2PREMAP_ENABLED_MASK       (1 << 0)
  69 #define MPI_L2PREMAP_IS_CARDBUS_MASK    (1 << 2)
  70
  71 #define MPI_PCIMODESEL_REG              0x144
  72 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
  73 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
  74 #define MPI_PCIMODESEL_EXT_ARB_MASK     (1 << 2)
  75 #define MPI_PCIMODESEL_PREFETCH_SHIFT   4
  76 #define MPI_PCIMODESEL_PREFETCH_MASK    (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
  77
  78 #define MPI_LOCBUSCTL_REG               0x14c
  79 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK  (1 << 0)
  80 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK   (1 << 1)
  81
  82 #define MPI_LOCINT_REG                  0x150
  83 #define MPI_LOCINT_MASK(x)              (1 << (x + 16))
  84 #define MPI_LOCINT_STAT(x)              (1 << (x))
  85 #define MPI_LOCINT_DIR_FAILED           6
  86 #define MPI_LOCINT_EXT_PCI_INT          7
  87 #define MPI_LOCINT_SERR                 8
  88 #define MPI_LOCINT_CSERR                9
  89
  90 #define MPI_PCICFGCTL_REG               0x178
  91 #define MPI_PCICFGCTL_CFGADDR_SHIFT     2
  92 #define MPI_PCICFGCTL_CFGADDR_MASK      (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
  93 #define MPI_PCICFGCTL_WRITEEN_MASK      (1 << 7)
  94
  95 #define MPI_PCICFGDATA_REG              0x17c
  96
  97 #define PCMCIA_OFFSET                   0x54
  98
  99 #define PCMCIA_C1_REG                   0x0
 100 #define PCMCIA_C1_CD1_MASK              (1 << 0)
 101 #define PCMCIA_C1_CD2_MASK              (1 << 1)
 102 #define PCMCIA_C1_VS1_MASK              (1 << 2)
 103 #define PCMCIA_C1_VS2_MASK              (1 << 3)
 104 #define PCMCIA_C1_VS1OE_MASK            (1 << 6)
 105 #define PCMCIA_C1_VS2OE_MASK            (1 << 7)
 106 #define PCMCIA_C1_CBIDSEL_SHIFT         (8)
 107 #define PCMCIA_C1_CBIDSEL_MASK          (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
 108 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK   (1 << 13)
 109 #define PCMCIA_C1_EN_PCMCIA_MASK        (1 << 14)
 110 #define PCMCIA_C1_EN_CARDBUS_MASK       (1 << 15)
 111 #define PCMCIA_C1_RESET_MASK            (1 << 18)
 112
 113 #ifdef CONFIG_CARDBUS
 114 struct bcm6348_cb {
 115         u16 pci_command;
 116         u8 cb_latency;
 117         u8 subordinate_busn;
 118         u8 cardbus_busn;
 119         u8 pci_busn;
 120         int bus_assigned;
 121         u16 bridge_control;
 122
 123         u32 mem_base0;
 124         u32 mem_limit0;
 125         u32 mem_base1;
 126         u32 mem_limit1;
 127
 128         u32 io_base0;
 129         u32 io_limit0;
 130         u32 io_base1;
 131         u32 io_limit1;
 132 };
 133 #endif /* CONFIG_CARDBUS */
 134
 135 struct bcm6348_pci {
 136         void __iomem *pci;
 137         void __iomem *pcmcia;
 138         void __iomem *io;
 139         int irq;
 140         struct reset_control *reset;
 141         bool remap;
 142 #ifdef CONFIG_CARDBUS
 143         struct bcm6348_cb cb;
 144         int cb_bus;
 145 #endif /* CONFIG_CARDBUS */
 146 };
 147
 148 static struct bcm6348_pci bcm6348_pci;
 149
 150 extern int bmips_pci_irq;
 151
 152 static u32 bcm6348_int_cfg_readl(u32 reg)
 153 {
 154         struct bcm6348_pci *priv = &bcm6348_pci;
 155         u32 tmp;
 156
 157         tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
 158         tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
 159         __raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
 160         iob();
 161         return __raw_readl(priv->pci + MPI_PCICFGDATA_REG);
 162 }
 163
 164 static void bcm6348_int_cfg_writel(u32 val, u32 reg)
 165 {
 166         struct bcm6348_pci *priv = &bcm6348_pci;
 167         u32 tmp;
 168
 169         tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK;
 170         tmp |= MPI_PCICFGCTL_WRITEEN_MASK;
 171         __raw_writel(tmp, priv->pci + MPI_PCICFGCTL_REG);
 172         __raw_writel(val, priv->pci + MPI_PCICFGDATA_REG);
 173 }
 174
 175 /*
 176  * swizzle 32bits data to return only the needed part
 177  */
 178 static int postprocess_read(u32 data, int where, unsigned int size)
 179 {
 180         u32 ret = 0;
 181
 182         switch (size) {
 183         case 1:
 184                 ret = (data >> ((where & 3) << 3)) & 0xff;
 185                 break;
 186         case 2:
 187                 ret = (data >> ((where & 3) << 3)) & 0xffff;
 188                 break;
 189         case 4:
 190                 ret = data;
 191                 break;
 192         }
 193
 194         return ret;
 195 }
 196
 197 static int preprocess_write(u32 orig_data, u32 val, int where,
 198                             unsigned int size)
 199 {
 200         u32 ret = 0;
 201
 202         switch (size) {
 203         case 1:
 204                 ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
 205                         (val << ((where & 3) << 3));
 206                 break;
 207         case 2:
 208                 ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
 209                         (val << ((where & 3) << 3));
 210                 break;
 211         case 4:
 212                 ret = val;
 213                 break;
 214         }
 215
 216         return ret;
 217 }
 218
 219 static int bcm6348_setup_cfg_access(int type, unsigned int busn,
 220                                     unsigned int devfn, int where)
 221 {
 222         struct bcm6348_pci *priv = &bcm6348_pci;
 223         unsigned int slot, func, reg;
 224         u32 val;
 225
 226         slot = PCI_SLOT(devfn);
 227         func = PCI_FUNC(devfn);
 228         reg = where >> 2;
 229
 230         /* sanity check */
 231         if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT))
 232                 return 1;
 233
 234         if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT))
 235                 return 1;
 236
 237         if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT))
 238                 return 1;
 239
 240         /* ok, setup config access */
 241         val = (reg << MPI_L2PCFG_REG_SHIFT);
 242         val |= (func << MPI_L2PCFG_FUNC_SHIFT);
 243         val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT);
 244         val |= MPI_L2PCFG_CFG_USEREG_MASK;
 245         val |= MPI_L2PCFG_CFG_SEL_MASK;
 246         /* type 0 cycle for local bus, type 1 cycle for anything else */
 247         if (type != 0) {
 248                 /* FIXME: how to specify bus ??? */
 249                 val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT);
 250         }
 251         __raw_writel(val, priv->pci + MPI_L2PCFG_REG);
 252
 253         return 0;
 254 }
 255
 256
 257 static int bcm6348_do_cfg_read(int type, unsigned int busn,
 258                                unsigned int devfn, int where, int size,
 259                                u32 *val)
 260 {
 261         struct bcm6348_pci *priv = &bcm6348_pci;
 262         u32 data;
 263
 264         /* two phase cycle, first we write address, then read data at
 265          * another location, caller already has a spinlock so no need
 266          * to add one here */
 267         if (bcm6348_setup_cfg_access(type, busn, devfn, where))
 268                 return PCIBIOS_DEVICE_NOT_FOUND;
 269         iob();
 270         data = le32_to_cpu(__raw_readl(priv->io));
 271         /* restore IO space normal behaviour */
 272         __raw_writel(0, priv->pci + MPI_L2PCFG_REG);
 273
 274         *val = postprocess_read(data, where, size);
 275
 276         return PCIBIOS_SUCCESSFUL;
 277 }
 278
 279 static int bcm6348_do_cfg_write(int type, unsigned int busn,
 280                                 unsigned int devfn, int where, int size,
 281                                 u32 val)
 282 {
 283         struct bcm6348_pci *priv = &bcm6348_pci;
 284         u32 data;
 285
 286         /* two phase cycle, first we write address, then write data to
 287          * another location, caller already has a spinlock so no need
 288          * to add one here */
 289         if (bcm6348_setup_cfg_access(type, busn, devfn, where))
 290                 return PCIBIOS_DEVICE_NOT_FOUND;
 291         iob();
 292
 293         data = le32_to_cpu(__raw_readl(priv->io));
 294         data = preprocess_write(data, val, where, size);
 295
 296         __raw_writel(cpu_to_le32(data), priv->io);
 297         wmb();
 298         /* no way to know the access is done, we have to wait */
 299         udelay(500);
 300         /* restore IO space normal behaviour */
 301         __raw_writel(0, priv->pci + MPI_L2PCFG_REG);
 302
 303         return PCIBIOS_SUCCESSFUL;
 304 }
 305
 306 static int bcm6348_pci_read(struct pci_bus *bus, unsigned int devfn,
 307                              int where, int size, u32 *val)
 308 {
 309         int type;
 310
 311         type = bus->parent ? 1 : 0;
 312
 313         if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
 314                 return PCIBIOS_DEVICE_NOT_FOUND;
 315
 316         return bcm6348_do_cfg_read(type, bus->number, devfn,
 317                                    where, size, val);
 318 }
 319
 320 static int bcm6348_pci_write(struct pci_bus *bus, unsigned int devfn,
 321                               int where, int size, u32 val)
 322 {
 323         int type;
 324
 325         type = bus->parent ? 1 : 0;
 326
 327         if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL)
 328                 return PCIBIOS_DEVICE_NOT_FOUND;
 329
 330         return bcm6348_do_cfg_write(type, bus->number, devfn,
 331                                     where, size, val);
 332 }
 333
 334 static struct pci_ops bcm6348_pci_ops = {
 335         .read = bcm6348_pci_read,
 336         .write = bcm6348_pci_write,
 337 };
 338
 339 static struct resource bcm6348_pci_io_resource = {
 340         .name = "BCM6348 PCI IO space",
 341         .flags = IORESOURCE_IO,
 342 };
 343 static struct resource bcm6348_pci_mem_resource;
 344 static struct resource bcm6348_pci_busn_resource;
 345
 346 static struct pci_controller bcm6348_pci_controller = {
 347         .pci_ops = &bcm6348_pci_ops,
 348         .io_resource = &bcm6348_pci_io_resource,
 349         .mem_resource = &bcm6348_pci_mem_resource,
 350 #if LINUX_VERSION_CODE < KERNEL_VERSION(5,13,0)
 351         .busn_resource = &bcm6348_pci_busn_resource,
 352 #endif
 353 };
 354
 355 #ifdef CONFIG_CARDBUS
 356 static int bcm6348_cb_bridge_read(int where, int size, u32 *val)
 357 {
 358         struct bcm6348_cb *cb = &bcm6348_pci.cb;
 359         unsigned int reg;
 360         u32 data;
 361
 362         data = 0;
 363         reg = where >> 2;
 364         switch (reg) {
 365         case (PCI_VENDOR_ID >> 2):
 366         case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
 367                 /* create dummy vendor/device id from our cpu id */
 368                 data = (CARDBUS_DUMMY_ID << 16) | PCI_VENDOR_ID_BROADCOM;
 369                 break;
 370
 371         case (PCI_COMMAND >> 2):
 372                 data = (PCI_STATUS_DEVSEL_SLOW << 16);
 373                 data |= cb->pci_command;
 374                 break;
 375
 376         case (PCI_CLASS_REVISION >> 2):
 377                 data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
 378                 break;
 379
 380         case (PCI_CACHE_LINE_SIZE >> 2):
 381                 data = (PCI_HEADER_TYPE_CARDBUS << 16);
 382                 break;
 383
 384         case (PCI_INTERRUPT_LINE >> 2):
 385                 /* bridge control */
 386                 data = (cb->bridge_control << 16);
 387                 /* pin:intA line:0xff */
 388                 data |= (0x1 << 8) | 0xff;
 389                 break;
 390
 391         case (PCI_CB_PRIMARY_BUS >> 2):
 392                 data = (cb->cb_latency << 24);
 393                 data |= (cb->subordinate_busn << 16);
 394                 data |= (cb->cardbus_busn << 8);
 395                 data |= cb->pci_busn;
 396                 break;
 397
 398         case (PCI_CB_MEMORY_BASE_0 >> 2):
 399                 data = cb->mem_base0;
 400                 break;
 401
 402         case (PCI_CB_MEMORY_LIMIT_0 >> 2):
 403                 data = cb->mem_limit0;
 404                 break;
 405
 406         case (PCI_CB_MEMORY_BASE_1 >> 2):
 407                 data = cb->mem_base1;
 408                 break;
 409
 410         case (PCI_CB_MEMORY_LIMIT_1 >> 2):
 411                 data = cb->mem_limit1;
 412                 break;
 413
 414         case (PCI_CB_IO_BASE_0 >> 2):
 415                 /* | 1 for 32bits io support */
 416                 data = cb->io_base0 | 0x1;
 417                 break;
 418
 419         case (PCI_CB_IO_LIMIT_0 >> 2):
 420                 data = cb->io_limit0;
 421                 break;
 422
 423         case (PCI_CB_IO_BASE_1 >> 2):
 424                 /* | 1 for 32bits io support */
 425                 data = cb->io_base1 | 0x1;
 426                 break;
 427
 428         case (PCI_CB_IO_LIMIT_1 >> 2):
 429                 data = cb->io_limit1;
 430                 break;
 431         }
 432
 433         *val = postprocess_read(data, where, size);
 434         return PCIBIOS_SUCCESSFUL;
 435 }
 436
 437 /*
 438  * emulate configuration write access on a cardbus bridge
 439  */
 440 static int bcm6348_cb_bridge_write(int where, int size, u32 val)
 441 {
 442         struct bcm6348_cb *cb = &bcm6348_pci.cb;
 443         unsigned int reg;
 444         u32 data, tmp;
 445         int ret;
 446
 447         ret = bcm6348_cb_bridge_read((where & ~0x3), 4, &data);
 448         if (ret != PCIBIOS_SUCCESSFUL)
 449                 return ret;
 450
 451         data = preprocess_write(data, val, where, size);
 452
 453         reg = where >> 2;
 454         switch (reg) {
 455         case (PCI_COMMAND >> 2):
 456                 cb->pci_command = (data & 0xffff);
 457                 break;
 458
 459         case (PCI_CB_PRIMARY_BUS >> 2):
 460                 cb->cb_latency = (data >> 24) & 0xff;
 461                 cb->subordinate_busn = (data >> 16) & 0xff;
 462                 cb->cardbus_busn = (data >> 8) & 0xff;
 463                 cb->pci_busn = data & 0xff;
 464                 if (cb->cardbus_busn)
 465                         cb->bus_assigned = 1;
 466                 break;
 467
 468         case (PCI_INTERRUPT_LINE >> 2):
 469                 tmp = (data >> 16) & 0xffff;
 470                 /* Disable memory prefetch support */
 471                 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
 472                 tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
 473                 cb->bridge_control = tmp;
 474                 break;
 475
 476         case (PCI_CB_MEMORY_BASE_0 >> 2):
 477                 cb->mem_base0 = data;
 478                 break;
 479
 480         case (PCI_CB_MEMORY_LIMIT_0 >> 2):
 481                 cb->mem_limit0 = data;
 482                 break;
 483
 484         case (PCI_CB_MEMORY_BASE_1 >> 2):
 485                 cb->mem_base1 = data;
 486                 break;
 487
 488         case (PCI_CB_MEMORY_LIMIT_1 >> 2):
 489                 cb->mem_limit1 = data;
 490                 break;
 491
 492         case (PCI_CB_IO_BASE_0 >> 2):
 493                 cb->io_base0 = data;
 494                 break;
 495
 496         case (PCI_CB_IO_LIMIT_0 >> 2):
 497                 cb->io_limit0 = data;
 498                 break;
 499
 500         case (PCI_CB_IO_BASE_1 >> 2):
 501                 cb->io_base1 = data;
 502                 break;
 503
 504         case (PCI_CB_IO_LIMIT_1 >> 2):
 505                 cb->io_limit1 = data;
 506                 break;
 507         }
 508
 509         return PCIBIOS_SUCCESSFUL;
 510 }
 511
 512 static int bcm6348_cb_read(struct pci_bus *bus, unsigned int devfn,
 513                            int where, int size, u32 *val)
 514 {
 515         struct bcm6348_pci *priv = &bcm6348_pci;
 516         struct bcm6348_cb *cb = &priv->cb;
 517
 518         /* Snoop access to slot 0x1e on root bus, we fake a cardbus
 519          * bridge at this location */
 520         if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
 521                 priv->cb_bus = bus->number;
 522                 return bcm6348_cb_bridge_read(where, size, val);
 523         }
 524
 525         /* A configuration cycle for the device behind the cardbus
 526          * bridge is actually done as a type 0 cycle on the primary
 527          * bus. This means that only one device can be on the cardbus
 528          * bus */
 529         if (cb->bus_assigned &&
 530             bus->number == cb->cardbus_busn &&
 531             PCI_SLOT(devfn) == 0)
 532                 return bcm6348_do_cfg_read(0, 0,
 533                                            PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
 534                                            where, size, val);
 535
 536         return PCIBIOS_DEVICE_NOT_FOUND;
 537 }
 538
 539 static int bcm6348_cb_write(struct pci_bus *bus, unsigned int devfn,
 540                             int where, int size, u32 val)
 541 {
 542         struct bcm6348_pci *priv = &bcm6348_pci;
 543         struct bcm6348_cb *cb = &priv->cb;
 544
 545         if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
 546                 priv->cb_bus = bus->number;
 547                 return bcm6348_cb_bridge_write(where, size, val);
 548         }
 549
 550         if (cb->bus_assigned &&
 551             bus->number == cb->cardbus_busn &&
 552             PCI_SLOT(devfn) == 0)
 553                 return bcm6348_do_cfg_write(0, 0,
 554                                             PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
 555                                             where, size, val);
 556
 557         return PCIBIOS_DEVICE_NOT_FOUND;
 558 }
 559
 560 static struct pci_ops bcm6348_cb_ops = {
 561         .read = bcm6348_cb_read,
 562         .write = bcm6348_cb_write,
 563 };
 564
 565 /*
 566  * only one IO window, so it  cannot be shared by PCI and cardbus, use
 567  * fixup to choose and detect unhandled configuration
 568  */
 569 static void bcm6348_pci_fixup(struct pci_dev *dev)
 570 {
 571         struct bcm6348_pci *priv = &bcm6348_pci;
 572         struct bcm6348_cb *cb = &priv->cb;
 573         static int io_window = -1;
 574         int i, found, new_io_window;
 575         u32 val;
 576
 577         /* look for any io resource */
 578         found = 0;
 579         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
 580                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
 581                         found = 1;
 582                         break;
 583                 }
 584         }
 585
 586         if (!found)
 587                 return;
 588
 589         /* skip our fake bus with only cardbus bridge on it */
 590         if (dev->bus->number == priv->cb_bus)
 591                 return;
 592
 593         /* find on which bus the device is */
 594         if (cb->bus_assigned &&
 595             dev->bus->number == cb->cardbus_busn &&
 596             PCI_SLOT(dev->devfn) == 0)
 597                 new_io_window = 1;
 598         else
 599                 new_io_window = 0;
 600
 601         if (new_io_window == io_window)
 602                 return;
 603
 604         if (io_window != -1) {
 605                 pr_err("bcm63xx: both PCI and cardbus devices "
 606                        "need IO, which hardware cannot do\n");
 607                 return;
 608         }
 609
 610         pr_info("bcm63xx: PCI IO window assigned to %s\n",
 611                (new_io_window == 0) ? "PCI" : "cardbus");
 612
 613         val = __raw_readl(priv->pci + MPI_L2PIOREMAP_REG);
 614         if (io_window)
 615                 val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
 616         else
 617                 val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
 618         __raw_writel(val, priv->pci + MPI_L2PIOREMAP_REG);
 619
 620         io_window = new_io_window;
 621 }
 622 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm6348_pci_fixup);
 623
 624 static struct resource bcm6348_cb_io_resource = {
 625         .name = "bcm6348 CB IO space",
 626         .flags = IORESOURCE_IO,
 627 };
 628 static struct resource bcm6348_cb_mem_resource;
 629
 630 static struct pci_controller bcm6348_cb_controller = {
 631         .pci_ops = &bcm6348_cb_ops,
 632         .io_resource = &bcm6348_cb_io_resource,
 633         .mem_resource = &bcm6348_cb_mem_resource,
 634 };
 635 #endif /* CONFIG_CARDBUS */
 636
 637 static void bcm6348_pci_setup(struct bcm6348_pci *priv)
 638 {
 639         u32 val;
 640
 641         /* Setup local bus to PCI access (PCI memory) */
 642         val = bcm6348_pci_mem_resource.start & MPI_L2P_BASE_MASK;
 643         __raw_writel(val, priv->pci + MPI_L2PMEMBASE1_REG);
 644         __raw_writel(~(resource_size(&bcm6348_pci_mem_resource) - 1),
 645                      priv->pci + MPI_L2PMEMRANGE1_REG);
 646         __raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
 647                      priv->pci + MPI_L2PMEMREMAP1_REG);
 648
 649         /* Set Cardbus IDSEL (type 0 cfg access on primary bus for
 650          * this IDSEL will be done on Cardbus instead) */
 651         val = __raw_readl(priv->pcmcia + PCMCIA_C1_REG);
 652         val &= ~PCMCIA_C1_CBIDSEL_MASK;
 653         val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
 654         __raw_writel(val, priv->pcmcia + PCMCIA_C1_REG);
 655
 656 #ifdef CONFIG_CARDBUS
 657         /* setup local bus to PCI access (Cardbus memory) */
 658         val = bcm6348_cb_mem_resource.start & MPI_L2P_BASE_MASK;
 659         __raw_writel(val, priv->pci + MPI_L2PMEMBASE2_REG);
 660         __raw_writel(~(resource_size(&bcm6348_cb_mem_resource) - 1),
 661                      priv->pci + MPI_L2PMEMRANGE2_REG);
 662         val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
 663         __raw_writel(val, priv->pci + MPI_L2PMEMREMAP2_REG);
 664 #else
 665         /* disable second access windows */
 666         __raw_writel(0, priv->pci + MPI_L2PMEMREMAP2_REG);
 667 #endif
 668
 669         /* setup local bus to PCI access (IO memory), we have only 1
 670          * IO window for both PCI and cardbus, but it cannot handle
 671          * both at the same time, assume standard PCI for now, if
 672          * cardbus card has IO zone, PCI fixup will change window to
 673          * cardbus */
 674         val = bcm6348_pci_io_resource.start & MPI_L2P_BASE_MASK;
 675         __raw_writel(val, priv->pci + MPI_L2PIOBASE_REG);
 676         __raw_writel(~(resource_size(&bcm6348_pci_io_resource) - 1),
 677                      priv->pci + MPI_L2PIORANGE_REG);
 678         __raw_writel(val | MPI_L2PREMAP_ENABLED_MASK,
 679                      priv->pci + MPI_L2PIOREMAP_REG);
 680
 681         /* Enable PCI related GPIO pins */
 682         __raw_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK,
 683                      priv->pci + MPI_LOCBUSCTL_REG);
 684
 685         /* Setup PCI to local bus access, used by PCI device to target
 686          * local RAM while bus mastering */
 687         bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_3);
 688         if (priv->remap)
 689                 val = MPI_SP0_REMAP_ENABLE_MASK;
 690         else
 691                 val = 0;
 692         __raw_writel(val, priv->pci + MPI_SP0_REMAP_REG);
 693
 694         bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_4);
 695         __raw_writel(0, priv->pci + MPI_SP1_REMAP_REG);
 696
 697         /* Setup sp0 range to local RAM size */
 698         __raw_writel(~(memblock_phys_mem_size() - 1),
 699                      priv->pci + MPI_SP0_RANGE_REG);
 700         __raw_writel(0, priv->pci + MPI_SP1_RANGE_REG);
 701
 702         /* Change host bridge retry counter to infinite number of
 703          * retries, needed for some broadcom wifi cards with Silicon
 704          * Backplane bus where access to srom seems very slow */
 705         val = bcm6348_int_cfg_readl(BCMPCI_REG_TIMERS);
 706         val &= ~REG_TIMER_RETRY_MASK;
 707         bcm6348_int_cfg_writel(val, BCMPCI_REG_TIMERS);
 708
 709         /* EEnable memory decoder and bus mastering */
 710         val = bcm6348_int_cfg_readl(PCI_COMMAND);
 711         val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 712         bcm6348_int_cfg_writel(val, PCI_COMMAND);
 713
 714         /* Enable read prefetching & disable byte swapping for bus
 715          * mastering transfers */
 716         val = __raw_readl(priv->pci + MPI_PCIMODESEL_REG);
 717         val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK;
 718         val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK;
 719         val &= ~MPI_PCIMODESEL_PREFETCH_MASK;
 720         val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT);
 721         __raw_writel(val, priv->pci + MPI_PCIMODESEL_REG);
 722
 723         /* Enable pci interrupt */
 724         val = __raw_readl(priv->pci + MPI_LOCINT_REG);
 725         val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT);
 726         __raw_writel(val, priv->pci + MPI_LOCINT_REG);
 727 }
 728
 729 static int bcm6348_pci_probe(struct platform_device *pdev)
 730 {
 731         struct device *dev = &pdev->dev;
 732         struct device_node *np = dev->of_node;
 733         struct bcm6348_pci *priv = &bcm6348_pci;
 734         struct resource *res;
 735 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,13,0)
 736         LIST_HEAD(resources);
 737 #endif
 738
 739         of_pci_check_probe_only();
 740
 741         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pci");
 742         priv->pci = devm_ioremap_resource(dev, res);
 743         if (IS_ERR(priv->pci))
 744                 return PTR_ERR(priv->pci);
 745
 746         priv->pcmcia = priv->pci + PCMCIA_OFFSET;
 747
 748         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pci-io");
 749         if (!res)
 750                 return -EINVAL;
 751 #ifdef CONFIG_CARDBUS
 752         bcm6348_pci_io_resource.start = res->start;
 753         bcm6348_pci_io_resource.end = res->end - (resource_size(res) >> 1);
 754         bcm6348_cb_io_resource.start = res->start + (resource_size(res) >> 1);
 755         bcm6348_cb_io_resource.end = res->end;
 756 #else
 757         bcm6348_pci_io_resource.start = res->start;
 758         bcm6348_pci_io_resource.end = res->end;
 759 #endif
 760
 761         priv->irq = platform_get_irq(pdev, 0);
 762         if (!priv->irq)
 763                 return -ENODEV;
 764
 765         bmips_pci_irq = priv->irq;
 766
 767         priv->reset = devm_reset_control_get(dev, "pci");
 768         if (IS_ERR(priv->reset))
 769                 return PTR_ERR(priv->reset);
 770
 771         priv->remap = of_property_read_bool(np, "brcm,remap");
 772
 773         reset_control_reset(priv->reset);
 774
 775         pci_load_of_ranges(&bcm6348_pci_controller, np);
 776         if (!bcm6348_pci_mem_resource.start)
 777                 return -EINVAL;
 778
 779         of_pci_parse_bus_range(np, &bcm6348_pci_busn_resource);
 780 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,13,0)
 781         pci_add_resource(&resources, &bcm6348_pci_busn_resource);
 782 #endif
 783
 784         /*
 785          * Configuration accesses are done through IO space, remap 4
 786          * first bytes to access it from CPU.
 787          *
 788          * This means that no IO access from CPU should happen while
 789          * we do a configuration cycle, but there's no way we can add
 790          * a spinlock for each io access, so this is currently kind of
 791          * broken on SMP.
 792          */
 793         priv->io = ioremap(bcm6348_pci_io_resource.start, sizeof(u32));
 794         if (!priv->io)
 795                 return -ENOMEM;
 796
 797         bcm6348_pci_setup(priv);
 798
 799         register_pci_controller(&bcm6348_pci_controller);
 800
 801 #ifdef CONFIG_CARDBUS
 802         priv->cb_bus = -1;
 803         register_pci_controller(&bcm6348_cb_controller);
 804 #endif /* CONFIG_CARDBUS */
 805
 806         /* Mark memory space used for IO mapping as reserved */
 807         request_mem_region(bcm6348_pci_io_resource.start,
 808                            resource_size(&bcm6348_pci_io_resource),
 809                            "BCM6348 PCI IO space");
 810
 811         return 0;
 812 }
 813
 814 static const struct of_device_id bcm6348_pci_of_match[] = {
 815         { .compatible = "brcm,bcm6348-pci", },
 816         { /* sentinel */ }
 817 };
 818
 819 static struct platform_driver bcm6348_pci_driver = {
 820         .probe = bcm6348_pci_probe,
 821         .driver = {
 822                 .name = "bcm6348-pci",
 823                 .of_match_table = bcm6348_pci_of_match,
 824         },
 825 };
 826
 827 int __init bcm6348_pci_init(void)
 828 {
 829         int ret = platform_driver_register(&bcm6348_pci_driver);
 830         if (ret)
 831                 pr_err("pci-bcm6348: Error registering platform driver!\n");
 832         return ret;
 833 }
 834 late_initcall_sync(bcm6348_pci_init);