1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * BCM6348 PCI Controller Driver
5 * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
6 * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
7 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
10 #include <linux/clk.h>
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/kernel.h>
14 #include <linux/memblock.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/of_gpio.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_pci.h>
21 #include <linux/of_platform.h>
22 #include <linux/pci.h>
23 #include <linux/reset.h>
24 #include <linux/types.h>
25 #include <linux/vmalloc.h>
29 #define CARDBUS_DUMMY_ID 0x6348
30 #define CARDBUS_PCI_IDSEL 0x8
31 #define FAKE_CB_BRIDGE_SLOT 0x1e
33 #define BCMPCI_REG_TIMERS 0x40
34 #define REG_TIMER_TRDY_SHIFT 0
35 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
36 #define REG_TIMER_RETRY_SHIFT 8
37 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
39 #define MPI_SP0_RANGE_REG 0x100
40 #define MPI_SP0_REMAP_REG 0x104
41 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
42 #define MPI_SP1_RANGE_REG 0x10C
43 #define MPI_SP1_REMAP_REG 0x110
44 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
46 #define MPI_L2PCFG_REG 0x11c
47 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
48 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
49 #define MPI_L2PCFG_REG_SHIFT 2
50 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
51 #define MPI_L2PCFG_FUNC_SHIFT 8
52 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
53 #define MPI_L2PCFG_DEVNUM_SHIFT 11
54 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
55 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
56 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
58 #define MPI_L2PMEMRANGE1_REG 0x120
59 #define MPI_L2PMEMBASE1_REG 0x124
60 #define MPI_L2PMEMREMAP1_REG 0x128
61 #define MPI_L2PMEMRANGE2_REG 0x12C
62 #define MPI_L2PMEMBASE2_REG 0x130
63 #define MPI_L2PMEMREMAP2_REG 0x134
64 #define MPI_L2PIORANGE_REG 0x138
65 #define MPI_L2PIOBASE_REG 0x13C
66 #define MPI_L2PIOREMAP_REG 0x140
67 #define MPI_L2P_BASE_MASK (0xffff8000)
68 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
69 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
71 #define MPI_PCIMODESEL_REG 0x144
72 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
73 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
74 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
75 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
76 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
78 #define MPI_LOCBUSCTL_REG 0x14c
79 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
80 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
82 #define MPI_LOCINT_REG 0x150
83 #define MPI_LOCINT_MASK(x) (1 << (x + 16))
84 #define MPI_LOCINT_STAT(x) (1 << (x))
85 #define MPI_LOCINT_DIR_FAILED 6
86 #define MPI_LOCINT_EXT_PCI_INT 7
87 #define MPI_LOCINT_SERR 8
88 #define MPI_LOCINT_CSERR 9
90 #define MPI_PCICFGCTL_REG 0x178
91 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
92 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
93 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
95 #define MPI_PCICFGDATA_REG 0x17c
97 #define PCMCIA_OFFSET 0x54
99 #define PCMCIA_C1_REG 0x0
100 #define PCMCIA_C1_CD1_MASK (1 << 0)
101 #define PCMCIA_C1_CD2_MASK (1 << 1)
102 #define PCMCIA_C1_VS1_MASK (1 << 2)
103 #define PCMCIA_C1_VS2_MASK (1 << 3)
104 #define PCMCIA_C1_VS1OE_MASK (1 << 6)
105 #define PCMCIA_C1_VS2OE_MASK (1 << 7)
106 #define PCMCIA_C1_CBIDSEL_SHIFT (8)
107 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
108 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
109 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
110 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
111 #define PCMCIA_C1_RESET_MASK (1 << 18)
113 #ifdef CONFIG_CARDBUS
133 #endif /* CONFIG_CARDBUS */
137 void __iomem
*pcmcia
;
140 struct reset_control
*reset
;
142 #ifdef CONFIG_CARDBUS
143 struct bcm6348_cb cb
;
145 #endif /* CONFIG_CARDBUS */
148 static struct bcm6348_pci bcm6348_pci
;
150 extern int bmips_pci_irq
;
152 static u32
bcm6348_int_cfg_readl(u32 reg
)
154 struct bcm6348_pci
*priv
= &bcm6348_pci
;
157 tmp
= reg
& MPI_PCICFGCTL_CFGADDR_MASK
;
158 tmp
|= MPI_PCICFGCTL_WRITEEN_MASK
;
159 __raw_writel(tmp
, priv
->pci
+ MPI_PCICFGCTL_REG
);
161 return __raw_readl(priv
->pci
+ MPI_PCICFGDATA_REG
);
164 static void bcm6348_int_cfg_writel(u32 val
, u32 reg
)
166 struct bcm6348_pci
*priv
= &bcm6348_pci
;
169 tmp
= reg
& MPI_PCICFGCTL_CFGADDR_MASK
;
170 tmp
|= MPI_PCICFGCTL_WRITEEN_MASK
;
171 __raw_writel(tmp
, priv
->pci
+ MPI_PCICFGCTL_REG
);
172 __raw_writel(val
, priv
->pci
+ MPI_PCICFGDATA_REG
);
176 * swizzle 32bits data to return only the needed part
178 static int postprocess_read(u32 data
, int where
, unsigned int size
)
184 ret
= (data
>> ((where
& 3) << 3)) & 0xff;
187 ret
= (data
>> ((where
& 3) << 3)) & 0xffff;
197 static int preprocess_write(u32 orig_data
, u32 val
, int where
,
204 ret
= (orig_data
& ~(0xff << ((where
& 3) << 3))) |
205 (val
<< ((where
& 3) << 3));
208 ret
= (orig_data
& ~(0xffff << ((where
& 3) << 3))) |
209 (val
<< ((where
& 3) << 3));
219 static int bcm6348_setup_cfg_access(int type
, unsigned int busn
,
220 unsigned int devfn
, int where
)
222 struct bcm6348_pci
*priv
= &bcm6348_pci
;
223 unsigned int slot
, func
, reg
;
226 slot
= PCI_SLOT(devfn
);
227 func
= PCI_FUNC(devfn
);
231 if (slot
> (MPI_L2PCFG_DEVNUM_MASK
>> MPI_L2PCFG_DEVNUM_SHIFT
))
234 if (func
> (MPI_L2PCFG_FUNC_MASK
>> MPI_L2PCFG_FUNC_SHIFT
))
237 if (reg
> (MPI_L2PCFG_REG_MASK
>> MPI_L2PCFG_REG_SHIFT
))
240 /* ok, setup config access */
241 val
= (reg
<< MPI_L2PCFG_REG_SHIFT
);
242 val
|= (func
<< MPI_L2PCFG_FUNC_SHIFT
);
243 val
|= (slot
<< MPI_L2PCFG_DEVNUM_SHIFT
);
244 val
|= MPI_L2PCFG_CFG_USEREG_MASK
;
245 val
|= MPI_L2PCFG_CFG_SEL_MASK
;
246 /* type 0 cycle for local bus, type 1 cycle for anything else */
248 /* FIXME: how to specify bus ??? */
249 val
|= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT
);
251 __raw_writel(val
, priv
->pci
+ MPI_L2PCFG_REG
);
257 static int bcm6348_do_cfg_read(int type
, unsigned int busn
,
258 unsigned int devfn
, int where
, int size
,
261 struct bcm6348_pci
*priv
= &bcm6348_pci
;
264 /* two phase cycle, first we write address, then read data at
265 * another location, caller already has a spinlock so no need
267 if (bcm6348_setup_cfg_access(type
, busn
, devfn
, where
))
268 return PCIBIOS_DEVICE_NOT_FOUND
;
270 data
= le32_to_cpu(__raw_readl(priv
->io
));
271 /* restore IO space normal behaviour */
272 __raw_writel(0, priv
->pci
+ MPI_L2PCFG_REG
);
274 *val
= postprocess_read(data
, where
, size
);
276 return PCIBIOS_SUCCESSFUL
;
279 static int bcm6348_do_cfg_write(int type
, unsigned int busn
,
280 unsigned int devfn
, int where
, int size
,
283 struct bcm6348_pci
*priv
= &bcm6348_pci
;
286 /* two phase cycle, first we write address, then write data to
287 * another location, caller already has a spinlock so no need
289 if (bcm6348_setup_cfg_access(type
, busn
, devfn
, where
))
290 return PCIBIOS_DEVICE_NOT_FOUND
;
293 data
= le32_to_cpu(__raw_readl(priv
->io
));
294 data
= preprocess_write(data
, val
, where
, size
);
296 __raw_writel(cpu_to_le32(data
), priv
->io
);
298 /* no way to know the access is done, we have to wait */
300 /* restore IO space normal behaviour */
301 __raw_writel(0, priv
->pci
+ MPI_L2PCFG_REG
);
303 return PCIBIOS_SUCCESSFUL
;
306 static int bcm6348_pci_read(struct pci_bus
*bus
, unsigned int devfn
,
307 int where
, int size
, u32
*val
)
311 type
= bus
->parent
? 1 : 0;
313 if (type
== 0 && PCI_SLOT(devfn
) == CARDBUS_PCI_IDSEL
)
314 return PCIBIOS_DEVICE_NOT_FOUND
;
316 return bcm6348_do_cfg_read(type
, bus
->number
, devfn
,
320 static int bcm6348_pci_write(struct pci_bus
*bus
, unsigned int devfn
,
321 int where
, int size
, u32 val
)
325 type
= bus
->parent
? 1 : 0;
327 if (type
== 0 && PCI_SLOT(devfn
) == CARDBUS_PCI_IDSEL
)
328 return PCIBIOS_DEVICE_NOT_FOUND
;
330 return bcm6348_do_cfg_write(type
, bus
->number
, devfn
,
334 static struct pci_ops bcm6348_pci_ops
= {
335 .read
= bcm6348_pci_read
,
336 .write
= bcm6348_pci_write
,
339 static struct resource bcm6348_pci_io_resource
;
340 static struct resource bcm6348_pci_mem_resource
;
341 static struct resource bcm6348_pci_busn_resource
;
343 static struct pci_controller bcm6348_pci_controller
= {
344 .pci_ops
= &bcm6348_pci_ops
,
345 .io_resource
= &bcm6348_pci_io_resource
,
346 .mem_resource
= &bcm6348_pci_mem_resource
,
349 #ifdef CONFIG_CARDBUS
350 static int bcm6348_cb_bridge_read(int where
, int size
, u32
*val
)
352 struct bcm6348_cb
*cb
= &bcm6348_pci
.cb
;
359 case (PCI_VENDOR_ID
>> 2):
360 case (PCI_CB_SUBSYSTEM_VENDOR_ID
>> 2):
361 /* create dummy vendor/device id from our cpu id */
362 data
= (CARDBUS_DUMMY_ID
<< 16) | PCI_VENDOR_ID_BROADCOM
;
365 case (PCI_COMMAND
>> 2):
366 data
= (PCI_STATUS_DEVSEL_SLOW
<< 16);
367 data
|= cb
->pci_command
;
370 case (PCI_CLASS_REVISION
>> 2):
371 data
= (PCI_CLASS_BRIDGE_CARDBUS
<< 16);
374 case (PCI_CACHE_LINE_SIZE
>> 2):
375 data
= (PCI_HEADER_TYPE_CARDBUS
<< 16);
378 case (PCI_INTERRUPT_LINE
>> 2):
380 data
= (cb
->bridge_control
<< 16);
381 /* pin:intA line:0xff */
382 data
|= (0x1 << 8) | 0xff;
385 case (PCI_CB_PRIMARY_BUS
>> 2):
386 data
= (cb
->cb_latency
<< 24);
387 data
|= (cb
->subordinate_busn
<< 16);
388 data
|= (cb
->cardbus_busn
<< 8);
389 data
|= cb
->pci_busn
;
392 case (PCI_CB_MEMORY_BASE_0
>> 2):
393 data
= cb
->mem_base0
;
396 case (PCI_CB_MEMORY_LIMIT_0
>> 2):
397 data
= cb
->mem_limit0
;
400 case (PCI_CB_MEMORY_BASE_1
>> 2):
401 data
= cb
->mem_base1
;
404 case (PCI_CB_MEMORY_LIMIT_1
>> 2):
405 data
= cb
->mem_limit1
;
408 case (PCI_CB_IO_BASE_0
>> 2):
409 /* | 1 for 32bits io support */
410 data
= cb
->io_base0
| 0x1;
413 case (PCI_CB_IO_LIMIT_0
>> 2):
414 data
= cb
->io_limit0
;
417 case (PCI_CB_IO_BASE_1
>> 2):
418 /* | 1 for 32bits io support */
419 data
= cb
->io_base1
| 0x1;
422 case (PCI_CB_IO_LIMIT_1
>> 2):
423 data
= cb
->io_limit1
;
427 *val
= postprocess_read(data
, where
, size
);
428 return PCIBIOS_SUCCESSFUL
;
432 * emulate configuration write access on a cardbus bridge
434 static int bcm6348_cb_bridge_write(int where
, int size
, u32 val
)
436 struct bcm6348_cb
*cb
= &bcm6348_pci
.cb
;
441 ret
= bcm6348_cb_bridge_read((where
& ~0x3), 4, &data
);
442 if (ret
!= PCIBIOS_SUCCESSFUL
)
445 data
= preprocess_write(data
, val
, where
, size
);
449 case (PCI_COMMAND
>> 2):
450 cb
->pci_command
= (data
& 0xffff);
453 case (PCI_CB_PRIMARY_BUS
>> 2):
454 cb
->cb_latency
= (data
>> 24) & 0xff;
455 cb
->subordinate_busn
= (data
>> 16) & 0xff;
456 cb
->cardbus_busn
= (data
>> 8) & 0xff;
457 cb
->pci_busn
= data
& 0xff;
458 if (cb
->cardbus_busn
)
459 cb
->bus_assigned
= 1;
462 case (PCI_INTERRUPT_LINE
>> 2):
463 tmp
= (data
>> 16) & 0xffff;
464 /* Disable memory prefetch support */
465 tmp
&= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0
;
466 tmp
&= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1
;
467 cb
->bridge_control
= tmp
;
470 case (PCI_CB_MEMORY_BASE_0
>> 2):
471 cb
->mem_base0
= data
;
474 case (PCI_CB_MEMORY_LIMIT_0
>> 2):
475 cb
->mem_limit0
= data
;
478 case (PCI_CB_MEMORY_BASE_1
>> 2):
479 cb
->mem_base1
= data
;
482 case (PCI_CB_MEMORY_LIMIT_1
>> 2):
483 cb
->mem_limit1
= data
;
486 case (PCI_CB_IO_BASE_0
>> 2):
490 case (PCI_CB_IO_LIMIT_0
>> 2):
491 cb
->io_limit0
= data
;
494 case (PCI_CB_IO_BASE_1
>> 2):
498 case (PCI_CB_IO_LIMIT_1
>> 2):
499 cb
->io_limit1
= data
;
503 return PCIBIOS_SUCCESSFUL
;
506 static int bcm6348_cb_read(struct pci_bus
*bus
, unsigned int devfn
,
507 int where
, int size
, u32
*val
)
509 struct bcm6348_pci
*priv
= &bcm6348_pci
;
510 struct bcm6348_cb
*cb
= &priv
->cb
;
512 /* Snoop access to slot 0x1e on root bus, we fake a cardbus
513 * bridge at this location */
514 if (!bus
->parent
&& PCI_SLOT(devfn
) == FAKE_CB_BRIDGE_SLOT
) {
515 priv
->cb_bus
= bus
->number
;
516 return bcm6348_cb_bridge_read(where
, size
, val
);
519 /* A configuration cycle for the device behind the cardbus
520 * bridge is actually done as a type 0 cycle on the primary
521 * bus. This means that only one device can be on the cardbus
523 if (cb
->bus_assigned
&&
524 bus
->number
== cb
->cardbus_busn
&&
525 PCI_SLOT(devfn
) == 0)
526 return bcm6348_do_cfg_read(0, 0,
527 PCI_DEVFN(CARDBUS_PCI_IDSEL
, 0),
530 return PCIBIOS_DEVICE_NOT_FOUND
;
533 static int bcm6348_cb_write(struct pci_bus
*bus
, unsigned int devfn
,
534 int where
, int size
, u32 val
)
536 struct bcm6348_pci
*priv
= &bcm6348_pci
;
537 struct bcm6348_cb
*cb
= &priv
->cb
;
539 if (!bus
->parent
&& PCI_SLOT(devfn
) == FAKE_CB_BRIDGE_SLOT
) {
540 priv
->cb_bus
= bus
->number
;
541 return bcm6348_cb_bridge_write(where
, size
, val
);
544 if (cb
->bus_assigned
&&
545 bus
->number
== cb
->cardbus_busn
&&
546 PCI_SLOT(devfn
) == 0)
547 return bcm6348_do_cfg_write(0, 0,
548 PCI_DEVFN(CARDBUS_PCI_IDSEL
, 0),
551 return PCIBIOS_DEVICE_NOT_FOUND
;
554 static struct pci_ops bcm6348_cb_ops
= {
555 .read
= bcm6348_cb_read
,
556 .write
= bcm6348_cb_write
,
560 * only one IO window, so it cannot be shared by PCI and cardbus, use
561 * fixup to choose and detect unhandled configuration
563 static void bcm6348_pci_fixup(struct pci_dev
*dev
)
565 struct bcm6348_pci
*priv
= &bcm6348_pci
;
566 struct bcm6348_cb
*cb
= &priv
->cb
;
567 static int io_window
= -1;
568 int i
, found
, new_io_window
;
571 /* look for any io resource */
573 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
574 if (pci_resource_flags(dev
, i
) & IORESOURCE_IO
) {
583 /* skip our fake bus with only cardbus bridge on it */
584 if (dev
->bus
->number
== priv
->cb_bus
)
587 /* find on which bus the device is */
588 if (cb
->bus_assigned
&&
589 dev
->bus
->number
== cb
->cardbus_busn
&&
590 PCI_SLOT(dev
->devfn
) == 0)
595 if (new_io_window
== io_window
)
598 if (io_window
!= -1) {
599 pr_err("bcm63xx: both PCI and cardbus devices "
600 "need IO, which hardware cannot do\n");
604 pr_info("bcm63xx: PCI IO window assigned to %s\n",
605 (new_io_window
== 0) ? "PCI" : "cardbus");
607 val
= __raw_readl(priv
->pci
+ MPI_L2PIOREMAP_REG
);
609 val
|= MPI_L2PREMAP_IS_CARDBUS_MASK
;
611 val
&= ~MPI_L2PREMAP_IS_CARDBUS_MASK
;
612 __raw_writel(val
, priv
->pci
+ MPI_L2PIOREMAP_REG
);
614 io_window
= new_io_window
;
616 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID
, PCI_ANY_ID
, bcm6348_pci_fixup
);
618 static struct resource bcm6348_cb_io_resource
= {
619 .name
= "bcm6348 CB IO space",
620 .flags
= IORESOURCE_IO
,
622 static struct resource bcm6348_cb_mem_resource
;
624 static struct pci_controller bcm6348_cb_controller
= {
625 .pci_ops
= &bcm6348_cb_ops
,
626 .io_resource
= &bcm6348_cb_io_resource
,
627 .mem_resource
= &bcm6348_cb_mem_resource
,
629 #endif /* CONFIG_CARDBUS */
631 static void bcm6348_pci_setup(struct bcm6348_pci
*priv
)
635 /* Setup local bus to PCI access (PCI memory) */
636 val
= bcm6348_pci_mem_resource
.start
& MPI_L2P_BASE_MASK
;
637 __raw_writel(val
, priv
->pci
+ MPI_L2PMEMBASE1_REG
);
638 __raw_writel(~(resource_size(&bcm6348_pci_mem_resource
) - 1),
639 priv
->pci
+ MPI_L2PMEMRANGE1_REG
);
640 __raw_writel(val
| MPI_L2PREMAP_ENABLED_MASK
,
641 priv
->pci
+ MPI_L2PMEMREMAP1_REG
);
643 /* Set Cardbus IDSEL (type 0 cfg access on primary bus for
644 * this IDSEL will be done on Cardbus instead) */
645 val
= __raw_readl(priv
->pcmcia
+ PCMCIA_C1_REG
);
646 val
&= ~PCMCIA_C1_CBIDSEL_MASK
;
647 val
|= (CARDBUS_PCI_IDSEL
<< PCMCIA_C1_CBIDSEL_SHIFT
);
648 __raw_writel(val
, priv
->pcmcia
+ PCMCIA_C1_REG
);
650 #ifdef CONFIG_CARDBUS
651 /* setup local bus to PCI access (Cardbus memory) */
652 val
= bcm6348_cb_mem_resource
.start
& MPI_L2P_BASE_MASK
;
653 __raw_writel(val
, priv
->pci
+ MPI_L2PMEMBASE2_REG
);
654 __raw_writel(~(resource_size(&bcm6348_cb_mem_resource
) - 1),
655 priv
->pci
+ MPI_L2PMEMRANGE2_REG
);
656 val
|= MPI_L2PREMAP_ENABLED_MASK
| MPI_L2PREMAP_IS_CARDBUS_MASK
;
657 __raw_writel(val
, priv
->pci
+ MPI_L2PMEMREMAP2_REG
);
659 /* disable second access windows */
660 __raw_writel(0, priv
->pci
+ MPI_L2PMEMREMAP2_REG
);
663 /* setup local bus to PCI access (IO memory), we have only 1
664 * IO window for both PCI and cardbus, but it cannot handle
665 * both at the same time, assume standard PCI for now, if
666 * cardbus card has IO zone, PCI fixup will change window to
668 val
= bcm6348_pci_io_resource
.start
& MPI_L2P_BASE_MASK
;
669 __raw_writel(val
, priv
->pci
+ MPI_L2PIOBASE_REG
);
670 __raw_writel(~(resource_size(&bcm6348_pci_io_resource
) - 1),
671 priv
->pci
+ MPI_L2PIORANGE_REG
);
672 __raw_writel(val
| MPI_L2PREMAP_ENABLED_MASK
,
673 priv
->pci
+ MPI_L2PIOREMAP_REG
);
675 /* Enable PCI related GPIO pins */
676 __raw_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK
,
677 priv
->pci
+ MPI_LOCBUSCTL_REG
);
679 /* Setup PCI to local bus access, used by PCI device to target
680 * local RAM while bus mastering */
681 bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_3
);
683 val
= MPI_SP0_REMAP_ENABLE_MASK
;
686 __raw_writel(val
, priv
->pci
+ MPI_SP0_REMAP_REG
);
688 bcm6348_int_cfg_writel(0, PCI_BASE_ADDRESS_4
);
689 __raw_writel(0, priv
->pci
+ MPI_SP1_REMAP_REG
);
691 /* Setup sp0 range to local RAM size */
692 __raw_writel(~(memblock_phys_mem_size() - 1),
693 priv
->pci
+ MPI_SP0_RANGE_REG
);
694 __raw_writel(0, priv
->pci
+ MPI_SP1_RANGE_REG
);
696 /* Change host bridge retry counter to infinite number of
697 * retries, needed for some broadcom wifi cards with Silicon
698 * Backplane bus where access to srom seems very slow */
699 val
= bcm6348_int_cfg_readl(BCMPCI_REG_TIMERS
);
700 val
&= ~REG_TIMER_RETRY_MASK
;
701 bcm6348_int_cfg_writel(val
, BCMPCI_REG_TIMERS
);
703 /* EEnable memory decoder and bus mastering */
704 val
= bcm6348_int_cfg_readl(PCI_COMMAND
);
705 val
|= (PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
706 bcm6348_int_cfg_writel(val
, PCI_COMMAND
);
708 /* Enable read prefetching & disable byte swapping for bus
709 * mastering transfers */
710 val
= __raw_readl(priv
->pci
+ MPI_PCIMODESEL_REG
);
711 val
&= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK
;
712 val
&= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK
;
713 val
&= ~MPI_PCIMODESEL_PREFETCH_MASK
;
714 val
|= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT
);
715 __raw_writel(val
, priv
->pci
+ MPI_PCIMODESEL_REG
);
717 /* Enable pci interrupt */
718 val
= __raw_readl(priv
->pci
+ MPI_LOCINT_REG
);
719 val
|= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT
);
720 __raw_writel(val
, priv
->pci
+ MPI_LOCINT_REG
);
723 static int bcm6348_pci_probe(struct platform_device
*pdev
)
725 struct device
*dev
= &pdev
->dev
;
726 struct device_node
*np
= dev
->of_node
;
727 struct bcm6348_pci
*priv
= &bcm6348_pci
;
728 struct resource
*res
;
729 LIST_HEAD(resources
);
731 of_pci_check_probe_only();
733 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
734 priv
->pci
= devm_ioremap_resource(dev
, res
);
735 if (IS_ERR(priv
->pci
))
736 return PTR_ERR(priv
->pci
);
738 priv
->pcmcia
= priv
->pci
+ PCMCIA_OFFSET
;
740 priv
->irq
= platform_get_irq(pdev
, 0);
744 bmips_pci_irq
= priv
->irq
;
746 priv
->reset
= devm_reset_control_get(dev
, "pci");
747 if (IS_ERR(priv
->reset
))
748 return PTR_ERR(priv
->reset
);
750 priv
->remap
= of_property_read_bool(np
, "brcm,remap");
752 reset_control_reset(priv
->reset
);
754 pci_load_of_ranges(&bcm6348_pci_controller
, np
);
755 if (!bcm6348_pci_mem_resource
.start
)
758 of_pci_parse_bus_range(np
, &bcm6348_pci_busn_resource
);
759 pci_add_resource(&resources
, &bcm6348_pci_busn_resource
);
761 #ifdef CONFIG_CARDBUS
762 bcm6348_cb_io_resource
.start
= bcm6348_pci_io_resource
.start
+ (resource_size(&bcm6348_pci_io_resource
) >> 1);
763 bcm6348_cb_io_resource
.end
= bcm6348_pci_io_resource
.end
;
764 bcm6348_pci_io_resource
.end
= bcm6348_pci_io_resource
.end
- (resource_size(&bcm6348_pci_io_resource
) >> 1);
768 * Configuration accesses are done through IO space, remap 4
769 * first bytes to access it from CPU.
771 * This means that no IO access from CPU should happen while
772 * we do a configuration cycle, but there's no way we can add
773 * a spinlock for each io access, so this is currently kind of
776 priv
->io
= ioremap(bcm6348_pci_io_resource
.start
, sizeof(u32
));
780 bcm6348_pci_setup(priv
);
782 register_pci_controller(&bcm6348_pci_controller
);
784 #ifdef CONFIG_CARDBUS
786 register_pci_controller(&bcm6348_cb_controller
);
787 #endif /* CONFIG_CARDBUS */
789 /* Mark memory space used for IO mapping as reserved */
790 request_mem_region(bcm6348_pci_io_resource
.start
,
791 resource_size(&bcm6348_pci_io_resource
),
792 "BCM6348 PCI IO space");
797 static const struct of_device_id bcm6348_pci_of_match
[] = {
798 { .compatible
= "brcm,bcm6348-pci", },
801 MODULE_DEVICE_TABLE(of
, bcm6348_pci_of_match
);
803 static struct platform_driver bcm6348_pci_driver
= {
804 .probe
= bcm6348_pci_probe
,
806 .name
= "bcm6348-pci",
807 .of_match_table
= bcm6348_pci_of_match
,
810 module_platform_driver(bcm6348_pci_driver
);
812 MODULE_AUTHOR("Álvaro Fernández Rojas <noltari@gmail.com>");
813 MODULE_DESCRIPTION("BCM6348 PCI Controller Driver");
814 MODULE_LICENSE("GPL v2");
815 MODULE_ALIAS("platform:bcm6348-pci");