target/linux/bmips/files/drivers/pci/controller/pcie-bcm6318.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * BCM6318 PCIe Controller Driver
   4  *
   5  * Copyright (C) 2020 Álvaro Fernández Rojas <noltari@gmail.com>
   6  * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
   7  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/init.h>
  12 #include <linux/delay.h>
  13 #include <linux/kernel.h>
  14 #include <linux/mm.h>
  15 #include <linux/of_gpio.h>
  16 #include <linux/of_irq.h>
  17 #include <linux/of_pci.h>
  18 #include <linux/of_platform.h>
  19 #include <linux/pci.h>
  20 #include <linux/reset.h>
  21 #include <linux/types.h>
  22 #include <linux/vmalloc.h>
  23
  24 #include "../pci.h"
  25
  26 #define PCIE_BUS_BRIDGE                 0
  27 #define PCIE_BUS_DEVICE                 1
  28
  29 #define PCIE_SPECIFIC_REG               0x188
  30 #define SPECIFIC_ENDIAN_MODE_BAR1_SHIFT 0
  31 #define SPECIFIC_ENDIAN_MODE_BAR1_MASK  (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
  32 #define SPECIFIC_ENDIAN_MODE_BAR2_SHIFT 2
  33 #define SPECIFIC_ENDIAN_MODE_BAR2_MASK  (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
  34 #define SPECIFIC_ENDIAN_MODE_BAR3_SHIFT 4
  35 #define SPECIFIC_ENDIAN_MODE_BAR3_MASK  (0x3 << SPECIFIC_ENDIAN_MODE_BAR1_SHIFT)
  36 #define SPECIFIC_ENDIAN_MODE_WORD_ALIGN 0
  37 #define SPECIFIC_ENDIAN_MODE_HALFWORD_ALIGN 1
  38 #define SPECIFIC_ENDIAN_MODE_BYTE_ALIGN 2
  39
  40 #define PCIE_CONFIG2_REG                0x408
  41 #define CONFIG2_BAR1_SIZE_EN            1
  42 #define CONFIG2_BAR1_SIZE_MASK          0xf
  43
  44 #define PCIE_IDVAL3_REG                 0x43c
  45 #define IDVAL3_CLASS_CODE_MASK          0xffffff
  46 #define IDVAL3_SUBCLASS_SHIFT           8
  47 #define IDVAL3_CLASS_SHIFT              16
  48
  49 #define PCIE_DLSTATUS_REG               0x1048
  50 #define DLSTATUS_PHYLINKUP              (1 << 13)
  51
  52 #define PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG 0x400c
  53 #define C2P_MEM_WIN_ENDIAN_MODE_MASK    0x3
  54 #define C2P_MEM_WIN_ENDIAN_NO_SWAP      0
  55 #define C2P_MEM_WIN_ENDIAN_HALF_WORD_SWAP 1
  56 #define C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP 2
  57 #define C2P_MEM_WIN_BASE_ADDR_SHIFT     20
  58 #define C2P_MEM_WIN_BASE_ADDR_MASK      (0xfff << C2P_MEM_WIN_BASE_ADDR_SHIFT)
  59
  60 #define PCIE_RC_BAR1_CONFIG_LO_REG      0x402c
  61 #define RC_BAR_CFG_LO_SIZE_256MB        0xd
  62 #define RC_BAR_CFG_LO_MATCH_ADDR_SHIFT  20
  63 #define RC_BAR_CFG_LO_MATCH_ADDR_MASK   (0xfff << RC_BAR_CFG_LO_MATCH_ADDR_SHIFT)
  64
  65 #define PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG 0x4070
  66 #define C2P_BASELIMIT_LIMIT_SHIFT       20
  67 #define C2P_BASELIMIT_LIMIT_MASK        (0xfff << C2P_BASELIMIT_LIMIT_SHIFT)
  68 #define C2P_BASELIMIT_BASE_SHIFT        4
  69 #define C2P_BASELIMIT_BASE_MASK         (0xfff << C2P_BASELIMIT_BASE_SHIFT)
  70
  71 #define PCIE_UBUS_BAR1_CFG_REMAP_REG    0x4088
  72 #define BAR1_CFG_REMAP_OFFSET_SHIFT     20
  73 #define BAR1_CFG_REMAP_OFFSET_MASK      (0xfff << BAR1_CFG_REMAP_OFFSET_SHIFT)
  74 #define BAR1_CFG_REMAP_ACCESS_EN        1
  75
  76 #define PCIE_HARD_DEBUG_REG             0x4204
  77 #define HARD_DEBUG_SERDES_IDDQ          (1 << 23)
  78
  79 #define PCIE_CPU_INT1_MASK_CLEAR_REG    0x830c
  80 #define CPU_INT_PCIE_ERR_ATTN_CPU       (1 << 0)
  81 #define CPU_INT_PCIE_INTA               (1 << 1)
  82 #define CPU_INT_PCIE_INTB               (1 << 2)
  83 #define CPU_INT_PCIE_INTC               (1 << 3)
  84 #define CPU_INT_PCIE_INTD               (1 << 4)
  85 #define CPU_INT_PCIE_INTR               (1 << 5)
  86 #define CPU_INT_PCIE_NMI                (1 << 6)
  87 #define CPU_INT_PCIE_UBUS               (1 << 7)
  88 #define CPU_INT_IPI                     (1 << 8)
  89
  90 #define PCIE_EXT_CFG_INDEX_REG          0x8400
  91 #define EXT_CFG_FUNC_NUM_SHIFT          12
  92 #define EXT_CFG_FUNC_NUM_MASK           (0x7 << EXT_CFG_FUNC_NUM_SHIFT)
  93 #define EXT_CFG_DEV_NUM_SHIFT           15
  94 #define EXT_CFG_DEV_NUM_MASK            (0xf << EXT_CFG_DEV_NUM_SHIFT)
  95 #define EXT_CFG_BUS_NUM_SHIFT           20
  96 #define EXT_CFG_BUS_NUM_MASK            (0xff << EXT_CFG_BUS_NUM_SHIFT)
  97
  98 #define PCIE_DEVICE_OFFSET              0x9000
  99
 100 struct bcm6318_pcie {
 101         void __iomem *base;
 102         int irq;
 103         struct clk *clk;
 104         struct clk *clk25;
 105         struct clk *clk_ubus;
 106         struct reset_control *reset;
 107         struct reset_control *reset_ext;
 108         struct reset_control *reset_core;
 109         struct reset_control *reset_hard;
 110 };
 111
 112 static struct bcm6318_pcie bcm6318_pcie;
 113
 114 extern int bmips_pci_irq;
 115
 116 /*
 117  * swizzle 32bits data to return only the needed part
 118  */
 119 static int postprocess_read(u32 data, int where, unsigned int size)
 120 {
 121         u32 ret = 0;
 122
 123         switch (size) {
 124         case 1:
 125                 ret = (data >> ((where & 3) << 3)) & 0xff;
 126                 break;
 127         case 2:
 128                 ret = (data >> ((where & 3) << 3)) & 0xffff;
 129                 break;
 130         case 4:
 131                 ret = data;
 132                 break;
 133         }
 134
 135         return ret;
 136 }
 137
 138 static int preprocess_write(u32 orig_data, u32 val, int where,
 139                             unsigned int size)
 140 {
 141         u32 ret = 0;
 142
 143         switch (size) {
 144         case 1:
 145                 ret = (orig_data & ~(0xff << ((where & 3) << 3))) |
 146                         (val << ((where & 3) << 3));
 147                 break;
 148         case 2:
 149                 ret = (orig_data & ~(0xffff << ((where & 3) << 3))) |
 150                         (val << ((where & 3) << 3));
 151                 break;
 152         case 4:
 153                 ret = val;
 154                 break;
 155         }
 156
 157         return ret;
 158 }
 159
 160 static int bcm6318_pcie_can_access(struct pci_bus *bus, int devfn)
 161 {
 162         struct bcm6318_pcie *priv = &bcm6318_pcie;
 163
 164         switch (bus->number) {
 165         case PCIE_BUS_BRIDGE:
 166                 return PCI_SLOT(devfn) == 0;
 167         case PCIE_BUS_DEVICE:
 168                 if (PCI_SLOT(devfn) == 0)
 169                         return __raw_readl(priv->base + PCIE_DLSTATUS_REG)
 170                                         & DLSTATUS_PHYLINKUP;
 171                 /* else, fall through */
 172         default:
 173                 return false;
 174         }
 175 }
 176
 177 static int bcm6318_pcie_read(struct pci_bus *bus, unsigned int devfn,
 178                              int where, int size, u32 *val)
 179 {
 180         struct bcm6318_pcie *priv = &bcm6318_pcie;
 181         u32 data;
 182         u32 reg = where & ~3;
 183
 184         if (!bcm6318_pcie_can_access(bus, devfn))
 185                 return PCIBIOS_DEVICE_NOT_FOUND;
 186
 187         if (bus->number == PCIE_BUS_DEVICE)
 188                 reg += PCIE_DEVICE_OFFSET;
 189
 190         data = __raw_readl(priv->base + reg);
 191         *val = postprocess_read(data, where, size);
 192
 193         return PCIBIOS_SUCCESSFUL;
 194 }
 195
 196 static int bcm6318_pcie_write(struct pci_bus *bus, unsigned int devfn,
 197                               int where, int size, u32 val)
 198 {
 199         struct bcm6318_pcie *priv = &bcm6318_pcie;
 200         u32 data;
 201         u32 reg = where & ~3;
 202
 203         if (!bcm6318_pcie_can_access(bus, devfn))
 204                 return PCIBIOS_DEVICE_NOT_FOUND;
 205
 206         if (bus->number == PCIE_BUS_DEVICE)
 207                 reg += PCIE_DEVICE_OFFSET;
 208
 209         data = __raw_readl(priv->base + reg);
 210         data = preprocess_write(data, val, where, size);
 211         __raw_writel(data, priv->base + reg);
 212
 213         return PCIBIOS_SUCCESSFUL;
 214 }
 215
 216 static struct pci_ops bcm6318_pcie_ops = {
 217         .read = bcm6318_pcie_read,
 218         .write = bcm6318_pcie_write,
 219 };
 220
 221 static struct resource bcm6318_pcie_io_resource;
 222 static struct resource bcm6318_pcie_mem_resource;
 223 static struct resource bcm6318_pcie_busn_resource;
 224
 225 static struct pci_controller bcm6318_pcie_controller = {
 226         .pci_ops = &bcm6318_pcie_ops,
 227         .io_resource = &bcm6318_pcie_io_resource,
 228         .mem_resource = &bcm6318_pcie_mem_resource,
 229         .busn_resource = &bcm6318_pcie_busn_resource,
 230 };
 231
 232 static void bcm6318_pcie_reset(struct bcm6318_pcie *priv)
 233 {
 234         u32 val;
 235
 236         reset_control_deassert(priv->reset_hard);
 237
 238         reset_control_assert(priv->reset);
 239         reset_control_assert(priv->reset_core);
 240         reset_control_assert(priv->reset_ext);
 241         mdelay(10);
 242
 243         reset_control_deassert(priv->reset_ext);
 244         mdelay(10);
 245
 246         reset_control_deassert(priv->reset);
 247         mdelay(10);
 248
 249         val = __raw_readl(priv->base + PCIE_HARD_DEBUG_REG);
 250         val &= ~HARD_DEBUG_SERDES_IDDQ;
 251         __raw_writel(val, priv->base + PCIE_HARD_DEBUG_REG);
 252         mdelay(10);
 253
 254         reset_control_deassert(priv->reset_core);
 255         mdelay(200);
 256 }
 257
 258 static void bcm6318_pcie_setup(struct bcm6318_pcie *priv)
 259 {
 260         u32 val;
 261
 262         __raw_writel(CPU_INT_PCIE_INTA | CPU_INT_PCIE_INTB |
 263                      CPU_INT_PCIE_INTC | CPU_INT_PCIE_INTD,
 264                      priv->base + PCIE_CPU_INT1_MASK_CLEAR_REG);
 265
 266         val = bcm6318_pcie_mem_resource.end & C2P_BASELIMIT_LIMIT_MASK;
 267         val |= (bcm6318_pcie_mem_resource.start >> C2P_BASELIMIT_LIMIT_SHIFT)
 268                << C2P_BASELIMIT_BASE_SHIFT;
 269         __raw_writel(val, priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_BASELIMIT_REG);
 270
 271         /* setup class code as bridge */
 272         val = __raw_readl(priv->base + PCIE_IDVAL3_REG);
 273         val &= ~IDVAL3_CLASS_CODE_MASK;
 274         val |= (PCI_CLASS_BRIDGE_PCI << IDVAL3_SUBCLASS_SHIFT);
 275         __raw_writel(val, priv->base + PCIE_IDVAL3_REG);
 276
 277         /* disable bar1 size */
 278         val = __raw_readl(priv->base + PCIE_CONFIG2_REG);
 279         val &= ~CONFIG2_BAR1_SIZE_MASK;
 280         __raw_writel(val, priv->base + PCIE_CONFIG2_REG);
 281
 282         /* set bar0 to little endian */
 283         val = __raw_readl(priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
 284         val |= bcm6318_pcie_mem_resource.start & C2P_MEM_WIN_BASE_ADDR_MASK;
 285         val |= C2P_MEM_WIN_ENDIAN_HALF_BYTE_SWAP;
 286         __raw_writel(val, priv->base + PCIE_CPU_2_PCIE_MEM_WIN0_LO_REG);
 287
 288         __raw_writel(SPECIFIC_ENDIAN_MODE_BYTE_ALIGN,
 289                      priv->base + PCIE_SPECIFIC_REG);
 290
 291         __raw_writel(RC_BAR_CFG_LO_SIZE_256MB,
 292                      priv->base + PCIE_RC_BAR1_CONFIG_LO_REG);
 293
 294         __raw_writel(BAR1_CFG_REMAP_ACCESS_EN,
 295                      priv->base + PCIE_UBUS_BAR1_CFG_REMAP_REG);
 296
 297         __raw_writel(PCIE_BUS_DEVICE << EXT_CFG_BUS_NUM_SHIFT,
 298                      priv->base + PCIE_EXT_CFG_INDEX_REG);
 299 }
 300
 301 static int bcm6318_pcie_probe(struct platform_device *pdev)
 302 {
 303         struct device *dev = &pdev->dev;
 304         struct device_node *np = dev->of_node;
 305         struct bcm6318_pcie *priv = &bcm6318_pcie;
 306         struct resource *res;
 307         int ret;
 308
 309         of_pci_check_probe_only();
 310
 311         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 312         priv->base = devm_ioremap_resource(dev, res);
 313         if (IS_ERR(priv->base))
 314                 return PTR_ERR(priv->base);
 315
 316         priv->irq = platform_get_irq(pdev, 0);
 317         if (!priv->irq)
 318                 return -ENODEV;
 319
 320         bmips_pci_irq = priv->irq;
 321
 322         priv->reset = devm_reset_control_get(dev, "pcie");
 323         if (IS_ERR(priv->reset))
 324                 return PTR_ERR(priv->reset);
 325
 326         priv->reset_ext = devm_reset_control_get(dev, "pcie-ext");
 327         if (IS_ERR(priv->reset_ext))
 328                 return PTR_ERR(priv->reset_ext);
 329
 330         priv->reset_core = devm_reset_control_get(dev, "pcie-core");
 331         if (IS_ERR(priv->reset_core))
 332                 return PTR_ERR(priv->reset_core);
 333
 334         priv->reset_hard = devm_reset_control_get(dev, "pcie-hard");
 335         if (IS_ERR(priv->reset_hard))
 336                 return PTR_ERR(priv->reset_hard);
 337
 338         priv->clk = devm_clk_get(dev, "pcie");
 339         if (IS_ERR(priv->clk))
 340                 return PTR_ERR(priv->clk);
 341
 342         priv->clk25 = devm_clk_get(dev, "pcie25");
 343         if (IS_ERR(priv->clk25))
 344                 return PTR_ERR(priv->clk25);
 345
 346         priv->clk_ubus = devm_clk_get(dev, "pcie-ubus");
 347         if (IS_ERR(priv->clk_ubus))
 348                 return PTR_ERR(priv->clk_ubus);
 349
 350         ret = clk_prepare_enable(priv->clk);
 351         if (ret) {
 352                 dev_err(dev, "could not enable clock\n");
 353                 return ret;
 354         }
 355
 356         ret = clk_prepare_enable(priv->clk25);
 357         if (ret) {
 358                 dev_err(dev, "could not enable clock\n");
 359                 return ret;
 360         }
 361
 362         ret = clk_prepare_enable(priv->clk_ubus);
 363         if (ret) {
 364                 dev_err(dev, "could not enable clock\n");
 365                 return ret;
 366         }
 367
 368         pci_load_of_ranges(&bcm6318_pcie_controller, np);
 369         if (!bcm6318_pcie_mem_resource.start)
 370                 return -EINVAL;
 371
 372         of_pci_parse_bus_range(np, &bcm6318_pcie_busn_resource);
 373
 374         bcm6318_pcie_reset(priv);
 375         bcm6318_pcie_setup(priv);
 376
 377         register_pci_controller(&bcm6318_pcie_controller);
 378
 379         return 0;
 380 }
 381
 382 static const struct of_device_id bcm6318_pcie_of_match[] = {
 383         { .compatible = "brcm,bcm6318-pcie", },
 384         { /* sentinel */ }
 385 };
 386
 387 static struct platform_driver bcm6318_pcie_driver = {
 388         .probe = bcm6318_pcie_probe,
 389         .driver = {
 390                 .name = "bcm6318-pcie",
 391                 .of_match_table = bcm6318_pcie_of_match,
 392         },
 393 };
 394
 395 int __init bcm6318_pcie_init(void)
 396 {
 397         int ret = platform_driver_register(&bcm6318_pcie_driver);
 398         if (ret)
 399                 pr_err("pci-bcm6318: Error registering platform driver!\n");
 400         return ret;
 401 }
 402 late_initcall_sync(bcm6318_pcie_init);