target/linux/bmips/patches-5.10/066-v5.13-dt-bindings-add-BCM6368-GPIO-sysctl-binding-document.patch

   1 From fd22635f222f44dcb4dd6382d97de13144edad2b Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
   3 Date: Wed, 24 Mar 2021 09:19:16 +0100
   4 Subject: [PATCH 15/22] dt-bindings: add BCM6368 GPIO sysctl binding
   5  documentation
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Add binding documentation for the GPIO sysctl found in BCM6368 SoCs.
  11
  12 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
  13 Reviewed-by: Rob Herring <robh@kernel.org>
  14 Link: https://lore.kernel.org/r/20210324081923.20379-16-noltari@gmail.com
  15 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  16 ---
  17  .../mfd/brcm,bcm6368-gpio-sysctl.yaml         | 246 ++++++++++++++++++
  18  1 file changed, 246 insertions(+)
  19  create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml
  20
  21 --- /dev/null
  22 +++ b/Documentation/devicetree/bindings/mfd/brcm,bcm6368-gpio-sysctl.yaml
  23 @@ -0,0 +1,246 @@
  24 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  25 +%YAML 1.2
  26 +---
  27 +$id: http://devicetree.org/schemas/mfd/brcm,bcm6368-gpio-sysctl.yaml#
  28 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  29 +
  30 +title: Broadcom BCM6368 GPIO System Controller Device Tree Bindings
  31 +
  32 +maintainers:
  33 +  - Álvaro Fernández Rojas <noltari@gmail.com>
  34 +  - Jonas Gorski <jonas.gorski@gmail.com>
  35 +
  36 +description:
  37 +  Broadcom BCM6368 SoC GPIO system controller which provides a register map
  38 +  for controlling the GPIO and pins of the SoC.
  39 +
  40 +properties:
  41 +  "#address-cells": true
  42 +
  43 +  "#size-cells": true
  44 +
  45 +  compatible:
  46 +    items:
  47 +      - const: brcm,bcm6368-gpio-sysctl
  48 +      - const: syscon
  49 +      - const: simple-mfd
  50 +
  51 +  ranges:
  52 +    maxItems: 1
  53 +
  54 +  reg:
  55 +    maxItems: 1
  56 +
  57 +patternProperties:
  58 +  "^gpio@[0-9a-f]+$":
  59 +    # Child node
  60 +    type: object
  61 +    $ref: "../gpio/brcm,bcm6345-gpio.yaml"
  62 +    description:
  63 +      GPIO controller for the SoC GPIOs. This child node definition
  64 +      should follow the bindings specified in
  65 +      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
  66 +
  67 +  "^pinctrl@[0-9a-f]+$":
  68 +    # Child node
  69 +    type: object
  70 +    $ref: "../pinctrl/brcm,bcm6368-pinctrl.yaml"
  71 +    description:
  72 +      Pin controller for the SoC pins. This child node definition
  73 +      should follow the bindings specified in
  74 +      Documentation/devicetree/bindings/pinctrl/brcm,bcm6368-pinctrl.yaml.
  75 +
  76 +required:
  77 +  - "#address-cells"
  78 +  - compatible
  79 +  - ranges
  80 +  - reg
  81 +  - "#size-cells"
  82 +
  83 +additionalProperties: false
  84 +
  85 +examples:
  86 +  - |
  87 +    syscon@10000080 {
  88 +      #address-cells = <1>;
  89 +      #size-cells = <1>;
  90 +      compatible = "brcm,bcm6368-gpio-sysctl", "syscon", "simple-mfd";
  91 +      reg = <0x10000080 0x80>;
  92 +      ranges = <0 0x10000080 0x80>;
  93 +
  94 +      gpio@0 {
  95 +        compatible = "brcm,bcm6368-gpio";
  96 +        reg-names = "dirout", "dat";
  97 +        reg = <0x0 0x8>, <0x8 0x8>;
  98 +
  99 +        gpio-controller;
 100 +        gpio-ranges = <&pinctrl 0 0 38>;
 101 +        #gpio-cells = <2>;
 102 +      };
 103 +
 104 +      pinctrl: pinctrl@18 {
 105 +        compatible = "brcm,bcm6368-pinctrl";
 106 +        reg = <0x18 0x4>, <0x38 0x4>;
 107 +
 108 +        pinctrl_analog_afe_0: analog_afe_0-pins {
 109 +          function = "analog_afe_0";
 110 +          pins = "gpio0";
 111 +        };
 112 +
 113 +        pinctrl_analog_afe_1: analog_afe_1-pins {
 114 +          function = "analog_afe_1";
 115 +          pins = "gpio1";
 116 +        };
 117 +
 118 +        pinctrl_sys_irq: sys_irq-pins {
 119 +          function = "sys_irq";
 120 +          pins = "gpio2";
 121 +        };
 122 +
 123 +        pinctrl_serial_led: serial_led-pins {
 124 +          pinctrl_serial_led_data: serial_led_data-pins {
 125 +            function = "serial_led_data";
 126 +            pins = "gpio3";
 127 +          };
 128 +
 129 +          pinctrl_serial_led_clk: serial_led_clk-pins {
 130 +            function = "serial_led_clk";
 131 +            pins = "gpio4";
 132 +          };
 133 +        };
 134 +
 135 +        pinctrl_inet_led: inet_led-pins {
 136 +          function = "inet_led";
 137 +          pins = "gpio5";
 138 +        };
 139 +
 140 +        pinctrl_ephy0_led: ephy0_led-pins {
 141 +          function = "ephy0_led";
 142 +          pins = "gpio6";
 143 +        };
 144 +
 145 +        pinctrl_ephy1_led: ephy1_led-pins {
 146 +          function = "ephy1_led";
 147 +          pins = "gpio7";
 148 +        };
 149 +
 150 +        pinctrl_ephy2_led: ephy2_led-pins {
 151 +          function = "ephy2_led";
 152 +          pins = "gpio8";
 153 +        };
 154 +
 155 +        pinctrl_ephy3_led: ephy3_led-pins {
 156 +          function = "ephy3_led";
 157 +          pins = "gpio9";
 158 +        };
 159 +
 160 +        pinctrl_robosw_led_data: robosw_led_data-pins {
 161 +          function = "robosw_led_data";
 162 +          pins = "gpio10";
 163 +        };
 164 +
 165 +        pinctrl_robosw_led_clk: robosw_led_clk-pins {
 166 +          function = "robosw_led_clk";
 167 +          pins = "gpio11";
 168 +        };
 169 +
 170 +        pinctrl_robosw_led0: robosw_led0-pins {
 171 +          function = "robosw_led0";
 172 +          pins = "gpio12";
 173 +        };
 174 +
 175 +        pinctrl_robosw_led1: robosw_led1-pins {
 176 +          function = "robosw_led1";
 177 +          pins = "gpio13";
 178 +        };
 179 +
 180 +        pinctrl_usb_device_led: usb_device_led-pins {
 181 +          function = "usb_device_led";
 182 +          pins = "gpio14";
 183 +        };
 184 +
 185 +        pinctrl_pci: pci-pins {
 186 +          pinctrl_pci_req1: pci_req1-pins {
 187 +            function = "pci_req1";
 188 +            pins = "gpio16";
 189 +          };
 190 +
 191 +          pinctrl_pci_gnt1: pci_gnt1-pins {
 192 +            function = "pci_gnt1";
 193 +            pins = "gpio17";
 194 +          };
 195 +
 196 +          pinctrl_pci_intb: pci_intb-pins {
 197 +            function = "pci_intb";
 198 +            pins = "gpio18";
 199 +          };
 200 +
 201 +          pinctrl_pci_req0: pci_req0-pins {
 202 +            function = "pci_req0";
 203 +            pins = "gpio19";
 204 +          };
 205 +
 206 +          pinctrl_pci_gnt0: pci_gnt0-pins {
 207 +            function = "pci_gnt0";
 208 +            pins = "gpio20";
 209 +          };
 210 +        };
 211 +
 212 +        pinctrl_pcmcia: pcmcia-pins {
 213 +          pinctrl_pcmcia_cd1: pcmcia_cd1-pins {
 214 +            function = "pcmcia_cd1";
 215 +            pins = "gpio22";
 216 +          };
 217 +
 218 +          pinctrl_pcmcia_cd2: pcmcia_cd2-pins {
 219 +            function = "pcmcia_cd2";
 220 +            pins = "gpio23";
 221 +          };
 222 +
 223 +          pinctrl_pcmcia_vs1: pcmcia_vs1-pins {
 224 +            function = "pcmcia_vs1";
 225 +            pins = "gpio24";
 226 +          };
 227 +
 228 +          pinctrl_pcmcia_vs2: pcmcia_vs2-pins {
 229 +            function = "pcmcia_vs2";
 230 +            pins = "gpio25";
 231 +          };
 232 +        };
 233 +
 234 +        pinctrl_ebi_cs2: ebi_cs2-pins {
 235 +          function = "ebi_cs2";
 236 +          pins = "gpio26";
 237 +        };
 238 +
 239 +        pinctrl_ebi_cs3: ebi_cs3-pins {
 240 +          function = "ebi_cs3";
 241 +          pins = "gpio27";
 242 +        };
 243 +
 244 +        pinctrl_spi_cs2: spi_cs2-pins {
 245 +          function = "spi_cs2";
 246 +          pins = "gpio28";
 247 +        };
 248 +
 249 +        pinctrl_spi_cs3: spi_cs3-pins {
 250 +          function = "spi_cs3";
 251 +          pins = "gpio29";
 252 +        };
 253 +
 254 +        pinctrl_spi_cs4: spi_cs4-pins {
 255 +          function = "spi_cs4";
 256 +          pins = "gpio30";
 257 +        };
 258 +
 259 +        pinctrl_spi_cs5: spi_cs5-pins {
 260 +          function = "spi_cs5";
 261 +          pins = "gpio31";
 262 +        };
 263 +
 264 +        pinctrl_uart1: uart1-pins {
 265 +          function = "uart1";
 266 +          group = "uart1_grp";
 267 +        };
 268 +      };
 269 +    };