target/linux/bmips/patches-5.10/069-v5.13-dt-bindings-add-BCM63268-GPIO-sysctl-binding-documen.patch

   1 From ff8324355d7ae2e4ebbd304de27bb5fa75e20c6a Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
   3 Date: Wed, 24 Mar 2021 09:19:19 +0100
   4 Subject: [PATCH 18/22] dt-bindings: add BCM63268 GPIO sysctl binding
   5  documentation
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 Add binding documentation for the GPIO sysctl found in BCM63268 SoCs.
  11
  12 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
  13 Reviewed-by: Rob Herring <robh@kernel.org>
  14 Link: https://lore.kernel.org/r/20210324081923.20379-19-noltari@gmail.com
  15 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  16 ---
  17  .../mfd/brcm,bcm63268-gpio-sysctl.yaml        | 194 ++++++++++++++++++
  18  1 file changed, 194 insertions(+)
  19  create mode 100644 Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml
  20
  21 --- /dev/null
  22 +++ b/Documentation/devicetree/bindings/mfd/brcm,bcm63268-gpio-sysctl.yaml
  23 @@ -0,0 +1,194 @@
  24 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  25 +%YAML 1.2
  26 +---
  27 +$id: http://devicetree.org/schemas/mfd/brcm,bcm63268-gpio-sysctl.yaml#
  28 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  29 +
  30 +title: Broadcom BCM63268 GPIO System Controller Device Tree Bindings
  31 +
  32 +maintainers:
  33 +  - Álvaro Fernández Rojas <noltari@gmail.com>
  34 +  - Jonas Gorski <jonas.gorski@gmail.com>
  35 +
  36 +description:
  37 +  Broadcom BCM63268 SoC GPIO system controller which provides a register map
  38 +  for controlling the GPIO and pins of the SoC.
  39 +
  40 +properties:
  41 +  "#address-cells": true
  42 +
  43 +  "#size-cells": true
  44 +
  45 +  compatible:
  46 +    items:
  47 +      - const: brcm,bcm63268-gpio-sysctl
  48 +      - const: syscon
  49 +      - const: simple-mfd
  50 +
  51 +  ranges:
  52 +    maxItems: 1
  53 +
  54 +  reg:
  55 +    maxItems: 1
  56 +
  57 +patternProperties:
  58 +  "^gpio@[0-9a-f]+$":
  59 +    # Child node
  60 +    type: object
  61 +    $ref: "../gpio/brcm,bcm6345-gpio.yaml"
  62 +    description:
  63 +      GPIO controller for the SoC GPIOs. This child node definition
  64 +      should follow the bindings specified in
  65 +      Documentation/devicetree/bindings/gpio/brcm,bcm6345-gpio.yaml.
  66 +
  67 +  "^pinctrl@[0-9a-f]+$":
  68 +    # Child node
  69 +    type: object
  70 +    $ref: "../pinctrl/brcm,bcm63268-pinctrl.yaml"
  71 +    description:
  72 +      Pin controller for the SoC pins. This child node definition
  73 +      should follow the bindings specified in
  74 +      Documentation/devicetree/bindings/pinctrl/brcm,bcm63268-pinctrl.yaml.
  75 +
  76 +required:
  77 +  - "#address-cells"
  78 +  - compatible
  79 +  - ranges
  80 +  - reg
  81 +  - "#size-cells"
  82 +
  83 +additionalProperties: false
  84 +
  85 +examples:
  86 +  - |
  87 +    syscon@100000c0 {
  88 +      #address-cells = <1>;
  89 +      #size-cells = <1>;
  90 +      compatible = "brcm,bcm63268-gpio-sysctl", "syscon", "simple-mfd";
  91 +      reg = <0x100000c0 0x80>;
  92 +      ranges = <0 0x100000c0 0x80>;
  93 +
  94 +      gpio@0 {
  95 +        compatible = "brcm,bcm63268-gpio";
  96 +        reg-names = "dirout", "dat";
  97 +        reg = <0x0 0x8>, <0x8 0x8>;
  98 +
  99 +        gpio-controller;
 100 +        gpio-ranges = <&pinctrl 0 0 52>;
 101 +        #gpio-cells = <2>;
 102 +      };
 103 +
 104 +      pinctrl: pinctrl@10 {
 105 +        compatible = "brcm,bcm63268-pinctrl";
 106 +        reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
 107 +
 108 +        pinctrl_serial_led: serial_led-pins {
 109 +          pinctrl_serial_led_clk: serial_led_clk-pins {
 110 +            function = "serial_led_clk";
 111 +            pins = "gpio0";
 112 +          };
 113 +
 114 +          pinctrl_serial_led_data: serial_led_data-pins {
 115 +            function = "serial_led_data";
 116 +            pins = "gpio1";
 117 +          };
 118 +        };
 119 +
 120 +        pinctrl_hsspi_cs4: hsspi_cs4-pins {
 121 +          function = "hsspi_cs4";
 122 +          pins = "gpio16";
 123 +        };
 124 +
 125 +        pinctrl_hsspi_cs5: hsspi_cs5-pins {
 126 +          function = "hsspi_cs5";
 127 +          pins = "gpio17";
 128 +        };
 129 +
 130 +        pinctrl_hsspi_cs6: hsspi_cs6-pins {
 131 +          function = "hsspi_cs6";
 132 +          pins = "gpio8";
 133 +        };
 134 +
 135 +        pinctrl_hsspi_cs7: hsspi_cs7-pins {
 136 +          function = "hsspi_cs7";
 137 +          pins = "gpio9";
 138 +        };
 139 +
 140 +        pinctrl_adsl_spi: adsl_spi-pins {
 141 +          pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
 142 +            function = "adsl_spi_miso";
 143 +            pins = "gpio18";
 144 +          };
 145 +
 146 +          pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
 147 +            function = "adsl_spi_mosi";
 148 +            pins = "gpio19";
 149 +          };
 150 +        };
 151 +
 152 +        pinctrl_vreq_clk: vreq_clk-pins {
 153 +          function = "vreq_clk";
 154 +          pins = "gpio22";
 155 +        };
 156 +
 157 +        pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
 158 +          function = "pcie_clkreq_b";
 159 +          pins = "gpio23";
 160 +        };
 161 +
 162 +        pinctrl_robosw_led_clk: robosw_led_clk-pins {
 163 +          function = "robosw_led_clk";
 164 +          pins = "gpio30";
 165 +        };
 166 +
 167 +        pinctrl_robosw_led_data: robosw_led_data-pins {
 168 +          function = "robosw_led_data";
 169 +          pins = "gpio31";
 170 +        };
 171 +
 172 +        pinctrl_nand: nand-pins {
 173 +          function = "nand";
 174 +          group = "nand_grp";
 175 +        };
 176 +
 177 +        pinctrl_gpio35_alt: gpio35_alt-pins {
 178 +          function = "gpio35_alt";
 179 +          pin = "gpio35";
 180 +        };
 181 +
 182 +        pinctrl_dectpd: dectpd-pins {
 183 +          function = "dectpd";
 184 +          group = "dectpd_grp";
 185 +        };
 186 +
 187 +        pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
 188 +          function = "vdsl_phy_override_0";
 189 +          group = "vdsl_phy_override_0_grp";
 190 +        };
 191 +
 192 +        pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
 193 +          function = "vdsl_phy_override_1";
 194 +          group = "vdsl_phy_override_1_grp";
 195 +        };
 196 +
 197 +        pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
 198 +          function = "vdsl_phy_override_2";
 199 +          group = "vdsl_phy_override_2_grp";
 200 +        };
 201 +
 202 +        pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
 203 +          function = "vdsl_phy_override_3";
 204 +          group = "vdsl_phy_override_3_grp";
 205 +        };
 206 +
 207 +        pinctrl_dsl_gpio8: dsl_gpio8-pins {
 208 +          function = "dsl_gpio8";
 209 +          group = "dsl_gpio8";
 210 +        };
 211 +
 212 +        pinctrl_dsl_gpio9: dsl_gpio9-pins {
 213 +          function = "dsl_gpio9";
 214 +          group = "dsl_gpio9";
 215 +        };
 216 +      };
 217 +    };