target/linux/bmips/patches-5.15/113-clk-bcm-Add-BCM63268-timer-clock-and-reset-driver.patch

   1 From 3c8dd9d0937a19f3f20f28ba0b0b64f448d50dd4 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
   3 Date: Thu, 25 Feb 2021 19:54:04 +0100
   4 Subject: [PATCH 4/4] clk: bcm: Add BCM63268 timer clock and reset driver
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Add driver for BCM63268 timer clock and reset controller.
  10
  11 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
  12 ---
  13  drivers/clk/bcm/Kconfig              |   9 ++
  14  drivers/clk/bcm/Makefile             |   1 +
  15  drivers/clk/bcm/clk-bcm63268-timer.c | 232 +++++++++++++++++++++++++++
  16  3 files changed, 242 insertions(+)
  17  create mode 100644 drivers/clk/bcm/clk-bcm63268-timer.c
  18
  19 --- a/drivers/clk/bcm/Kconfig
  20 +++ b/drivers/clk/bcm/Kconfig
  21 @@ -37,6 +37,15 @@ config CLK_BCM_63XX_GATE
  22           Enable common clock framework support for Broadcom BCM63xx DSL SoCs
  23           based on the MIPS architecture
  24
  25 +config CLK_BCM63268_TIMER
  26 +       bool "Broadcom BCM63268 timer clock and reset support"
  27 +       depends on BMIPS_GENERIC || COMPILE_TEST
  28 +       default BMIPS_GENERIC
  29 +       select RESET_CONTROLLER
  30 +       help
  31 +         Enable timer clock and reset support for Broadcom BCM63268 DSL SoCs
  32 +         based on the MIPS architecture.
  33 +
  34  config CLK_BCM_KONA
  35         bool "Broadcom Kona CCU clock support"
  36         depends on ARCH_BCM_MOBILE || COMPILE_TEST
  37 --- a/drivers/clk/bcm/Makefile
  38 +++ b/drivers/clk/bcm/Makefile
  39 @@ -1,6 +1,7 @@
  40  # SPDX-License-Identifier: GPL-2.0
  41  obj-$(CONFIG_CLK_BCM_63XX)     += clk-bcm63xx.o
  42  obj-$(CONFIG_CLK_BCM_63XX_GATE)        += clk-bcm63xx-gate.o
  43 +obj-$(CONFIG_CLK_BCM63268_TIMER) += clk-bcm63268-timer.o
  44  obj-$(CONFIG_CLK_BCM_KONA)     += clk-kona.o
  45  obj-$(CONFIG_CLK_BCM_KONA)     += clk-kona-setup.o
  46  obj-$(CONFIG_CLK_BCM_KONA)     += clk-bcm281xx.o
  47 --- /dev/null
  48 +++ b/drivers/clk/bcm/clk-bcm63268-timer.c
  49 @@ -0,0 +1,232 @@
  50 +// SPDX-License-Identifier: GPL-2.0
  51 +/*
  52 + * BCM63268 Timer Clock and Reset Controller Driver
  53 + *
  54 + * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
  55 + */
  56 +
  57 +#include <linux/clk-provider.h>
  58 +#include <linux/delay.h>
  59 +#include <linux/init.h>
  60 +#include <linux/of.h>
  61 +#include <linux/of_device.h>
  62 +#include <linux/platform_device.h>
  63 +#include <linux/reset-controller.h>
  64 +
  65 +#include <dt-bindings/clock/bcm63268-clock.h>
  66 +
  67 +#define BCM63268_TIMER_RESET_SLEEP_MIN_US      10000
  68 +#define BCM63268_TIMER_RESET_SLEEP_MAX_US      20000
  69 +
  70 +struct bcm63268_tclkrst_hw {
  71 +       void __iomem *regs;
  72 +       spinlock_t lock;
  73 +
  74 +       struct reset_controller_dev rcdev;
  75 +       struct clk_hw_onecell_data data;
  76 +};
  77 +
  78 +struct bcm63268_tclk_table_entry {
  79 +       const char * const name;
  80 +       u8 bit;
  81 +       unsigned long flags;
  82 +};
  83 +
  84 +static const struct bcm63268_tclk_table_entry bcm63268_timer_clocks[] = {
  85 +       {
  86 +               .name = "ephy1",
  87 +               .bit = BCM63268_TCLK_EPHY1,
  88 +       }, {
  89 +               .name = "ephy2",
  90 +               .bit = BCM63268_TCLK_EPHY2,
  91 +       }, {
  92 +               .name = "ephy3",
  93 +               .bit = BCM63268_TCLK_EPHY3,
  94 +       }, {
  95 +               .name = "gphy1",
  96 +               .bit = BCM63268_TCLK_GPHY1,
  97 +       }, {
  98 +               .name = "dsl",
  99 +               .bit = BCM63268_TCLK_DSL,
 100 +       }, {
 101 +               .name = "wakeon_ephy",
 102 +               .bit = BCM63268_TCLK_WAKEON_EPHY,
 103 +       }, {
 104 +               .name = "wakeon_dsl",
 105 +               .bit = BCM63268_TCLK_WAKEON_DSL,
 106 +       }, {
 107 +               .name = "fap1_pll",
 108 +               .bit = BCM63268_TCLK_FAP1,
 109 +       }, {
 110 +               .name = "fap2_pll",
 111 +               .bit = BCM63268_TCLK_FAP2,
 112 +       }, {
 113 +               .name = "uto_50",
 114 +               .bit = BCM63268_TCLK_UTO_50,
 115 +       }, {
 116 +               .name = "uto_extin",
 117 +               .bit = BCM63268_TCLK_UTO_EXTIN,
 118 +       }, {
 119 +               .name = "usb_ref",
 120 +               .bit = BCM63268_TCLK_USB_REF,
 121 +       }, {
 122 +               /* sentinel */
 123 +       }
 124 +};
 125 +
 126 +static inline struct bcm63268_tclkrst_hw *
 127 +to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
 128 +{
 129 +       return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
 130 +}
 131 +
 132 +static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev,
 133 +                               unsigned long id, bool assert)
 134 +{
 135 +       struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
 136 +       unsigned long flags;
 137 +       uint32_t val;
 138 +
 139 +       spin_lock_irqsave(&reset->lock, flags);
 140 +       val = __raw_readl(reset->regs);
 141 +       if (assert)
 142 +               val &= ~BIT(id);
 143 +       else
 144 +               val |= BIT(id);
 145 +       __raw_writel(val, reset->regs);
 146 +       spin_unlock_irqrestore(&reset->lock, flags);
 147 +
 148 +       return 0;
 149 +}
 150 +
 151 +static int bcm63268_timer_reset_assert(struct reset_controller_dev *rcdev,
 152 +                               unsigned long id)
 153 +{
 154 +       return bcm63268_timer_reset_update(rcdev, id, true);
 155 +}
 156 +
 157 +static int bcm63268_timer_reset_deassert(struct reset_controller_dev *rcdev,
 158 +                                 unsigned long id)
 159 +{
 160 +       return bcm63268_timer_reset_update(rcdev, id, false);
 161 +}
 162 +
 163 +static int bcm63268_timer_reset_reset(struct reset_controller_dev *rcdev,
 164 +                              unsigned long id)
 165 +{
 166 +       bcm63268_timer_reset_update(rcdev, id, true);
 167 +       usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US,
 168 +                    BCM63268_TIMER_RESET_SLEEP_MAX_US);
 169 +
 170 +       bcm63268_timer_reset_update(rcdev, id, false);
 171 +       /*
 172 +        * Ensure component is taken out reset state by sleeping also after
 173 +        * deasserting the reset. Otherwise, the component may not be ready
 174 +        * for operation.
 175 +        */
 176 +       usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US,
 177 +                    BCM63268_TIMER_RESET_SLEEP_MAX_US);
 178 +
 179 +       return 0;
 180 +}
 181 +
 182 +static int bcm63268_timer_reset_status(struct reset_controller_dev *rcdev,
 183 +                               unsigned long id)
 184 +{
 185 +       struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
 186 +
 187 +       return !(__raw_readl(reset->regs) & BIT(id));
 188 +}
 189 +
 190 +static struct reset_control_ops bcm63268_timer_reset_ops = {
 191 +       .assert = bcm63268_timer_reset_assert,
 192 +       .deassert = bcm63268_timer_reset_deassert,
 193 +       .reset = bcm63268_timer_reset_reset,
 194 +       .status = bcm63268_timer_reset_status,
 195 +};
 196 +
 197 +static int bcm63268_tclk_probe(struct platform_device *pdev)
 198 +{
 199 +       struct device *dev = &pdev->dev;
 200 +       const struct bcm63268_tclk_table_entry *entry, *table;
 201 +       struct bcm63268_tclkrst_hw *hw;
 202 +       u8 maxbit = 0;
 203 +       int i, ret;
 204 +
 205 +       table = of_device_get_match_data(dev);
 206 +       if (!table)
 207 +               return -EINVAL;
 208 +
 209 +       for (entry = table; entry->name; entry++)
 210 +               maxbit = max_t(u8, maxbit, entry->bit);
 211 +       maxbit++;
 212 +
 213 +       hw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit),
 214 +                         GFP_KERNEL);
 215 +       if (!hw)
 216 +               return -ENOMEM;
 217 +
 218 +       platform_set_drvdata(pdev, hw);
 219 +
 220 +       spin_lock_init(&hw->lock);
 221 +
 222 +       hw->data.num = maxbit;
 223 +       for (i = 0; i < maxbit; i++)
 224 +               hw->data.hws[i] = ERR_PTR(-ENODEV);
 225 +
 226 +       hw->regs = devm_platform_ioremap_resource(pdev, 0);
 227 +       if (IS_ERR(hw->regs))
 228 +               return PTR_ERR(hw->regs);
 229 +
 230 +       for (entry = table; entry->name; entry++) {
 231 +               struct clk_hw *clk;
 232 +
 233 +               clk = clk_hw_register_gate(dev, entry->name, NULL,
 234 +                                          entry->flags, hw->regs, entry->bit,
 235 +                                          CLK_GATE_BIG_ENDIAN, &hw->lock);
 236 +               if (IS_ERR(clk)) {
 237 +                       ret = PTR_ERR(clk);
 238 +                       goto out_err;
 239 +               }
 240 +
 241 +               hw->data.hws[entry->bit] = clk;
 242 +       }
 243 +
 244 +       ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
 245 +                                    &hw->data);
 246 +       if (!ret)
 247 +               return 0;
 248 +
 249 +       hw->rcdev.of_node = dev->of_node;
 250 +       hw->rcdev.ops = &bcm63268_timer_reset_ops;
 251 +
 252 +       ret = devm_reset_controller_register(dev, &hw->rcdev);
 253 +       if (ret)
 254 +               dev_err(dev, "Failed to register reset controller\n");
 255 +
 256 +out_err:
 257 +       for (i = 0; i < hw->data.num; i++) {
 258 +               if (!IS_ERR(hw->data.hws[i]))
 259 +                       clk_hw_unregister_gate(hw->data.hws[i]);
 260 +       }
 261 +
 262 +       return ret;
 263 +}
 264 +
 265 +static const struct of_device_id bcm63268_tclk_dt_ids[] = {
 266 +       {
 267 +               .compatible = "brcm,bcm63268-timer-clocks",
 268 +               .data = &bcm63268_timer_clocks,
 269 +       }, {
 270 +               /* sentinel */
 271 +       }
 272 +};
 273 +
 274 +static struct platform_driver bcm63268_tclk = {
 275 +       .probe = bcm63268_tclk_probe,
 276 +       .driver = {
 277 +               .name = "bcm63268-timer-clock",
 278 +               .of_match_table = bcm63268_tclk_dt_ids,
 279 +       },
 280 +};
 281 +builtin_platform_driver(bcm63268_tclk);