1 From 3e4c3863e0cfb8c2abdff6bb494ca69d3d2aed9c Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
3 Date: Sat, 10 Jun 2023 17:01:40 +0200
4 Subject: [PATCH] mips: bmips: dma: fix CBR address
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 Some BCM63xx SoCs may return CBR address as 0.
11 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
13 arch/mips/bmips/dma.c | 12 ++++--------
14 arch/mips/bmips/setup.c | 11 ++++-------
15 2 files changed, 8 insertions(+), 15 deletions(-)
17 --- a/arch/mips/bmips/dma.c
18 +++ b/arch/mips/bmips/dma.c
20 #include <asm/bmips.h>
23 -bool bmips_rac_flush_disable;
24 +void __iomem *bmips_cbr_addr;
26 void arch_sync_dma_for_cpu_all(void)
28 - void __iomem *cbr = BMIPS_GET_CBR();
31 if (boot_cpu_type() != CPU_BMIPS3300 &&
32 @@ -17,11 +16,8 @@ void arch_sync_dma_for_cpu_all(void)
33 boot_cpu_type() != CPU_BMIPS4380)
36 - if (unlikely(bmips_rac_flush_disable))
39 /* Flush stale data out of the readahead cache */
40 - cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
41 - __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
42 - __raw_readl(cbr + BMIPS_RAC_CONFIG);
43 + cfg = __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG);
44 + __raw_writel(cfg | 0x100, bmips_cbr_addr + BMIPS_RAC_CONFIG);
45 + __raw_readl(bmips_cbr_addr + BMIPS_RAC_CONFIG);
47 --- a/arch/mips/bmips/setup.c
48 +++ b/arch/mips/bmips/setup.c
51 #define DDR_CSEND_REG 0x8
53 -extern bool bmips_rac_flush_disable;
54 +extern void __iomem *bmips_cbr_addr;
56 static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
58 @@ -171,12 +171,6 @@ static void bcm6358_quirks(void)
61 bmips_smp_enabled = 0;
64 - * RAC flush causes kernel panics on BCM6358 when booting from TP1
65 - * because the bootloader is not initializing it properly.
67 - bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31));
70 static void bcm6368_quirks(void)
71 @@ -209,6 +203,11 @@ static void __init bmips_init_cfe(void)
73 void __init prom_init(void)
75 + if (!(read_c0_brcm_cbr() >> 18))
76 + bmips_cbr_addr = (void __iomem *) 0xff400000;
78 + bmips_cbr_addr = BMIPS_GET_CBR();
82 register_bmips_smp_ops();