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brcm2708: update to v3.18
[openwrt/staging/wigyori.git] / target / linux / brcm2708 / patches-3.18 / 0089-Add-2709-platform-for-Raspberry-Pi-2.patch
1 From 08891f5b4dedf2c490371cef6af91f3b7475282d Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Tue, 7 May 2013 14:32:27 +0100
4 Subject: [PATCH 089/114] Add 2709 platform for Raspberry Pi 2
5
6 ---
7 arch/arm/Kconfig | 21 +
8 arch/arm/Makefile | 1 +
9 arch/arm/boot/dts/Makefile | 11 +-
10 arch/arm/boot/dts/bcm2709-rpi-2-b.dts | 101 ++
11 arch/arm/boot/dts/bcm2709.dtsi | 159 +++
12 arch/arm/configs/bcm2709_defconfig | 1149 ++++++++++++++++++++
13 arch/arm/configs/bcm2709_sdcard_defconfig | 129 +++
14 arch/arm/configs/bcm2709_small_defconfig | 61 ++
15 arch/arm/configs/bcm2835_sdcard_defconfig | 176 +++
16 arch/arm/configs/bcmrpi_sdcard_defconfig | 176 +++
17 arch/arm/configs/bcmrpi_small_defconfig | 103 ++
18 arch/arm/kernel/head.S | 8 +
19 arch/arm/mach-bcm2709/Kconfig | 49 +
20 arch/arm/mach-bcm2709/Makefile | 7 +
21 arch/arm/mach-bcm2709/Makefile.boot | 3 +
22 arch/arm/mach-bcm2709/armctrl.c | 357 +++++++
23 arch/arm/mach-bcm2709/armctrl.h | 27 +
24 arch/arm/mach-bcm2709/bcm2708_gpio.c | 426 ++++++++
25 arch/arm/mach-bcm2709/bcm2709.c | 1237 ++++++++++++++++++++++
26 arch/arm/mach-bcm2709/bcm2709.h | 49 +
27 arch/arm/mach-bcm2709/clock.c | 61 ++
28 arch/arm/mach-bcm2709/clock.h | 24 +
29 arch/arm/mach-bcm2709/delay.S | 21 +
30 arch/arm/mach-bcm2709/dma.c | 409 +++++++
31 arch/arm/mach-bcm2709/dmaer.c | 886 ++++++++++++++++
32 arch/arm/mach-bcm2709/include/mach/arm_control.h | 493 +++++++++
33 arch/arm/mach-bcm2709/include/mach/arm_power.h | 62 ++
34 arch/arm/mach-bcm2709/include/mach/barriers.h | 3 +
35 arch/arm/mach-bcm2709/include/mach/clkdev.h | 7 +
36 arch/arm/mach-bcm2709/include/mach/debug-macro.S | 22 +
37 arch/arm/mach-bcm2709/include/mach/dma.h | 94 ++
38 arch/arm/mach-bcm2709/include/mach/entry-macro.S | 123 +++
39 arch/arm/mach-bcm2709/include/mach/frc.h | 38 +
40 arch/arm/mach-bcm2709/include/mach/gpio.h | 17 +
41 arch/arm/mach-bcm2709/include/mach/hardware.h | 28 +
42 arch/arm/mach-bcm2709/include/mach/io.h | 27 +
43 arch/arm/mach-bcm2709/include/mach/irqs.h | 225 ++++
44 arch/arm/mach-bcm2709/include/mach/memory.h | 57 +
45 arch/arm/mach-bcm2709/include/mach/platform.h | 225 ++++
46 arch/arm/mach-bcm2709/include/mach/power.h | 26 +
47 arch/arm/mach-bcm2709/include/mach/system.h | 38 +
48 arch/arm/mach-bcm2709/include/mach/timex.h | 23 +
49 arch/arm/mach-bcm2709/include/mach/uncompress.h | 84 ++
50 arch/arm/mach-bcm2709/include/mach/vc_mem.h | 35 +
51 arch/arm/mach-bcm2709/include/mach/vc_support.h | 69 ++
52 arch/arm/mach-bcm2709/include/mach/vcio.h | 165 +++
53 arch/arm/mach-bcm2709/include/mach/vmalloc.h | 20 +
54 arch/arm/mach-bcm2709/power.c | 195 ++++
55 arch/arm/mach-bcm2709/vc_mem.c | 431 ++++++++
56 arch/arm/mach-bcm2709/vc_support.c | 318 ++++++
57 arch/arm/mach-bcm2709/vcio.c | 474 +++++++++
58 arch/arm/mm/proc-v7.S | 1 +
59 arch/arm/tools/mach-types | 1 +
60 drivers/char/hw_random/Kconfig | 2 +-
61 drivers/clocksource/arm_arch_timer.c | 36 +
62 drivers/dma/Kconfig | 2 +-
63 drivers/i2c/busses/Kconfig | 4 +-
64 drivers/media/platform/bcm2835/Kconfig | 2 +-
65 drivers/misc/vc04_services/Kconfig | 2 +-
66 drivers/misc/vc04_services/Makefile | 3 -
67 drivers/mmc/host/Kconfig | 2 +-
68 drivers/spi/Kconfig | 4 +-
69 drivers/watchdog/Kconfig | 2 +-
70 sound/arm/Kconfig | 2 +-
71 sound/soc/bcm/Kconfig | 2 +-
72 65 files changed, 8999 insertions(+), 16 deletions(-)
73 create mode 100644 arch/arm/boot/dts/bcm2709-rpi-2-b.dts
74 create mode 100644 arch/arm/boot/dts/bcm2709.dtsi
75 create mode 100644 arch/arm/configs/bcm2709_defconfig
76 create mode 100644 arch/arm/configs/bcm2709_sdcard_defconfig
77 create mode 100644 arch/arm/configs/bcm2709_small_defconfig
78 create mode 100644 arch/arm/configs/bcm2835_sdcard_defconfig
79 create mode 100644 arch/arm/configs/bcmrpi_sdcard_defconfig
80 create mode 100644 arch/arm/configs/bcmrpi_small_defconfig
81 create mode 100644 arch/arm/mach-bcm2709/Kconfig
82 create mode 100644 arch/arm/mach-bcm2709/Makefile
83 create mode 100644 arch/arm/mach-bcm2709/Makefile.boot
84 create mode 100644 arch/arm/mach-bcm2709/armctrl.c
85 create mode 100644 arch/arm/mach-bcm2709/armctrl.h
86 create mode 100644 arch/arm/mach-bcm2709/bcm2708_gpio.c
87 create mode 100644 arch/arm/mach-bcm2709/bcm2709.c
88 create mode 100644 arch/arm/mach-bcm2709/bcm2709.h
89 create mode 100644 arch/arm/mach-bcm2709/clock.c
90 create mode 100644 arch/arm/mach-bcm2709/clock.h
91 create mode 100644 arch/arm/mach-bcm2709/delay.S
92 create mode 100644 arch/arm/mach-bcm2709/dma.c
93 create mode 100755 arch/arm/mach-bcm2709/dmaer.c
94 create mode 100644 arch/arm/mach-bcm2709/include/mach/arm_control.h
95 create mode 100644 arch/arm/mach-bcm2709/include/mach/arm_power.h
96 create mode 100644 arch/arm/mach-bcm2709/include/mach/barriers.h
97 create mode 100644 arch/arm/mach-bcm2709/include/mach/clkdev.h
98 create mode 100644 arch/arm/mach-bcm2709/include/mach/debug-macro.S
99 create mode 100644 arch/arm/mach-bcm2709/include/mach/dma.h
100 create mode 100644 arch/arm/mach-bcm2709/include/mach/entry-macro.S
101 create mode 100644 arch/arm/mach-bcm2709/include/mach/frc.h
102 create mode 100644 arch/arm/mach-bcm2709/include/mach/gpio.h
103 create mode 100644 arch/arm/mach-bcm2709/include/mach/hardware.h
104 create mode 100644 arch/arm/mach-bcm2709/include/mach/io.h
105 create mode 100644 arch/arm/mach-bcm2709/include/mach/irqs.h
106 create mode 100644 arch/arm/mach-bcm2709/include/mach/memory.h
107 create mode 100644 arch/arm/mach-bcm2709/include/mach/platform.h
108 create mode 100644 arch/arm/mach-bcm2709/include/mach/power.h
109 create mode 100644 arch/arm/mach-bcm2709/include/mach/system.h
110 create mode 100644 arch/arm/mach-bcm2709/include/mach/timex.h
111 create mode 100644 arch/arm/mach-bcm2709/include/mach/uncompress.h
112 create mode 100644 arch/arm/mach-bcm2709/include/mach/vc_mem.h
113 create mode 100755 arch/arm/mach-bcm2709/include/mach/vc_support.h
114 create mode 100644 arch/arm/mach-bcm2709/include/mach/vcio.h
115 create mode 100644 arch/arm/mach-bcm2709/include/mach/vmalloc.h
116 create mode 100644 arch/arm/mach-bcm2709/power.c
117 create mode 100644 arch/arm/mach-bcm2709/vc_mem.c
118 create mode 100755 arch/arm/mach-bcm2709/vc_support.c
119 create mode 100644 arch/arm/mach-bcm2709/vcio.c
120
121 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
122 index 0f2287f..1faad0d 100644
123 --- a/arch/arm/Kconfig
124 +++ b/arch/arm/Kconfig
125 @@ -803,6 +803,26 @@ config ARCH_OMAP1
126 help
127 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
128
129 +config ARCH_BCM2709
130 + bool "Broadcom BCM2709 family"
131 + select ARCH_HAS_BARRIERS if SMP
132 + select CPU_V7
133 + select HAVE_SMP
134 + select ARM_AMBA
135 + select MIGHT_HAVE_CACHE_L2X0
136 + select HAVE_SCHED_CLOCK
137 + select NEED_MACH_MEMORY_H
138 + select NEED_MACH_IO_H
139 + select COMMON_CLK
140 + select ARCH_HAS_CPUFREQ
141 + select GENERIC_CLOCKEVENTS
142 + select MACH_BCM2709
143 + select VC4
144 + select FIQ
145 +# select ZONE_DMA
146 + help
147 + This enables support for Broadcom BCM2709 boards.
148 +
149 endchoice
150
151 menu "Multiple platform selection"
152 @@ -990,6 +1010,7 @@ source "arch/arm/mach-vt8500/Kconfig"
153
154 source "arch/arm/mach-w90x900/Kconfig"
155 source "arch/arm/mach-bcm2708/Kconfig"
156 +source "arch/arm/mach-bcm2709/Kconfig"
157
158 source "arch/arm/mach-zynq/Kconfig"
159
160 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
161 index fea9213..2f1376e 100644
162 --- a/arch/arm/Makefile
163 +++ b/arch/arm/Makefile
164 @@ -147,6 +147,7 @@ machine-$(CONFIG_ARCH_AT91) += at91
165 machine-$(CONFIG_ARCH_AXXIA) += axxia
166 machine-$(CONFIG_ARCH_BCM) += bcm
167 machine-$(CONFIG_ARCH_BCM2708) += bcm2708
168 +machine-$(CONFIG_ARCH_BCM2709) += bcm2709
169 machine-$(CONFIG_ARCH_BERLIN) += berlin
170 machine-$(CONFIG_ARCH_CLPS711X) += clps711x
171 machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
172 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
173 index 1b66478..605ed38 100644
174 --- a/arch/arm/boot/dts/Makefile
175 +++ b/arch/arm/boot/dts/Makefile
176 @@ -53,6 +53,14 @@ dtb-$(CONFIG_ARCH_AT91) += at91-sama5d4ek.dtb
177
178 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
179 dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
180 +
181 +# Raspberry Pi
182 +ifeq ($(CONFIG_BCM2708_DT),y)
183 + RPI_DT_OVERLAYS=y
184 +endif
185 +ifeq ($(CONFIG_BCM2709_DT),y)
186 + RPI_DT_OVERLAYS=y
187 +endif
188 dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b.dtb
189 dtb-$(CONFIG_BCM2708_DT) += bcm2708-rpi-b-plus.dtb
190 dtb-$(CONFIG_BCM2708_DT) += hifiberry-dac-overlay.dtb
191 @@ -68,6 +76,7 @@ dtb-$(CONFIG_BCM2708_DT) += ds1307-rtc-overlay.dtb
192 dtb-$(CONFIG_BCM2708_DT) += w1-gpio-overlay.dtb
193 dtb-$(CONFIG_BCM2708_DT) += w1-gpio-pullup-overlay.dtb
194 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
195 +
196 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
197 dtb-$(CONFIG_ARCH_BCM_63XX) += bcm963138dvt.dtb
198 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
199 @@ -537,7 +546,7 @@ targets += $(dtb-y)
200 endif
201
202 # Enable fixups to support overlays on BCM2708 platforms
203 -ifeq ($(CONFIG_BCM2708_DT),y)
204 +ifeq ($(RPI_DT_OVERLAYS),y)
205 DTC_FLAGS ?= -@
206 endif
207
208 diff --git a/arch/arm/boot/dts/bcm2709-rpi-2-b.dts b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts
209 new file mode 100644
210 index 0000000..0cdff31
211 --- /dev/null
212 +++ b/arch/arm/boot/dts/bcm2709-rpi-2-b.dts
213 @@ -0,0 +1,101 @@
214 +/dts-v1/;
215 +
216 +/include/ "bcm2709.dtsi"
217 +
218 +/ {
219 + compatible = "brcm,bcm2709";
220 + model = "Raspberry Pi 2 Model B";
221 +
222 + aliases {
223 + soc = &soc;
224 + spi0 = &spi0;
225 + i2c0 = &i2c0;
226 + i2c1 = &i2c1;
227 + i2s = &i2s;
228 + gpio = &gpio;
229 + intc = &intc;
230 + leds = &leds;
231 + sound = &sound;
232 + };
233 +
234 + sound: sound {
235 + };
236 +};
237 +
238 +&gpio {
239 + spi0_pins: spi0_pins {
240 + brcm,pins = <7 8 9 10 11>;
241 + brcm,function = <4>; /* alt0 */
242 + };
243 +
244 + i2c0_pins: i2c0 {
245 + brcm,pins = <0 1>;
246 + brcm,function = <4>;
247 + };
248 +
249 + i2c1_pins: i2c1 {
250 + brcm,pins = <2 3>;
251 + brcm,function = <4>;
252 + };
253 +
254 + i2s_pins: i2s {
255 + brcm,pins = <18 19 20 21>;
256 + brcm,function = <4>; /* alt0 */
257 + };
258 +};
259 +
260 +&spi0 {
261 + pinctrl-names = "default";
262 + pinctrl-0 = <&spi0_pins>;
263 +
264 + spidev@0{
265 + compatible = "spidev";
266 + reg = <0>; /* CE0 */
267 + #address-cells = <1>;
268 + #size-cells = <0>;
269 + spi-max-frequency = <500000>;
270 + };
271 +
272 + spidev@1{
273 + compatible = "spidev";
274 + reg = <1>; /* CE1 */
275 + #address-cells = <1>;
276 + #size-cells = <0>;
277 + spi-max-frequency = <500000>;
278 + };
279 +};
280 +
281 +&i2c0 {
282 + pinctrl-names = "default";
283 + pinctrl-0 = <&i2c0_pins>;
284 + clock-frequency = <100000>;
285 +};
286 +
287 +&i2c1 {
288 + pinctrl-names = "default";
289 + pinctrl-0 = <&i2c1_pins>;
290 + clock-frequency = <100000>;
291 +};
292 +
293 +&i2s {
294 + #sound-dai-cells = <0>;
295 + pinctrl-names = "default";
296 + pinctrl-0 = <&i2s_pins>;
297 +};
298 +
299 +&act_led {
300 + gpios = <&gpio 47 0>;
301 +};
302 +
303 +/ {
304 + __overrides__ {
305 + i2s = <&i2s>,"status";
306 + spi = <&spi0>,"status";
307 + i2c0 = <&i2c0>,"status";
308 + i2c1 = <&i2c1>,"status";
309 +
310 + act_led_gpio = <&act_led>,"gpios:4";
311 + act_led_activelow = <&act_led>,"gpios:8";
312 + act_led_trigger = <&act_led>,"linux,default-trigger";
313 + };
314 +};
315 diff --git a/arch/arm/boot/dts/bcm2709.dtsi b/arch/arm/boot/dts/bcm2709.dtsi
316 new file mode 100644
317 index 0000000..c7e975c
318 --- /dev/null
319 +++ b/arch/arm/boot/dts/bcm2709.dtsi
320 @@ -0,0 +1,159 @@
321 +/include/ "skeleton.dtsi"
322 +
323 +/ {
324 + compatible = "brcm,bcm2709";
325 + model = "BCM2709";
326 +
327 + interrupt-parent = <&intc>;
328 +
329 + chosen {
330 + /* No padding required - the boot loader can do that. */
331 + bootargs = "";
332 + };
333 +
334 + soc: soc {
335 + compatible = "simple-bus";
336 + #address-cells = <1>;
337 + #size-cells = <1>;
338 + ranges = <0x7e000000 0x3f000000 0x01000000>;
339 +
340 + intc: interrupt-controller {
341 + compatible = "brcm,bcm2708-armctrl-ic";
342 + reg = <0x7e00b200 0x200>;
343 + interrupt-controller;
344 + #interrupt-cells = <2>;
345 + };
346 +
347 + gpio: gpio {
348 + compatible = "brcm,bcm2835-gpio";
349 + reg = <0x7e200000 0xb4>;
350 + interrupts = <2 17>, <2 18>;
351 +
352 + gpio-controller;
353 + #gpio-cells = <2>;
354 +
355 + interrupt-controller;
356 + #interrupt-cells = <2>;
357 + };
358 +
359 + i2s: i2s@7e203000 {
360 + compatible = "brcm,bcm2708-i2s";
361 + reg = <0x7e203000 0x20>,
362 + <0x7e101098 0x02>;
363 +
364 + //dmas = <&dma 2>,
365 + // <&dma 3>;
366 + dma-names = "tx", "rx";
367 + status = "disabled";
368 + };
369 +
370 + spi0: spi@7e204000 {
371 + compatible = "brcm,bcm2708-spi";
372 + reg = <0x7e204000 0x1000>;
373 + interrupts = <2 22>;
374 + clocks = <&clk_spi>;
375 + #address-cells = <1>;
376 + #size-cells = <0>;
377 + status = "disabled";
378 + };
379 +
380 + i2c0: i2c@7e205000 {
381 + compatible = "brcm,bcm2708-i2c";
382 + reg = <0x7e205000 0x1000>;
383 + interrupts = <2 21>;
384 + clocks = <&clk_i2c>;
385 + #address-cells = <1>;
386 + #size-cells = <0>;
387 + status = "disabled";
388 + };
389 +
390 + i2c1: i2c@7e804000 {
391 + compatible = "brcm,bcm2708-i2c";
392 + reg = <0x7e804000 0x1000>;
393 + interrupts = <2 21>;
394 + clocks = <&clk_i2c>;
395 + #address-cells = <1>;
396 + #size-cells = <0>;
397 + status = "disabled";
398 + };
399 +
400 + leds: leds {
401 + compatible = "gpio-leds";
402 +
403 + act_led: act {
404 + label = "ACT";
405 + linux,default-trigger = "mmc0";
406 + };
407 + };
408 + };
409 +
410 + clocks {
411 + compatible = "simple-bus";
412 + #address-cells = <1>;
413 + #size-cells = <0>;
414 +
415 + clk_i2c: i2c {
416 + compatible = "fixed-clock";
417 + reg = <1>;
418 + #clock-cells = <0>;
419 + clock-frequency = <250000000>;
420 + };
421 +
422 + clk_spi: clock@2 {
423 + compatible = "fixed-clock";
424 + reg = <2>;
425 + #clock-cells = <0>;
426 + clock-output-names = "spi";
427 + clock-frequency = <250000000>;
428 + };
429 + };
430 +
431 + timer {
432 + compatible = "arm,armv7-timer";
433 + clock-frequency = <19200000>;
434 + interrupts = <3 0>, // PHYS_SECURE_PPI
435 + <3 1>, // PHYS_NONSECURE_PPI
436 + <3 3>, // VIRT_PPI
437 + <3 2>; // HYP_PPI
438 + };
439 +
440 + cpus: cpus {
441 + #address-cells = <1>;
442 + #size-cells = <0>;
443 +
444 + v7_cpu0: cpu@0 {
445 + device_type = "cpu";
446 + compatible = "arm,cortex-a7";
447 + reg = <0xf00>;
448 + clock-frequency = <800000000>;
449 + };
450 +
451 + v7_cpu1: cpu@1 {
452 + device_type = "cpu";
453 + compatible = "arm,cortex-a7";
454 + reg = <0xf01>;
455 + clock-frequency = <800000000>;
456 + };
457 +
458 + v7_cpu2: cpu@2 {
459 + device_type = "cpu";
460 + compatible = "arm,cortex-a7";
461 + reg = <0xf02>;
462 + clock-frequency = <800000000>;
463 + };
464 +
465 + v7_cpu3: cpu@3 {
466 + device_type = "cpu";
467 + compatible = "arm,cortex-a7";
468 + reg = <0xf03>;
469 + clock-frequency = <800000000>;
470 + };
471 + };
472 +
473 + __overrides__ {
474 + arm_freq = <&v7_cpu0>, "clock-frequency:0",
475 + <&v7_cpu1>, "clock-frequency:0",
476 + <&v7_cpu2>, "clock-frequency:0",
477 + <&v7_cpu3>, "clock-frequency:0";
478 + };
479 +};
480 diff --git a/arch/arm/configs/bcm2709_defconfig b/arch/arm/configs/bcm2709_defconfig
481 new file mode 100644
482 index 0000000..70b175c
483 --- /dev/null
484 +++ b/arch/arm/configs/bcm2709_defconfig
485 @@ -0,0 +1,1149 @@
486 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
487 +CONFIG_PHYS_OFFSET=0
488 +CONFIG_LOCALVERSION="-v7"
489 +# CONFIG_LOCALVERSION_AUTO is not set
490 +CONFIG_SYSVIPC=y
491 +CONFIG_POSIX_MQUEUE=y
492 +CONFIG_FHANDLE=y
493 +CONFIG_AUDIT=y
494 +CONFIG_NO_HZ=y
495 +CONFIG_HIGH_RES_TIMERS=y
496 +CONFIG_BSD_PROCESS_ACCT=y
497 +CONFIG_BSD_PROCESS_ACCT_V3=y
498 +CONFIG_TASKSTATS=y
499 +CONFIG_TASK_DELAY_ACCT=y
500 +CONFIG_TASK_XACCT=y
501 +CONFIG_TASK_IO_ACCOUNTING=y
502 +CONFIG_IKCONFIG=y
503 +CONFIG_IKCONFIG_PROC=y
504 +CONFIG_CGROUP_FREEZER=y
505 +CONFIG_CGROUP_DEVICE=y
506 +CONFIG_CGROUP_CPUACCT=y
507 +CONFIG_RESOURCE_COUNTERS=y
508 +CONFIG_MEMCG=y
509 +CONFIG_BLK_CGROUP=y
510 +CONFIG_NAMESPACES=y
511 +CONFIG_SCHED_AUTOGROUP=y
512 +CONFIG_BLK_DEV_INITRD=y
513 +CONFIG_EMBEDDED=y
514 +# CONFIG_COMPAT_BRK is not set
515 +CONFIG_PROFILING=y
516 +CONFIG_OPROFILE=m
517 +CONFIG_KPROBES=y
518 +CONFIG_JUMP_LABEL=y
519 +CONFIG_MODULES=y
520 +CONFIG_MODULE_UNLOAD=y
521 +CONFIG_MODVERSIONS=y
522 +CONFIG_MODULE_SRCVERSION_ALL=y
523 +CONFIG_BLK_DEV_THROTTLING=y
524 +CONFIG_PARTITION_ADVANCED=y
525 +CONFIG_MAC_PARTITION=y
526 +CONFIG_CFQ_GROUP_IOSCHED=y
527 +CONFIG_ARCH_BCM2709=y
528 +CONFIG_BCM2709_DT=y
529 +# CONFIG_CACHE_L2X0 is not set
530 +CONFIG_SMP=y
531 +CONFIG_HAVE_ARM_ARCH_TIMER=y
532 +CONFIG_VMSPLIT_2G=y
533 +CONFIG_PREEMPT=y
534 +CONFIG_AEABI=y
535 +CONFIG_CLEANCACHE=y
536 +CONFIG_FRONTSWAP=y
537 +CONFIG_CMA=y
538 +CONFIG_UACCESS_WITH_MEMCPY=y
539 +CONFIG_SECCOMP=y
540 +CONFIG_ZBOOT_ROM_TEXT=0x0
541 +CONFIG_ZBOOT_ROM_BSS=0x0
542 +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
543 +CONFIG_KEXEC=y
544 +CONFIG_CPU_FREQ=y
545 +CONFIG_CPU_FREQ_STAT=m
546 +CONFIG_CPU_FREQ_STAT_DETAILS=y
547 +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
548 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
549 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
550 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
551 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
552 +CONFIG_CPU_IDLE=y
553 +CONFIG_VFP=y
554 +CONFIG_NEON=y
555 +CONFIG_KERNEL_MODE_NEON=y
556 +CONFIG_BINFMT_MISC=m
557 +CONFIG_NET=y
558 +CONFIG_PACKET=y
559 +CONFIG_UNIX=y
560 +CONFIG_XFRM_USER=y
561 +CONFIG_NET_KEY=m
562 +CONFIG_INET=y
563 +CONFIG_IP_MULTICAST=y
564 +CONFIG_IP_ADVANCED_ROUTER=y
565 +CONFIG_IP_MULTIPLE_TABLES=y
566 +CONFIG_IP_ROUTE_MULTIPATH=y
567 +CONFIG_IP_ROUTE_VERBOSE=y
568 +CONFIG_IP_PNP=y
569 +CONFIG_IP_PNP_DHCP=y
570 +CONFIG_IP_PNP_RARP=y
571 +CONFIG_NET_IPIP=m
572 +CONFIG_NET_IPGRE_DEMUX=m
573 +CONFIG_NET_IPGRE=m
574 +CONFIG_IP_MROUTE=y
575 +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
576 +CONFIG_IP_PIMSM_V1=y
577 +CONFIG_IP_PIMSM_V2=y
578 +CONFIG_SYN_COOKIES=y
579 +CONFIG_INET_AH=m
580 +CONFIG_INET_ESP=m
581 +CONFIG_INET_IPCOMP=m
582 +CONFIG_INET_XFRM_MODE_TRANSPORT=m
583 +CONFIG_INET_XFRM_MODE_TUNNEL=m
584 +CONFIG_INET_XFRM_MODE_BEET=m
585 +CONFIG_INET_LRO=m
586 +CONFIG_INET_DIAG=m
587 +CONFIG_INET6_AH=m
588 +CONFIG_INET6_ESP=m
589 +CONFIG_INET6_IPCOMP=m
590 +CONFIG_IPV6_TUNNEL=m
591 +CONFIG_IPV6_MULTIPLE_TABLES=y
592 +CONFIG_IPV6_MROUTE=y
593 +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
594 +CONFIG_IPV6_PIMSM_V2=y
595 +CONFIG_NETFILTER=y
596 +CONFIG_NF_CONNTRACK=m
597 +CONFIG_NF_CONNTRACK_ZONES=y
598 +CONFIG_NF_CONNTRACK_EVENTS=y
599 +CONFIG_NF_CONNTRACK_TIMESTAMP=y
600 +CONFIG_NF_CT_PROTO_DCCP=m
601 +CONFIG_NF_CT_PROTO_UDPLITE=m
602 +CONFIG_NF_CONNTRACK_AMANDA=m
603 +CONFIG_NF_CONNTRACK_FTP=m
604 +CONFIG_NF_CONNTRACK_H323=m
605 +CONFIG_NF_CONNTRACK_IRC=m
606 +CONFIG_NF_CONNTRACK_NETBIOS_NS=m
607 +CONFIG_NF_CONNTRACK_SNMP=m
608 +CONFIG_NF_CONNTRACK_PPTP=m
609 +CONFIG_NF_CONNTRACK_SANE=m
610 +CONFIG_NF_CONNTRACK_SIP=m
611 +CONFIG_NF_CONNTRACK_TFTP=m
612 +CONFIG_NF_CT_NETLINK=m
613 +CONFIG_NETFILTER_XT_SET=m
614 +CONFIG_NETFILTER_XT_TARGET_AUDIT=m
615 +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
616 +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
617 +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
618 +CONFIG_NETFILTER_XT_TARGET_DSCP=m
619 +CONFIG_NETFILTER_XT_TARGET_HMARK=m
620 +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
621 +CONFIG_NETFILTER_XT_TARGET_LED=m
622 +CONFIG_NETFILTER_XT_TARGET_LOG=m
623 +CONFIG_NETFILTER_XT_TARGET_MARK=m
624 +CONFIG_NETFILTER_XT_TARGET_NFLOG=m
625 +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
626 +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
627 +CONFIG_NETFILTER_XT_TARGET_TEE=m
628 +CONFIG_NETFILTER_XT_TARGET_TPROXY=m
629 +CONFIG_NETFILTER_XT_TARGET_TRACE=m
630 +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
631 +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
632 +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
633 +CONFIG_NETFILTER_XT_MATCH_BPF=m
634 +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
635 +CONFIG_NETFILTER_XT_MATCH_COMMENT=m
636 +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
637 +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
638 +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
639 +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
640 +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
641 +CONFIG_NETFILTER_XT_MATCH_CPU=m
642 +CONFIG_NETFILTER_XT_MATCH_DCCP=m
643 +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
644 +CONFIG_NETFILTER_XT_MATCH_DSCP=m
645 +CONFIG_NETFILTER_XT_MATCH_ESP=m
646 +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
647 +CONFIG_NETFILTER_XT_MATCH_HELPER=m
648 +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
649 +CONFIG_NETFILTER_XT_MATCH_IPVS=m
650 +CONFIG_NETFILTER_XT_MATCH_LENGTH=m
651 +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
652 +CONFIG_NETFILTER_XT_MATCH_MAC=m
653 +CONFIG_NETFILTER_XT_MATCH_MARK=m
654 +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
655 +CONFIG_NETFILTER_XT_MATCH_NFACCT=m
656 +CONFIG_NETFILTER_XT_MATCH_OSF=m
657 +CONFIG_NETFILTER_XT_MATCH_OWNER=m
658 +CONFIG_NETFILTER_XT_MATCH_POLICY=m
659 +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
660 +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
661 +CONFIG_NETFILTER_XT_MATCH_QUOTA=m
662 +CONFIG_NETFILTER_XT_MATCH_RATEEST=m
663 +CONFIG_NETFILTER_XT_MATCH_REALM=m
664 +CONFIG_NETFILTER_XT_MATCH_RECENT=m
665 +CONFIG_NETFILTER_XT_MATCH_SOCKET=m
666 +CONFIG_NETFILTER_XT_MATCH_STATE=m
667 +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
668 +CONFIG_NETFILTER_XT_MATCH_STRING=m
669 +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
670 +CONFIG_NETFILTER_XT_MATCH_TIME=m
671 +CONFIG_NETFILTER_XT_MATCH_U32=m
672 +CONFIG_IP_SET=m
673 +CONFIG_IP_SET_BITMAP_IP=m
674 +CONFIG_IP_SET_BITMAP_IPMAC=m
675 +CONFIG_IP_SET_BITMAP_PORT=m
676 +CONFIG_IP_SET_HASH_IP=m
677 +CONFIG_IP_SET_HASH_IPPORT=m
678 +CONFIG_IP_SET_HASH_IPPORTIP=m
679 +CONFIG_IP_SET_HASH_IPPORTNET=m
680 +CONFIG_IP_SET_HASH_NET=m
681 +CONFIG_IP_SET_HASH_NETPORT=m
682 +CONFIG_IP_SET_HASH_NETIFACE=m
683 +CONFIG_IP_SET_LIST_SET=m
684 +CONFIG_IP_VS=m
685 +CONFIG_IP_VS_PROTO_TCP=y
686 +CONFIG_IP_VS_PROTO_UDP=y
687 +CONFIG_IP_VS_PROTO_ESP=y
688 +CONFIG_IP_VS_PROTO_AH=y
689 +CONFIG_IP_VS_PROTO_SCTP=y
690 +CONFIG_IP_VS_RR=m
691 +CONFIG_IP_VS_WRR=m
692 +CONFIG_IP_VS_LC=m
693 +CONFIG_IP_VS_WLC=m
694 +CONFIG_IP_VS_LBLC=m
695 +CONFIG_IP_VS_LBLCR=m
696 +CONFIG_IP_VS_DH=m
697 +CONFIG_IP_VS_SH=m
698 +CONFIG_IP_VS_SED=m
699 +CONFIG_IP_VS_NQ=m
700 +CONFIG_IP_VS_FTP=m
701 +CONFIG_IP_VS_PE_SIP=m
702 +CONFIG_NF_CONNTRACK_IPV4=m
703 +CONFIG_IP_NF_IPTABLES=m
704 +CONFIG_IP_NF_MATCH_AH=m
705 +CONFIG_IP_NF_MATCH_ECN=m
706 +CONFIG_IP_NF_MATCH_TTL=m
707 +CONFIG_IP_NF_FILTER=m
708 +CONFIG_IP_NF_TARGET_REJECT=m
709 +CONFIG_IP_NF_NAT=m
710 +CONFIG_IP_NF_TARGET_MASQUERADE=m
711 +CONFIG_IP_NF_TARGET_NETMAP=m
712 +CONFIG_IP_NF_TARGET_REDIRECT=m
713 +CONFIG_IP_NF_MANGLE=m
714 +CONFIG_IP_NF_TARGET_ECN=m
715 +CONFIG_IP_NF_TARGET_TTL=m
716 +CONFIG_IP_NF_RAW=m
717 +CONFIG_IP_NF_ARPTABLES=m
718 +CONFIG_IP_NF_ARPFILTER=m
719 +CONFIG_IP_NF_ARP_MANGLE=m
720 +CONFIG_NF_CONNTRACK_IPV6=m
721 +CONFIG_IP6_NF_IPTABLES=m
722 +CONFIG_IP6_NF_MATCH_AH=m
723 +CONFIG_IP6_NF_MATCH_EUI64=m
724 +CONFIG_IP6_NF_MATCH_FRAG=m
725 +CONFIG_IP6_NF_MATCH_OPTS=m
726 +CONFIG_IP6_NF_MATCH_HL=m
727 +CONFIG_IP6_NF_MATCH_IPV6HEADER=m
728 +CONFIG_IP6_NF_MATCH_MH=m
729 +CONFIG_IP6_NF_MATCH_RT=m
730 +CONFIG_IP6_NF_TARGET_HL=m
731 +CONFIG_IP6_NF_FILTER=m
732 +CONFIG_IP6_NF_TARGET_REJECT=m
733 +CONFIG_IP6_NF_MANGLE=m
734 +CONFIG_IP6_NF_RAW=m
735 +CONFIG_IP6_NF_NAT=m
736 +CONFIG_IP6_NF_TARGET_MASQUERADE=m
737 +CONFIG_IP6_NF_TARGET_NPT=m
738 +CONFIG_BRIDGE_NF_EBTABLES=m
739 +CONFIG_BRIDGE_EBT_BROUTE=m
740 +CONFIG_BRIDGE_EBT_T_FILTER=m
741 +CONFIG_BRIDGE_EBT_T_NAT=m
742 +CONFIG_BRIDGE_EBT_802_3=m
743 +CONFIG_BRIDGE_EBT_AMONG=m
744 +CONFIG_BRIDGE_EBT_ARP=m
745 +CONFIG_BRIDGE_EBT_IP=m
746 +CONFIG_BRIDGE_EBT_IP6=m
747 +CONFIG_BRIDGE_EBT_LIMIT=m
748 +CONFIG_BRIDGE_EBT_MARK=m
749 +CONFIG_BRIDGE_EBT_PKTTYPE=m
750 +CONFIG_BRIDGE_EBT_STP=m
751 +CONFIG_BRIDGE_EBT_VLAN=m
752 +CONFIG_BRIDGE_EBT_ARPREPLY=m
753 +CONFIG_BRIDGE_EBT_DNAT=m
754 +CONFIG_BRIDGE_EBT_MARK_T=m
755 +CONFIG_BRIDGE_EBT_REDIRECT=m
756 +CONFIG_BRIDGE_EBT_SNAT=m
757 +CONFIG_BRIDGE_EBT_LOG=m
758 +CONFIG_BRIDGE_EBT_NFLOG=m
759 +CONFIG_SCTP_COOKIE_HMAC_SHA1=y
760 +CONFIG_ATM=m
761 +CONFIG_L2TP=m
762 +CONFIG_L2TP_V3=y
763 +CONFIG_L2TP_IP=m
764 +CONFIG_L2TP_ETH=m
765 +CONFIG_BRIDGE=m
766 +CONFIG_VLAN_8021Q=m
767 +CONFIG_VLAN_8021Q_GVRP=y
768 +CONFIG_ATALK=m
769 +CONFIG_NET_SCHED=y
770 +CONFIG_NET_SCH_CBQ=m
771 +CONFIG_NET_SCH_HTB=m
772 +CONFIG_NET_SCH_HFSC=m
773 +CONFIG_NET_SCH_PRIO=m
774 +CONFIG_NET_SCH_MULTIQ=m
775 +CONFIG_NET_SCH_RED=m
776 +CONFIG_NET_SCH_SFB=m
777 +CONFIG_NET_SCH_SFQ=m
778 +CONFIG_NET_SCH_TEQL=m
779 +CONFIG_NET_SCH_TBF=m
780 +CONFIG_NET_SCH_GRED=m
781 +CONFIG_NET_SCH_DSMARK=m
782 +CONFIG_NET_SCH_NETEM=m
783 +CONFIG_NET_SCH_DRR=m
784 +CONFIG_NET_SCH_MQPRIO=m
785 +CONFIG_NET_SCH_CHOKE=m
786 +CONFIG_NET_SCH_QFQ=m
787 +CONFIG_NET_SCH_CODEL=m
788 +CONFIG_NET_SCH_FQ_CODEL=m
789 +CONFIG_NET_SCH_INGRESS=m
790 +CONFIG_NET_SCH_PLUG=m
791 +CONFIG_NET_CLS_BASIC=m
792 +CONFIG_NET_CLS_TCINDEX=m
793 +CONFIG_NET_CLS_ROUTE4=m
794 +CONFIG_NET_CLS_FW=m
795 +CONFIG_NET_CLS_U32=m
796 +CONFIG_CLS_U32_MARK=y
797 +CONFIG_NET_CLS_RSVP=m
798 +CONFIG_NET_CLS_RSVP6=m
799 +CONFIG_NET_CLS_FLOW=m
800 +CONFIG_NET_CLS_CGROUP=m
801 +CONFIG_NET_EMATCH=y
802 +CONFIG_NET_EMATCH_CMP=m
803 +CONFIG_NET_EMATCH_NBYTE=m
804 +CONFIG_NET_EMATCH_U32=m
805 +CONFIG_NET_EMATCH_META=m
806 +CONFIG_NET_EMATCH_TEXT=m
807 +CONFIG_NET_EMATCH_IPSET=m
808 +CONFIG_NET_CLS_ACT=y
809 +CONFIG_NET_ACT_POLICE=m
810 +CONFIG_NET_ACT_GACT=m
811 +CONFIG_GACT_PROB=y
812 +CONFIG_NET_ACT_MIRRED=m
813 +CONFIG_NET_ACT_IPT=m
814 +CONFIG_NET_ACT_NAT=m
815 +CONFIG_NET_ACT_PEDIT=m
816 +CONFIG_NET_ACT_SIMP=m
817 +CONFIG_NET_ACT_SKBEDIT=m
818 +CONFIG_NET_ACT_CSUM=m
819 +CONFIG_BATMAN_ADV=m
820 +CONFIG_OPENVSWITCH=m
821 +CONFIG_NET_PKTGEN=m
822 +CONFIG_HAMRADIO=y
823 +CONFIG_AX25=m
824 +CONFIG_NETROM=m
825 +CONFIG_ROSE=m
826 +CONFIG_MKISS=m
827 +CONFIG_6PACK=m
828 +CONFIG_BPQETHER=m
829 +CONFIG_BAYCOM_SER_FDX=m
830 +CONFIG_BAYCOM_SER_HDX=m
831 +CONFIG_YAM=m
832 +CONFIG_IRDA=m
833 +CONFIG_IRLAN=m
834 +CONFIG_IRNET=m
835 +CONFIG_IRCOMM=m
836 +CONFIG_IRDA_ULTRA=y
837 +CONFIG_IRDA_CACHE_LAST_LSAP=y
838 +CONFIG_IRDA_FAST_RR=y
839 +CONFIG_IRTTY_SIR=m
840 +CONFIG_KINGSUN_DONGLE=m
841 +CONFIG_KSDAZZLE_DONGLE=m
842 +CONFIG_KS959_DONGLE=m
843 +CONFIG_USB_IRDA=m
844 +CONFIG_SIGMATEL_FIR=m
845 +CONFIG_MCS_FIR=m
846 +CONFIG_BT=m
847 +CONFIG_BT_RFCOMM=m
848 +CONFIG_BT_RFCOMM_TTY=y
849 +CONFIG_BT_BNEP=m
850 +CONFIG_BT_BNEP_MC_FILTER=y
851 +CONFIG_BT_BNEP_PROTO_FILTER=y
852 +CONFIG_BT_HIDP=m
853 +CONFIG_BT_HCIBTUSB=m
854 +CONFIG_BT_HCIBCM203X=m
855 +CONFIG_BT_HCIBPA10X=m
856 +CONFIG_BT_HCIBFUSB=m
857 +CONFIG_BT_HCIVHCI=m
858 +CONFIG_BT_MRVL=m
859 +CONFIG_BT_MRVL_SDIO=m
860 +CONFIG_BT_ATH3K=m
861 +CONFIG_BT_WILINK=m
862 +CONFIG_CFG80211_WEXT=y
863 +CONFIG_MAC80211=m
864 +CONFIG_MAC80211_MESH=y
865 +CONFIG_WIMAX=m
866 +CONFIG_RFKILL=m
867 +CONFIG_RFKILL_INPUT=y
868 +CONFIG_NET_9P=m
869 +CONFIG_NFC=m
870 +CONFIG_NFC_PN533=m
871 +CONFIG_DEVTMPFS=y
872 +CONFIG_DEVTMPFS_MOUNT=y
873 +CONFIG_DMA_CMA=y
874 +CONFIG_CMA_SIZE_MBYTES=5
875 +CONFIG_BLK_DEV_LOOP=y
876 +CONFIG_BLK_DEV_CRYPTOLOOP=m
877 +CONFIG_BLK_DEV_DRBD=m
878 +CONFIG_BLK_DEV_NBD=m
879 +CONFIG_BLK_DEV_RAM=y
880 +CONFIG_CDROM_PKTCDVD=m
881 +CONFIG_EEPROM_AT24=m
882 +CONFIG_SCSI=y
883 +# CONFIG_SCSI_PROC_FS is not set
884 +CONFIG_BLK_DEV_SD=y
885 +CONFIG_CHR_DEV_ST=m
886 +CONFIG_CHR_DEV_OSST=m
887 +CONFIG_BLK_DEV_SR=m
888 +CONFIG_CHR_DEV_SG=m
889 +CONFIG_SCSI_ISCSI_ATTRS=y
890 +CONFIG_ISCSI_TCP=m
891 +CONFIG_ISCSI_BOOT_SYSFS=m
892 +CONFIG_MD=y
893 +CONFIG_MD_LINEAR=m
894 +CONFIG_MD_RAID0=m
895 +CONFIG_BLK_DEV_DM=m
896 +CONFIG_DM_CRYPT=m
897 +CONFIG_DM_SNAPSHOT=m
898 +CONFIG_DM_MIRROR=m
899 +CONFIG_DM_LOG_USERSPACE=m
900 +CONFIG_DM_RAID=m
901 +CONFIG_DM_ZERO=m
902 +CONFIG_DM_DELAY=m
903 +CONFIG_NETDEVICES=y
904 +CONFIG_BONDING=m
905 +CONFIG_DUMMY=m
906 +CONFIG_IFB=m
907 +CONFIG_MACVLAN=m
908 +CONFIG_NETCONSOLE=m
909 +CONFIG_TUN=m
910 +CONFIG_VETH=m
911 +CONFIG_MDIO_BITBANG=m
912 +CONFIG_PPP=m
913 +CONFIG_PPP_BSDCOMP=m
914 +CONFIG_PPP_DEFLATE=m
915 +CONFIG_PPP_FILTER=y
916 +CONFIG_PPP_MPPE=m
917 +CONFIG_PPP_MULTILINK=y
918 +CONFIG_PPPOATM=m
919 +CONFIG_PPPOE=m
920 +CONFIG_PPPOL2TP=m
921 +CONFIG_PPP_ASYNC=m
922 +CONFIG_PPP_SYNC_TTY=m
923 +CONFIG_SLIP=m
924 +CONFIG_SLIP_COMPRESSED=y
925 +CONFIG_SLIP_SMART=y
926 +CONFIG_USB_CATC=m
927 +CONFIG_USB_KAWETH=m
928 +CONFIG_USB_PEGASUS=m
929 +CONFIG_USB_RTL8150=m
930 +CONFIG_USB_RTL8152=m
931 +CONFIG_USB_USBNET=y
932 +CONFIG_USB_NET_AX8817X=m
933 +CONFIG_USB_NET_AX88179_178A=m
934 +CONFIG_USB_NET_CDCETHER=m
935 +CONFIG_USB_NET_CDC_EEM=m
936 +CONFIG_USB_NET_CDC_NCM=m
937 +CONFIG_USB_NET_HUAWEI_CDC_NCM=m
938 +CONFIG_USB_NET_CDC_MBIM=m
939 +CONFIG_USB_NET_DM9601=m
940 +CONFIG_USB_NET_SR9700=m
941 +CONFIG_USB_NET_SR9800=m
942 +CONFIG_USB_NET_SMSC75XX=m
943 +CONFIG_USB_NET_SMSC95XX=y
944 +CONFIG_USB_NET_GL620A=m
945 +CONFIG_USB_NET_NET1080=m
946 +CONFIG_USB_NET_PLUSB=m
947 +CONFIG_USB_NET_MCS7830=m
948 +CONFIG_USB_NET_CDC_SUBSET=m
949 +CONFIG_USB_ALI_M5632=y
950 +CONFIG_USB_AN2720=y
951 +CONFIG_USB_EPSON2888=y
952 +CONFIG_USB_KC2190=y
953 +CONFIG_USB_NET_ZAURUS=m
954 +CONFIG_USB_NET_CX82310_ETH=m
955 +CONFIG_USB_NET_KALMIA=m
956 +CONFIG_USB_NET_QMI_WWAN=m
957 +CONFIG_USB_HSO=m
958 +CONFIG_USB_NET_INT51X1=m
959 +CONFIG_USB_IPHETH=m
960 +CONFIG_USB_SIERRA_NET=m
961 +CONFIG_USB_VL600=m
962 +CONFIG_LIBERTAS_THINFIRM=m
963 +CONFIG_LIBERTAS_THINFIRM_USB=m
964 +CONFIG_AT76C50X_USB=m
965 +CONFIG_USB_ZD1201=m
966 +CONFIG_USB_NET_RNDIS_WLAN=m
967 +CONFIG_RTL8187=m
968 +CONFIG_MAC80211_HWSIM=m
969 +CONFIG_ATH_CARDS=m
970 +CONFIG_ATH9K=m
971 +CONFIG_ATH9K_HTC=m
972 +CONFIG_CARL9170=m
973 +CONFIG_ATH6KL=m
974 +CONFIG_ATH6KL_USB=m
975 +CONFIG_AR5523=m
976 +CONFIG_B43=m
977 +# CONFIG_B43_PHY_N is not set
978 +CONFIG_B43LEGACY=m
979 +CONFIG_BRCMFMAC=m
980 +CONFIG_BRCMFMAC_USB=y
981 +CONFIG_HOSTAP=m
982 +CONFIG_LIBERTAS=m
983 +CONFIG_LIBERTAS_USB=m
984 +CONFIG_LIBERTAS_SDIO=m
985 +CONFIG_P54_COMMON=m
986 +CONFIG_P54_USB=m
987 +CONFIG_RT2X00=m
988 +CONFIG_RT2500USB=m
989 +CONFIG_RT73USB=m
990 +CONFIG_RT2800USB=m
991 +CONFIG_RT2800USB_RT3573=y
992 +CONFIG_RT2800USB_RT53XX=y
993 +CONFIG_RT2800USB_RT55XX=y
994 +CONFIG_RT2800USB_UNKNOWN=y
995 +CONFIG_RTL8192CU=m
996 +CONFIG_ZD1211RW=m
997 +CONFIG_MWIFIEX=m
998 +CONFIG_MWIFIEX_SDIO=m
999 +CONFIG_WIMAX_I2400M_USB=m
1000 +CONFIG_INPUT_POLLDEV=m
1001 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1002 +CONFIG_INPUT_JOYDEV=m
1003 +CONFIG_INPUT_EVDEV=m
1004 +# CONFIG_INPUT_KEYBOARD is not set
1005 +# CONFIG_INPUT_MOUSE is not set
1006 +CONFIG_INPUT_JOYSTICK=y
1007 +CONFIG_JOYSTICK_IFORCE=m
1008 +CONFIG_JOYSTICK_IFORCE_USB=y
1009 +CONFIG_JOYSTICK_XPAD=m
1010 +CONFIG_JOYSTICK_XPAD_FF=y
1011 +CONFIG_INPUT_TOUCHSCREEN=y
1012 +CONFIG_TOUCHSCREEN_ADS7846=m
1013 +CONFIG_INPUT_MISC=y
1014 +CONFIG_INPUT_AD714X=m
1015 +CONFIG_INPUT_ATI_REMOTE2=m
1016 +CONFIG_INPUT_KEYSPAN_REMOTE=m
1017 +CONFIG_INPUT_POWERMATE=m
1018 +CONFIG_INPUT_YEALINK=m
1019 +CONFIG_INPUT_CM109=m
1020 +CONFIG_INPUT_UINPUT=m
1021 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
1022 +CONFIG_INPUT_ADXL34X=m
1023 +CONFIG_INPUT_CMA3000=m
1024 +CONFIG_SERIO=m
1025 +CONFIG_SERIO_RAW=m
1026 +CONFIG_GAMEPORT=m
1027 +CONFIG_GAMEPORT_NS558=m
1028 +CONFIG_GAMEPORT_L4=m
1029 +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
1030 +# CONFIG_LEGACY_PTYS is not set
1031 +# CONFIG_DEVKMEM is not set
1032 +CONFIG_SERIAL_AMBA_PL011=y
1033 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1034 +CONFIG_TTY_PRINTK=y
1035 +CONFIG_HW_RANDOM=y
1036 +CONFIG_HW_RANDOM_BCM2708=m
1037 +CONFIG_RAW_DRIVER=y
1038 +CONFIG_BRCM_CHAR_DRIVERS=y
1039 +CONFIG_BCM_VC_CMA=y
1040 +CONFIG_BCM_VC_SM=y
1041 +CONFIG_I2C=y
1042 +CONFIG_I2C_CHARDEV=m
1043 +CONFIG_I2C_MUX=m
1044 +CONFIG_I2C_BCM2708=m
1045 +CONFIG_SPI=y
1046 +CONFIG_SPI_BCM2708=m
1047 +CONFIG_SPI_SPIDEV=y
1048 +CONFIG_PPS=m
1049 +CONFIG_PPS_CLIENT_LDISC=m
1050 +CONFIG_PPS_CLIENT_GPIO=m
1051 +CONFIG_GPIO_SYSFS=y
1052 +CONFIG_GPIO_ARIZONA=m
1053 +CONFIG_W1=m
1054 +CONFIG_W1_MASTER_DS2490=m
1055 +CONFIG_W1_MASTER_DS2482=m
1056 +CONFIG_W1_MASTER_DS1WM=m
1057 +CONFIG_W1_MASTER_GPIO=m
1058 +CONFIG_W1_SLAVE_THERM=m
1059 +CONFIG_W1_SLAVE_SMEM=m
1060 +CONFIG_W1_SLAVE_DS2408=m
1061 +CONFIG_W1_SLAVE_DS2413=m
1062 +CONFIG_W1_SLAVE_DS2406=m
1063 +CONFIG_W1_SLAVE_DS2423=m
1064 +CONFIG_W1_SLAVE_DS2431=m
1065 +CONFIG_W1_SLAVE_DS2433=m
1066 +CONFIG_W1_SLAVE_DS2760=m
1067 +CONFIG_W1_SLAVE_DS2780=m
1068 +CONFIG_W1_SLAVE_DS2781=m
1069 +CONFIG_W1_SLAVE_DS28E04=m
1070 +CONFIG_W1_SLAVE_BQ27000=m
1071 +CONFIG_BATTERY_DS2760=m
1072 +# CONFIG_HWMON is not set
1073 +CONFIG_THERMAL=y
1074 +CONFIG_THERMAL_BCM2835=y
1075 +CONFIG_WATCHDOG=y
1076 +CONFIG_BCM2708_WDT=m
1077 +CONFIG_UCB1400_CORE=m
1078 +CONFIG_MFD_ARIZONA_I2C=m
1079 +CONFIG_MFD_ARIZONA_SPI=m
1080 +CONFIG_MFD_WM5102=y
1081 +CONFIG_MEDIA_SUPPORT=m
1082 +CONFIG_MEDIA_CAMERA_SUPPORT=y
1083 +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y
1084 +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y
1085 +CONFIG_MEDIA_RADIO_SUPPORT=y
1086 +CONFIG_MEDIA_RC_SUPPORT=y
1087 +CONFIG_MEDIA_CONTROLLER=y
1088 +CONFIG_LIRC=m
1089 +CONFIG_RC_DEVICES=y
1090 +CONFIG_RC_ATI_REMOTE=m
1091 +CONFIG_IR_IMON=m
1092 +CONFIG_IR_MCEUSB=m
1093 +CONFIG_IR_REDRAT3=m
1094 +CONFIG_IR_STREAMZAP=m
1095 +CONFIG_IR_IGUANA=m
1096 +CONFIG_IR_TTUSBIR=m
1097 +CONFIG_RC_LOOPBACK=m
1098 +CONFIG_IR_GPIO_CIR=m
1099 +CONFIG_MEDIA_USB_SUPPORT=y
1100 +CONFIG_USB_VIDEO_CLASS=m
1101 +CONFIG_USB_M5602=m
1102 +CONFIG_USB_STV06XX=m
1103 +CONFIG_USB_GL860=m
1104 +CONFIG_USB_GSPCA_BENQ=m
1105 +CONFIG_USB_GSPCA_CONEX=m
1106 +CONFIG_USB_GSPCA_CPIA1=m
1107 +CONFIG_USB_GSPCA_DTCS033=m
1108 +CONFIG_USB_GSPCA_ETOMS=m
1109 +CONFIG_USB_GSPCA_FINEPIX=m
1110 +CONFIG_USB_GSPCA_JEILINJ=m
1111 +CONFIG_USB_GSPCA_JL2005BCD=m
1112 +CONFIG_USB_GSPCA_KINECT=m
1113 +CONFIG_USB_GSPCA_KONICA=m
1114 +CONFIG_USB_GSPCA_MARS=m
1115 +CONFIG_USB_GSPCA_MR97310A=m
1116 +CONFIG_USB_GSPCA_NW80X=m
1117 +CONFIG_USB_GSPCA_OV519=m
1118 +CONFIG_USB_GSPCA_OV534=m
1119 +CONFIG_USB_GSPCA_OV534_9=m
1120 +CONFIG_USB_GSPCA_PAC207=m
1121 +CONFIG_USB_GSPCA_PAC7302=m
1122 +CONFIG_USB_GSPCA_PAC7311=m
1123 +CONFIG_USB_GSPCA_SE401=m
1124 +CONFIG_USB_GSPCA_SN9C2028=m
1125 +CONFIG_USB_GSPCA_SN9C20X=m
1126 +CONFIG_USB_GSPCA_SONIXB=m
1127 +CONFIG_USB_GSPCA_SONIXJ=m
1128 +CONFIG_USB_GSPCA_SPCA500=m
1129 +CONFIG_USB_GSPCA_SPCA501=m
1130 +CONFIG_USB_GSPCA_SPCA505=m
1131 +CONFIG_USB_GSPCA_SPCA506=m
1132 +CONFIG_USB_GSPCA_SPCA508=m
1133 +CONFIG_USB_GSPCA_SPCA561=m
1134 +CONFIG_USB_GSPCA_SPCA1528=m
1135 +CONFIG_USB_GSPCA_SQ905=m
1136 +CONFIG_USB_GSPCA_SQ905C=m
1137 +CONFIG_USB_GSPCA_SQ930X=m
1138 +CONFIG_USB_GSPCA_STK014=m
1139 +CONFIG_USB_GSPCA_STK1135=m
1140 +CONFIG_USB_GSPCA_STV0680=m
1141 +CONFIG_USB_GSPCA_SUNPLUS=m
1142 +CONFIG_USB_GSPCA_T613=m
1143 +CONFIG_USB_GSPCA_TOPRO=m
1144 +CONFIG_USB_GSPCA_TV8532=m
1145 +CONFIG_USB_GSPCA_VC032X=m
1146 +CONFIG_USB_GSPCA_VICAM=m
1147 +CONFIG_USB_GSPCA_XIRLINK_CIT=m
1148 +CONFIG_USB_GSPCA_ZC3XX=m
1149 +CONFIG_USB_PWC=m
1150 +CONFIG_VIDEO_CPIA2=m
1151 +CONFIG_USB_ZR364XX=m
1152 +CONFIG_USB_STKWEBCAM=m
1153 +CONFIG_USB_S2255=m
1154 +CONFIG_VIDEO_USBTV=m
1155 +CONFIG_VIDEO_PVRUSB2=m
1156 +CONFIG_VIDEO_HDPVR=m
1157 +CONFIG_VIDEO_TLG2300=m
1158 +CONFIG_VIDEO_USBVISION=m
1159 +CONFIG_VIDEO_STK1160_COMMON=m
1160 +CONFIG_VIDEO_STK1160_AC97=y
1161 +CONFIG_VIDEO_GO7007=m
1162 +CONFIG_VIDEO_GO7007_USB=m
1163 +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m
1164 +CONFIG_VIDEO_AU0828=m
1165 +CONFIG_VIDEO_AU0828_RC=y
1166 +CONFIG_VIDEO_CX231XX=m
1167 +CONFIG_VIDEO_CX231XX_ALSA=m
1168 +CONFIG_VIDEO_CX231XX_DVB=m
1169 +CONFIG_VIDEO_TM6000=m
1170 +CONFIG_VIDEO_TM6000_ALSA=m
1171 +CONFIG_VIDEO_TM6000_DVB=m
1172 +CONFIG_DVB_USB=m
1173 +CONFIG_DVB_USB_A800=m
1174 +CONFIG_DVB_USB_DIBUSB_MB=m
1175 +CONFIG_DVB_USB_DIBUSB_MB_FAULTY=y
1176 +CONFIG_DVB_USB_DIBUSB_MC=m
1177 +CONFIG_DVB_USB_DIB0700=m
1178 +CONFIG_DVB_USB_UMT_010=m
1179 +CONFIG_DVB_USB_CXUSB=m
1180 +CONFIG_DVB_USB_M920X=m
1181 +CONFIG_DVB_USB_DIGITV=m
1182 +CONFIG_DVB_USB_VP7045=m
1183 +CONFIG_DVB_USB_VP702X=m
1184 +CONFIG_DVB_USB_GP8PSK=m
1185 +CONFIG_DVB_USB_NOVA_T_USB2=m
1186 +CONFIG_DVB_USB_TTUSB2=m
1187 +CONFIG_DVB_USB_DTT200U=m
1188 +CONFIG_DVB_USB_OPERA1=m
1189 +CONFIG_DVB_USB_AF9005=m
1190 +CONFIG_DVB_USB_AF9005_REMOTE=m
1191 +CONFIG_DVB_USB_PCTV452E=m
1192 +CONFIG_DVB_USB_DW2102=m
1193 +CONFIG_DVB_USB_CINERGY_T2=m
1194 +CONFIG_DVB_USB_DTV5100=m
1195 +CONFIG_DVB_USB_FRIIO=m
1196 +CONFIG_DVB_USB_AZ6027=m
1197 +CONFIG_DVB_USB_TECHNISAT_USB2=m
1198 +CONFIG_DVB_USB_V2=m
1199 +CONFIG_DVB_USB_AF9015=m
1200 +CONFIG_DVB_USB_AF9035=m
1201 +CONFIG_DVB_USB_ANYSEE=m
1202 +CONFIG_DVB_USB_AU6610=m
1203 +CONFIG_DVB_USB_AZ6007=m
1204 +CONFIG_DVB_USB_CE6230=m
1205 +CONFIG_DVB_USB_EC168=m
1206 +CONFIG_DVB_USB_GL861=m
1207 +CONFIG_DVB_USB_LME2510=m
1208 +CONFIG_DVB_USB_MXL111SF=m
1209 +CONFIG_DVB_USB_RTL28XXU=m
1210 +CONFIG_SMS_USB_DRV=m
1211 +CONFIG_DVB_B2C2_FLEXCOP_USB=m
1212 +CONFIG_DVB_AS102=m
1213 +CONFIG_VIDEO_EM28XX=m
1214 +CONFIG_VIDEO_EM28XX_ALSA=m
1215 +CONFIG_VIDEO_EM28XX_DVB=m
1216 +CONFIG_V4L_PLATFORM_DRIVERS=y
1217 +CONFIG_VIDEO_BCM2835=y
1218 +CONFIG_VIDEO_BCM2835_MMAL=m
1219 +CONFIG_RADIO_SI470X=y
1220 +CONFIG_USB_SI470X=m
1221 +CONFIG_I2C_SI470X=m
1222 +CONFIG_RADIO_SI4713=m
1223 +CONFIG_I2C_SI4713=m
1224 +CONFIG_USB_MR800=m
1225 +CONFIG_USB_DSBR=m
1226 +CONFIG_RADIO_SHARK=m
1227 +CONFIG_RADIO_SHARK2=m
1228 +CONFIG_USB_KEENE=m
1229 +CONFIG_USB_MA901=m
1230 +CONFIG_RADIO_TEA5764=m
1231 +CONFIG_RADIO_SAA7706H=m
1232 +CONFIG_RADIO_TEF6862=m
1233 +CONFIG_RADIO_WL1273=m
1234 +CONFIG_RADIO_WL128X=m
1235 +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
1236 +CONFIG_VIDEO_UDA1342=m
1237 +CONFIG_VIDEO_SONY_BTF_MPX=m
1238 +CONFIG_VIDEO_TVP5150=m
1239 +CONFIG_VIDEO_TW2804=m
1240 +CONFIG_VIDEO_TW9903=m
1241 +CONFIG_VIDEO_TW9906=m
1242 +CONFIG_VIDEO_OV7640=m
1243 +CONFIG_VIDEO_MT9V011=m
1244 +CONFIG_FB=y
1245 +CONFIG_FB_BCM2708=y
1246 +# CONFIG_BACKLIGHT_GENERIC is not set
1247 +CONFIG_FRAMEBUFFER_CONSOLE=y
1248 +CONFIG_LOGO=y
1249 +# CONFIG_LOGO_LINUX_MONO is not set
1250 +# CONFIG_LOGO_LINUX_VGA16 is not set
1251 +CONFIG_SOUND=y
1252 +CONFIG_SND=m
1253 +CONFIG_SND_SEQUENCER=m
1254 +CONFIG_SND_SEQ_DUMMY=m
1255 +CONFIG_SND_MIXER_OSS=m
1256 +CONFIG_SND_PCM_OSS=m
1257 +CONFIG_SND_SEQUENCER_OSS=y
1258 +CONFIG_SND_HRTIMER=m
1259 +CONFIG_SND_DUMMY=m
1260 +CONFIG_SND_ALOOP=m
1261 +CONFIG_SND_VIRMIDI=m
1262 +CONFIG_SND_MTPAV=m
1263 +CONFIG_SND_SERIAL_U16550=m
1264 +CONFIG_SND_MPU401=m
1265 +CONFIG_SND_BCM2835=m
1266 +CONFIG_SND_USB_AUDIO=m
1267 +CONFIG_SND_USB_UA101=m
1268 +CONFIG_SND_USB_CAIAQ=m
1269 +CONFIG_SND_USB_CAIAQ_INPUT=y
1270 +CONFIG_SND_USB_6FIRE=m
1271 +CONFIG_SND_SOC=m
1272 +CONFIG_SND_BCM2708_SOC_I2S=m
1273 +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC=m
1274 +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS=m
1275 +CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI=m
1276 +CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP=m
1277 +CONFIG_SND_BCM2708_SOC_RPI_DAC=m
1278 +CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC=m
1279 +CONFIG_SND_SIMPLE_CARD=m
1280 +CONFIG_SOUND_PRIME=m
1281 +CONFIG_HIDRAW=y
1282 +CONFIG_HID_A4TECH=m
1283 +CONFIG_HID_ACRUX=m
1284 +CONFIG_HID_APPLE=m
1285 +CONFIG_HID_BELKIN=m
1286 +CONFIG_HID_CHERRY=m
1287 +CONFIG_HID_CHICONY=m
1288 +CONFIG_HID_CYPRESS=m
1289 +CONFIG_HID_DRAGONRISE=m
1290 +CONFIG_HID_EMS_FF=m
1291 +CONFIG_HID_ELECOM=m
1292 +CONFIG_HID_ELO=m
1293 +CONFIG_HID_EZKEY=m
1294 +CONFIG_HID_HOLTEK=m
1295 +CONFIG_HID_KEYTOUCH=m
1296 +CONFIG_HID_KYE=m
1297 +CONFIG_HID_UCLOGIC=m
1298 +CONFIG_HID_WALTOP=m
1299 +CONFIG_HID_GYRATION=m
1300 +CONFIG_HID_TWINHAN=m
1301 +CONFIG_HID_KENSINGTON=m
1302 +CONFIG_HID_LCPOWER=m
1303 +CONFIG_HID_LOGITECH=m
1304 +CONFIG_HID_MAGICMOUSE=m
1305 +CONFIG_HID_MICROSOFT=m
1306 +CONFIG_HID_MONTEREY=m
1307 +CONFIG_HID_MULTITOUCH=m
1308 +CONFIG_HID_NTRIG=m
1309 +CONFIG_HID_ORTEK=m
1310 +CONFIG_HID_PANTHERLORD=m
1311 +CONFIG_HID_PETALYNX=m
1312 +CONFIG_HID_PICOLCD=m
1313 +CONFIG_HID_ROCCAT=m
1314 +CONFIG_HID_SAMSUNG=m
1315 +CONFIG_HID_SONY=m
1316 +CONFIG_HID_SPEEDLINK=m
1317 +CONFIG_HID_SUNPLUS=m
1318 +CONFIG_HID_GREENASIA=m
1319 +CONFIG_HID_SMARTJOYPLUS=m
1320 +CONFIG_HID_TOPSEED=m
1321 +CONFIG_HID_THINGM=m
1322 +CONFIG_HID_THRUSTMASTER=m
1323 +CONFIG_HID_WACOM=m
1324 +CONFIG_HID_WIIMOTE=m
1325 +CONFIG_HID_XINMO=m
1326 +CONFIG_HID_ZEROPLUS=m
1327 +CONFIG_HID_ZYDACRON=m
1328 +CONFIG_HID_PID=y
1329 +CONFIG_USB_HIDDEV=y
1330 +CONFIG_USB=y
1331 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1332 +CONFIG_USB_MON=m
1333 +CONFIG_USB_DWCOTG=y
1334 +CONFIG_USB_PRINTER=m
1335 +CONFIG_USB_STORAGE=y
1336 +CONFIG_USB_STORAGE_REALTEK=m
1337 +CONFIG_USB_STORAGE_DATAFAB=m
1338 +CONFIG_USB_STORAGE_FREECOM=m
1339 +CONFIG_USB_STORAGE_ISD200=m
1340 +CONFIG_USB_STORAGE_USBAT=m
1341 +CONFIG_USB_STORAGE_SDDR09=m
1342 +CONFIG_USB_STORAGE_SDDR55=m
1343 +CONFIG_USB_STORAGE_JUMPSHOT=m
1344 +CONFIG_USB_STORAGE_ALAUDA=m
1345 +CONFIG_USB_STORAGE_ONETOUCH=m
1346 +CONFIG_USB_STORAGE_KARMA=m
1347 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1348 +CONFIG_USB_STORAGE_ENE_UB6250=m
1349 +CONFIG_USB_UAS=m
1350 +CONFIG_USB_MDC800=m
1351 +CONFIG_USB_MICROTEK=m
1352 +CONFIG_USB_SERIAL=m
1353 +CONFIG_USB_SERIAL_GENERIC=y
1354 +CONFIG_USB_SERIAL_AIRCABLE=m
1355 +CONFIG_USB_SERIAL_ARK3116=m
1356 +CONFIG_USB_SERIAL_BELKIN=m
1357 +CONFIG_USB_SERIAL_CH341=m
1358 +CONFIG_USB_SERIAL_WHITEHEAT=m
1359 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1360 +CONFIG_USB_SERIAL_CP210X=m
1361 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1362 +CONFIG_USB_SERIAL_EMPEG=m
1363 +CONFIG_USB_SERIAL_FTDI_SIO=m
1364 +CONFIG_USB_SERIAL_VISOR=m
1365 +CONFIG_USB_SERIAL_IPAQ=m
1366 +CONFIG_USB_SERIAL_IR=m
1367 +CONFIG_USB_SERIAL_EDGEPORT=m
1368 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1369 +CONFIG_USB_SERIAL_F81232=m
1370 +CONFIG_USB_SERIAL_GARMIN=m
1371 +CONFIG_USB_SERIAL_IPW=m
1372 +CONFIG_USB_SERIAL_IUU=m
1373 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1374 +CONFIG_USB_SERIAL_KEYSPAN=m
1375 +CONFIG_USB_SERIAL_KLSI=m
1376 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1377 +CONFIG_USB_SERIAL_MCT_U232=m
1378 +CONFIG_USB_SERIAL_METRO=m
1379 +CONFIG_USB_SERIAL_MOS7720=m
1380 +CONFIG_USB_SERIAL_MOS7840=m
1381 +CONFIG_USB_SERIAL_NAVMAN=m
1382 +CONFIG_USB_SERIAL_PL2303=m
1383 +CONFIG_USB_SERIAL_OTI6858=m
1384 +CONFIG_USB_SERIAL_QCAUX=m
1385 +CONFIG_USB_SERIAL_QUALCOMM=m
1386 +CONFIG_USB_SERIAL_SPCP8X5=m
1387 +CONFIG_USB_SERIAL_SAFE=m
1388 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1389 +CONFIG_USB_SERIAL_SYMBOL=m
1390 +CONFIG_USB_SERIAL_TI=m
1391 +CONFIG_USB_SERIAL_CYBERJACK=m
1392 +CONFIG_USB_SERIAL_XIRCOM=m
1393 +CONFIG_USB_SERIAL_OPTION=m
1394 +CONFIG_USB_SERIAL_OMNINET=m
1395 +CONFIG_USB_SERIAL_OPTICON=m
1396 +CONFIG_USB_SERIAL_XSENS_MT=m
1397 +CONFIG_USB_SERIAL_WISHBONE=m
1398 +CONFIG_USB_SERIAL_SSU100=m
1399 +CONFIG_USB_SERIAL_QT2=m
1400 +CONFIG_USB_SERIAL_DEBUG=m
1401 +CONFIG_USB_EMI62=m
1402 +CONFIG_USB_EMI26=m
1403 +CONFIG_USB_ADUTUX=m
1404 +CONFIG_USB_SEVSEG=m
1405 +CONFIG_USB_RIO500=m
1406 +CONFIG_USB_LEGOTOWER=m
1407 +CONFIG_USB_LCD=m
1408 +CONFIG_USB_LED=m
1409 +CONFIG_USB_CYPRESS_CY7C63=m
1410 +CONFIG_USB_CYTHERM=m
1411 +CONFIG_USB_IDMOUSE=m
1412 +CONFIG_USB_FTDI_ELAN=m
1413 +CONFIG_USB_APPLEDISPLAY=m
1414 +CONFIG_USB_LD=m
1415 +CONFIG_USB_TRANCEVIBRATOR=m
1416 +CONFIG_USB_IOWARRIOR=m
1417 +CONFIG_USB_TEST=m
1418 +CONFIG_USB_ISIGHTFW=m
1419 +CONFIG_USB_YUREX=m
1420 +CONFIG_USB_ATM=m
1421 +CONFIG_USB_SPEEDTOUCH=m
1422 +CONFIG_USB_CXACRU=m
1423 +CONFIG_USB_UEAGLEATM=m
1424 +CONFIG_USB_XUSBATM=m
1425 +CONFIG_MMC=y
1426 +CONFIG_MMC_BLOCK_MINORS=32
1427 +CONFIG_MMC_SDHCI=y
1428 +CONFIG_MMC_SDHCI_PLTFM=y
1429 +CONFIG_MMC_BCM2835=y
1430 +CONFIG_MMC_BCM2835_DMA=y
1431 +CONFIG_MMC_SPI=m
1432 +CONFIG_LEDS_CLASS=y
1433 +CONFIG_LEDS_GPIO=y
1434 +CONFIG_LEDS_TRIGGER_TIMER=y
1435 +CONFIG_LEDS_TRIGGER_ONESHOT=y
1436 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1437 +CONFIG_LEDS_TRIGGER_BACKLIGHT=y
1438 +CONFIG_LEDS_TRIGGER_CPU=y
1439 +CONFIG_LEDS_TRIGGER_GPIO=y
1440 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
1441 +CONFIG_LEDS_TRIGGER_TRANSIENT=m
1442 +CONFIG_LEDS_TRIGGER_CAMERA=m
1443 +CONFIG_RTC_CLASS=y
1444 +# CONFIG_RTC_HCTOSYS is not set
1445 +CONFIG_RTC_DRV_DS1307=m
1446 +CONFIG_RTC_DRV_DS1374=m
1447 +CONFIG_RTC_DRV_DS1672=m
1448 +CONFIG_RTC_DRV_DS3232=m
1449 +CONFIG_RTC_DRV_MAX6900=m
1450 +CONFIG_RTC_DRV_RS5C372=m
1451 +CONFIG_RTC_DRV_ISL1208=m
1452 +CONFIG_RTC_DRV_ISL12022=m
1453 +CONFIG_RTC_DRV_ISL12057=m
1454 +CONFIG_RTC_DRV_X1205=m
1455 +CONFIG_RTC_DRV_PCF2127=m
1456 +CONFIG_RTC_DRV_PCF8523=m
1457 +CONFIG_RTC_DRV_PCF8563=m
1458 +CONFIG_RTC_DRV_PCF8583=m
1459 +CONFIG_RTC_DRV_M41T80=m
1460 +CONFIG_RTC_DRV_BQ32K=m
1461 +CONFIG_RTC_DRV_S35390A=m
1462 +CONFIG_RTC_DRV_FM3130=m
1463 +CONFIG_RTC_DRV_RX8581=m
1464 +CONFIG_RTC_DRV_RX8025=m
1465 +CONFIG_RTC_DRV_EM3027=m
1466 +CONFIG_RTC_DRV_RV3029C2=m
1467 +CONFIG_RTC_DRV_M41T93=m
1468 +CONFIG_RTC_DRV_M41T94=m
1469 +CONFIG_RTC_DRV_DS1305=m
1470 +CONFIG_RTC_DRV_DS1390=m
1471 +CONFIG_RTC_DRV_MAX6902=m
1472 +CONFIG_RTC_DRV_R9701=m
1473 +CONFIG_RTC_DRV_RS5C348=m
1474 +CONFIG_RTC_DRV_DS3234=m
1475 +CONFIG_RTC_DRV_PCF2123=m
1476 +CONFIG_RTC_DRV_RX4581=m
1477 +CONFIG_DMADEVICES=y
1478 +CONFIG_DMA_BCM2708=y
1479 +CONFIG_UIO=m
1480 +CONFIG_UIO_PDRV_GENIRQ=m
1481 +CONFIG_STAGING=y
1482 +CONFIG_PRISM2_USB=m
1483 +CONFIG_R8712U=m
1484 +CONFIG_R8188EU=m
1485 +CONFIG_R8723AU=m
1486 +CONFIG_VT6656=m
1487 +CONFIG_SPEAKUP=m
1488 +CONFIG_SPEAKUP_SYNTH_SOFT=m
1489 +CONFIG_STAGING_MEDIA=y
1490 +CONFIG_LIRC_STAGING=y
1491 +CONFIG_LIRC_IGORPLUGUSB=m
1492 +CONFIG_LIRC_IMON=m
1493 +CONFIG_LIRC_RPI=m
1494 +CONFIG_LIRC_SASEM=m
1495 +CONFIG_LIRC_SERIAL=m
1496 +# CONFIG_IOMMU_SUPPORT is not set
1497 +CONFIG_EXTCON=m
1498 +CONFIG_EXTCON_ARIZONA=m
1499 +CONFIG_EXT4_FS=y
1500 +CONFIG_EXT4_FS_POSIX_ACL=y
1501 +CONFIG_EXT4_FS_SECURITY=y
1502 +CONFIG_REISERFS_FS=m
1503 +CONFIG_REISERFS_FS_XATTR=y
1504 +CONFIG_REISERFS_FS_POSIX_ACL=y
1505 +CONFIG_REISERFS_FS_SECURITY=y
1506 +CONFIG_JFS_FS=m
1507 +CONFIG_JFS_POSIX_ACL=y
1508 +CONFIG_JFS_SECURITY=y
1509 +CONFIG_JFS_STATISTICS=y
1510 +CONFIG_XFS_FS=m
1511 +CONFIG_XFS_QUOTA=y
1512 +CONFIG_XFS_POSIX_ACL=y
1513 +CONFIG_XFS_RT=y
1514 +CONFIG_GFS2_FS=m
1515 +CONFIG_OCFS2_FS=m
1516 +CONFIG_BTRFS_FS=m
1517 +CONFIG_BTRFS_FS_POSIX_ACL=y
1518 +CONFIG_NILFS2_FS=m
1519 +CONFIG_FANOTIFY=y
1520 +CONFIG_QFMT_V1=m
1521 +CONFIG_QFMT_V2=m
1522 +CONFIG_AUTOFS4_FS=y
1523 +CONFIG_FUSE_FS=m
1524 +CONFIG_CUSE=m
1525 +CONFIG_FSCACHE=y
1526 +CONFIG_FSCACHE_STATS=y
1527 +CONFIG_FSCACHE_HISTOGRAM=y
1528 +CONFIG_CACHEFILES=y
1529 +CONFIG_ISO9660_FS=m
1530 +CONFIG_JOLIET=y
1531 +CONFIG_ZISOFS=y
1532 +CONFIG_UDF_FS=m
1533 +CONFIG_MSDOS_FS=y
1534 +CONFIG_VFAT_FS=y
1535 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1536 +CONFIG_NTFS_FS=m
1537 +CONFIG_NTFS_RW=y
1538 +CONFIG_TMPFS=y
1539 +CONFIG_TMPFS_POSIX_ACL=y
1540 +CONFIG_CONFIGFS_FS=y
1541 +CONFIG_ECRYPT_FS=m
1542 +CONFIG_HFS_FS=m
1543 +CONFIG_HFSPLUS_FS=m
1544 +CONFIG_SQUASHFS=m
1545 +CONFIG_SQUASHFS_XATTR=y
1546 +CONFIG_SQUASHFS_LZO=y
1547 +CONFIG_SQUASHFS_XZ=y
1548 +CONFIG_F2FS_FS=y
1549 +CONFIG_NFS_FS=y
1550 +CONFIG_NFS_V3_ACL=y
1551 +CONFIG_NFS_V4=y
1552 +CONFIG_NFS_SWAP=y
1553 +CONFIG_ROOT_NFS=y
1554 +CONFIG_NFS_FSCACHE=y
1555 +CONFIG_NFSD=m
1556 +CONFIG_NFSD_V3_ACL=y
1557 +CONFIG_NFSD_V4=y
1558 +CONFIG_CIFS=m
1559 +CONFIG_CIFS_WEAK_PW_HASH=y
1560 +CONFIG_CIFS_XATTR=y
1561 +CONFIG_CIFS_POSIX=y
1562 +CONFIG_9P_FS=m
1563 +CONFIG_9P_FS_POSIX_ACL=y
1564 +CONFIG_NLS_DEFAULT="utf8"
1565 +CONFIG_NLS_CODEPAGE_437=y
1566 +CONFIG_NLS_CODEPAGE_737=m
1567 +CONFIG_NLS_CODEPAGE_775=m
1568 +CONFIG_NLS_CODEPAGE_850=m
1569 +CONFIG_NLS_CODEPAGE_852=m
1570 +CONFIG_NLS_CODEPAGE_855=m
1571 +CONFIG_NLS_CODEPAGE_857=m
1572 +CONFIG_NLS_CODEPAGE_860=m
1573 +CONFIG_NLS_CODEPAGE_861=m
1574 +CONFIG_NLS_CODEPAGE_862=m
1575 +CONFIG_NLS_CODEPAGE_863=m
1576 +CONFIG_NLS_CODEPAGE_864=m
1577 +CONFIG_NLS_CODEPAGE_865=m
1578 +CONFIG_NLS_CODEPAGE_866=m
1579 +CONFIG_NLS_CODEPAGE_869=m
1580 +CONFIG_NLS_CODEPAGE_936=m
1581 +CONFIG_NLS_CODEPAGE_950=m
1582 +CONFIG_NLS_CODEPAGE_932=m
1583 +CONFIG_NLS_CODEPAGE_949=m
1584 +CONFIG_NLS_CODEPAGE_874=m
1585 +CONFIG_NLS_ISO8859_8=m
1586 +CONFIG_NLS_CODEPAGE_1250=m
1587 +CONFIG_NLS_CODEPAGE_1251=m
1588 +CONFIG_NLS_ASCII=y
1589 +CONFIG_NLS_ISO8859_1=m
1590 +CONFIG_NLS_ISO8859_2=m
1591 +CONFIG_NLS_ISO8859_3=m
1592 +CONFIG_NLS_ISO8859_4=m
1593 +CONFIG_NLS_ISO8859_5=m
1594 +CONFIG_NLS_ISO8859_6=m
1595 +CONFIG_NLS_ISO8859_7=m
1596 +CONFIG_NLS_ISO8859_9=m
1597 +CONFIG_NLS_ISO8859_13=m
1598 +CONFIG_NLS_ISO8859_14=m
1599 +CONFIG_NLS_ISO8859_15=m
1600 +CONFIG_NLS_KOI8_R=m
1601 +CONFIG_NLS_KOI8_U=m
1602 +CONFIG_DLM=m
1603 +CONFIG_PRINTK_TIME=y
1604 +CONFIG_BOOT_PRINTK_DELAY=y
1605 +CONFIG_DEBUG_MEMORY_INIT=y
1606 +CONFIG_DETECT_HUNG_TASK=y
1607 +CONFIG_TIMER_STATS=y
1608 +# CONFIG_DEBUG_PREEMPT is not set
1609 +CONFIG_IRQSOFF_TRACER=y
1610 +CONFIG_SCHED_TRACER=y
1611 +CONFIG_STACK_TRACER=y
1612 +CONFIG_BLK_DEV_IO_TRACE=y
1613 +# CONFIG_KPROBE_EVENT is not set
1614 +CONFIG_FUNCTION_PROFILER=y
1615 +CONFIG_KGDB=y
1616 +CONFIG_KGDB_KDB=y
1617 +CONFIG_KDB_KEYBOARD=y
1618 +CONFIG_CRYPTO_USER=m
1619 +CONFIG_CRYPTO_NULL=m
1620 +CONFIG_CRYPTO_CBC=y
1621 +CONFIG_CRYPTO_CTS=m
1622 +CONFIG_CRYPTO_XTS=m
1623 +CONFIG_CRYPTO_XCBC=m
1624 +CONFIG_CRYPTO_SHA1_ARM_NEON=m
1625 +CONFIG_CRYPTO_SHA512_ARM_NEON=m
1626 +CONFIG_CRYPTO_TGR192=m
1627 +CONFIG_CRYPTO_WP512=m
1628 +CONFIG_CRYPTO_AES_ARM_BS=m
1629 +CONFIG_CRYPTO_CAST5=m
1630 +CONFIG_CRYPTO_DES=y
1631 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1632 +# CONFIG_CRYPTO_HW is not set
1633 +CONFIG_CRC_ITU_T=y
1634 +CONFIG_LIBCRC32C=y
1635 diff --git a/arch/arm/configs/bcm2709_sdcard_defconfig b/arch/arm/configs/bcm2709_sdcard_defconfig
1636 new file mode 100644
1637 index 0000000..287b15d
1638 --- /dev/null
1639 +++ b/arch/arm/configs/bcm2709_sdcard_defconfig
1640 @@ -0,0 +1,129 @@
1641 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
1642 +CONFIG_PHYS_OFFSET=0x0
1643 +CONFIG_LOCALVERSION="-sdcard"
1644 +# CONFIG_LOCALVERSION_AUTO is not set
1645 +# CONFIG_SWAP is not set
1646 +CONFIG_SYSVIPC=y
1647 +CONFIG_POSIX_MQUEUE=y
1648 +CONFIG_FHANDLE=y
1649 +CONFIG_AUDIT=y
1650 +CONFIG_NO_HZ=y
1651 +CONFIG_HIGH_RES_TIMERS=y
1652 +CONFIG_BSD_PROCESS_ACCT=y
1653 +CONFIG_BSD_PROCESS_ACCT_V3=y
1654 +CONFIG_TASKSTATS=y
1655 +CONFIG_TASK_DELAY_ACCT=y
1656 +CONFIG_TASK_XACCT=y
1657 +CONFIG_TASK_IO_ACCOUNTING=y
1658 +CONFIG_IKCONFIG=y
1659 +CONFIG_IKCONFIG_PROC=y
1660 +CONFIG_CGROUP_FREEZER=y
1661 +CONFIG_CGROUP_DEVICE=y
1662 +CONFIG_CGROUP_CPUACCT=y
1663 +CONFIG_RESOURCE_COUNTERS=y
1664 +CONFIG_MEMCG=y
1665 +CONFIG_BLK_CGROUP=y
1666 +CONFIG_NAMESPACES=y
1667 +CONFIG_SCHED_AUTOGROUP=y
1668 +CONFIG_RELAY=y
1669 +CONFIG_BLK_DEV_INITRD=y
1670 +CONFIG_EMBEDDED=y
1671 +# CONFIG_PERF_EVENTS is not set
1672 +# CONFIG_COMPAT_BRK is not set
1673 +CONFIG_PROFILING=y
1674 +CONFIG_JUMP_LABEL=y
1675 +CONFIG_BLK_DEV_BSGLIB=y
1676 +CONFIG_BLK_DEV_THROTTLING=y
1677 +CONFIG_CFQ_GROUP_IOSCHED=y
1678 +CONFIG_ARCH_BCM2709=y
1679 +# CONFIG_CACHE_L2X0 is not set
1680 +CONFIG_SMP=y
1681 +CONFIG_HAVE_ARM_ARCH_TIMER=y
1682 +CONFIG_HOTPLUG_CPU=y
1683 +CONFIG_PREEMPT=y
1684 +CONFIG_AEABI=y
1685 +CONFIG_CMA=y
1686 +CONFIG_UACCESS_WITH_MEMCPY=y
1687 +CONFIG_SECCOMP=y
1688 +CONFIG_ZBOOT_ROM_TEXT=0x0
1689 +CONFIG_ZBOOT_ROM_BSS=0x0
1690 +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
1691 +CONFIG_CPU_IDLE=y
1692 +CONFIG_VFP=y
1693 +# CONFIG_COREDUMP is not set
1694 +# CONFIG_SUSPEND is not set
1695 +CONFIG_NET=y
1696 +CONFIG_UNIX=y
1697 +CONFIG_CGROUP_NET_CLASSID=y
1698 +# CONFIG_WIRELESS is not set
1699 +CONFIG_DEVTMPFS=y
1700 +CONFIG_DEVTMPFS_MOUNT=y
1701 +CONFIG_DMA_CMA=y
1702 +CONFIG_CMA_SIZE_MBYTES=8
1703 +CONFIG_BLK_DEV_LOOP=y
1704 +CONFIG_BLK_DEV_RAM=y
1705 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1706 +# CONFIG_INPUT_KEYBOARD is not set
1707 +# CONFIG_INPUT_MOUSE is not set
1708 +# CONFIG_SERIO is not set
1709 +# CONFIG_LEGACY_PTYS is not set
1710 +# CONFIG_DEVKMEM is not set
1711 +CONFIG_SERIAL_AMBA_PL011=y
1712 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1713 +CONFIG_TTY_PRINTK=y
1714 +# CONFIG_HW_RANDOM is not set
1715 +CONFIG_BRCM_CHAR_DRIVERS=y
1716 +CONFIG_BCM_VC_CMA=y
1717 +CONFIG_GPIO_SYSFS=y
1718 +# CONFIG_HWMON is not set
1719 +CONFIG_FB=y
1720 +CONFIG_FB_BCM2708=y
1721 +CONFIG_FRAMEBUFFER_CONSOLE=y
1722 +# CONFIG_HID is not set
1723 +# CONFIG_USB_SUPPORT is not set
1724 +CONFIG_MMC=y
1725 +CONFIG_MMC_BLOCK_MINORS=32
1726 +CONFIG_MMC_SDHCI=y
1727 +CONFIG_MMC_SDHCI_PLTFM=y
1728 +CONFIG_MMC_BCM2835=y
1729 +CONFIG_MMC_BCM2835_DMA=y
1730 +CONFIG_DMADEVICES=y
1731 +CONFIG_DMA_BCM2708=y
1732 +# CONFIG_IOMMU_SUPPORT is not set
1733 +CONFIG_EXT4_FS=y
1734 +CONFIG_EXT4_FS_POSIX_ACL=y
1735 +CONFIG_EXT4_FS_SECURITY=y
1736 +CONFIG_FANOTIFY=y
1737 +CONFIG_FSCACHE=y
1738 +CONFIG_FSCACHE_STATS=y
1739 +CONFIG_FSCACHE_HISTOGRAM=y
1740 +CONFIG_CACHEFILES=y
1741 +CONFIG_MSDOS_FS=y
1742 +CONFIG_VFAT_FS=y
1743 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1744 +CONFIG_TMPFS=y
1745 +CONFIG_TMPFS_POSIX_ACL=y
1746 +CONFIG_CONFIGFS_FS=y
1747 +# CONFIG_MISC_FILESYSTEMS is not set
1748 +# CONFIG_NETWORK_FILESYSTEMS is not set
1749 +CONFIG_NLS_DEFAULT="utf8"
1750 +CONFIG_NLS_CODEPAGE_437=y
1751 +CONFIG_NLS_ASCII=y
1752 +CONFIG_PRINTK_TIME=y
1753 +CONFIG_BOOT_PRINTK_DELAY=y
1754 +CONFIG_DEBUG_FS=y
1755 +CONFIG_MAGIC_SYSRQ=y
1756 +CONFIG_DETECT_HUNG_TASK=y
1757 +CONFIG_TIMER_STATS=y
1758 +# CONFIG_DEBUG_PREEMPT is not set
1759 +CONFIG_DEBUG_LL=y
1760 +CONFIG_EARLY_PRINTK=y
1761 +CONFIG_KEYS=y
1762 +CONFIG_CRYPTO_CBC=y
1763 +CONFIG_CRYPTO_AES=y
1764 +CONFIG_CRYPTO_DES=y
1765 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1766 +# CONFIG_CRYPTO_HW is not set
1767 +CONFIG_CRC_ITU_T=y
1768 +CONFIG_LIBCRC32C=y
1769 +CONFIG_AVERAGE=y
1770 diff --git a/arch/arm/configs/bcm2709_small_defconfig b/arch/arm/configs/bcm2709_small_defconfig
1771 new file mode 100644
1772 index 0000000..9974a9d
1773 --- /dev/null
1774 +++ b/arch/arm/configs/bcm2709_small_defconfig
1775 @@ -0,0 +1,61 @@
1776 +CONFIG_LOCALVERSION="-small"
1777 +# CONFIG_LOCALVERSION_AUTO is not set
1778 +# CONFIG_SWAP is not set
1779 +CONFIG_SYSVIPC=y
1780 +CONFIG_HIGH_RES_TIMERS=y
1781 +CONFIG_LOG_BUF_SHIFT=16
1782 +CONFIG_BLK_DEV_INITRD=y
1783 +CONFIG_INITRAMFS_SOURCE="../target_fs"
1784 +CONFIG_SLAB=y
1785 +# CONFIG_BLK_DEV_BSG is not set
1786 +# CONFIG_IOSCHED_CFQ is not set
1787 +CONFIG_ARCH_BCM2709=y
1788 +# CONFIG_BCM2708_GPIO is not set
1789 +# CONFIG_BCM2708_VCMEM is not set
1790 +CONFIG_ARM_THUMBEE=y
1791 +# CONFIG_SWP_EMULATE is not set
1792 +# CONFIG_CACHE_L2X0 is not set
1793 +CONFIG_ARM_ERRATA_720789=y
1794 +CONFIG_SMP=y
1795 +CONFIG_SCHED_MC=y
1796 +CONFIG_SCHED_SMT=y
1797 +CONFIG_HOTPLUG_CPU=y
1798 +CONFIG_PREEMPT=y
1799 +CONFIG_AEABI=y
1800 +CONFIG_HIGHMEM=y
1801 +CONFIG_HIGHPTE=y
1802 +# CONFIG_COMPACTION is not set
1803 +CONFIG_ZBOOT_ROM_TEXT=0x0
1804 +CONFIG_ZBOOT_ROM_BSS=0x0
1805 +CONFIG_CMDLINE="earlyprintk=ttyAMA0,19200 loglevel=9 console=ttyAMA0,19200"
1806 +CONFIG_AUTO_ZRELADDR=y
1807 +CONFIG_BINFMT_MISC=y
1808 +# CONFIG_SUSPEND is not set
1809 +# CONFIG_UEVENT_HELPER is not set
1810 +# CONFIG_FIRMWARE_IN_KERNEL is not set
1811 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1812 +# CONFIG_INPUT_KEYBOARD is not set
1813 +# CONFIG_INPUT_MOUSE is not set
1814 +# CONFIG_SERIO is not set
1815 +# CONFIG_LEGACY_PTYS is not set
1816 +# CONFIG_DEVKMEM is not set
1817 +CONFIG_SERIAL_AMBA_PL011=y
1818 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1819 +# CONFIG_HW_RANDOM is not set
1820 +# CONFIG_HWMON is not set
1821 +# CONFIG_HID is not set
1822 +# CONFIG_USB_SUPPORT is not set
1823 +# CONFIG_IOMMU_SUPPORT is not set
1824 +CONFIG_AUTOFS4_FS=y
1825 +# CONFIG_MISC_FILESYSTEMS is not set
1826 +CONFIG_PRINTK_TIME=y
1827 +CONFIG_FRAME_WARN=4096
1828 +CONFIG_MAGIC_SYSRQ=y
1829 +CONFIG_DEBUG_KERNEL=y
1830 +CONFIG_RCU_CPU_STALL_TIMEOUT=60
1831 +# CONFIG_FTRACE is not set
1832 +# CONFIG_ARM_UNWIND is not set
1833 +CONFIG_DEBUG_LL=y
1834 +CONFIG_EARLY_PRINTK=y
1835 +CONFIG_CRC16=y
1836 +CONFIG_CRC_ITU_T=y
1837 diff --git a/arch/arm/configs/bcm2835_sdcard_defconfig b/arch/arm/configs/bcm2835_sdcard_defconfig
1838 new file mode 100644
1839 index 0000000..987471b
1840 --- /dev/null
1841 +++ b/arch/arm/configs/bcm2835_sdcard_defconfig
1842 @@ -0,0 +1,176 @@
1843 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
1844 +CONFIG_LOCALVERSION="-quick"
1845 +# CONFIG_LOCALVERSION_AUTO is not set
1846 +# CONFIG_SWAP is not set
1847 +CONFIG_SYSVIPC=y
1848 +CONFIG_POSIX_MQUEUE=y
1849 +CONFIG_NO_HZ=y
1850 +CONFIG_HIGH_RES_TIMERS=y
1851 +CONFIG_IKCONFIG=y
1852 +CONFIG_IKCONFIG_PROC=y
1853 +CONFIG_KALLSYMS_ALL=y
1854 +CONFIG_EMBEDDED=y
1855 +CONFIG_PERF_EVENTS=y
1856 +# CONFIG_COMPAT_BRK is not set
1857 +CONFIG_SLAB=y
1858 +# CONFIG_BLK_DEV_BSG is not set
1859 +CONFIG_ARCH_BCM2708=y
1860 +# CONFIG_BCM2708_GPIO is not set
1861 +CONFIG_PREEMPT=y
1862 +CONFIG_AEABI=y
1863 +CONFIG_UACCESS_WITH_MEMCPY=y
1864 +CONFIG_ZBOOT_ROM_TEXT=0x0
1865 +CONFIG_ZBOOT_ROM_BSS=0x0
1866 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
1867 +CONFIG_CPU_FREQ=y
1868 +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
1869 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
1870 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
1871 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
1872 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
1873 +CONFIG_CPU_IDLE=y
1874 +CONFIG_VFP=y
1875 +CONFIG_BINFMT_MISC=y
1876 +CONFIG_NET=y
1877 +CONFIG_PACKET=y
1878 +CONFIG_UNIX=y
1879 +CONFIG_INET=y
1880 +CONFIG_IP_MULTICAST=y
1881 +CONFIG_IP_PNP=y
1882 +CONFIG_IP_PNP_DHCP=y
1883 +CONFIG_IP_PNP_RARP=y
1884 +CONFIG_SYN_COOKIES=y
1885 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1886 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1887 +# CONFIG_INET_XFRM_MODE_BEET is not set
1888 +# CONFIG_INET_LRO is not set
1889 +# CONFIG_INET_DIAG is not set
1890 +# CONFIG_IPV6 is not set
1891 +# CONFIG_WIRELESS is not set
1892 +CONFIG_DEVTMPFS=y
1893 +CONFIG_DEVTMPFS_MOUNT=y
1894 +CONFIG_BLK_DEV_LOOP=y
1895 +CONFIG_BLK_DEV_RAM=y
1896 +CONFIG_SCSI=y
1897 +# CONFIG_SCSI_PROC_FS is not set
1898 +# CONFIG_SCSI_LOWLEVEL is not set
1899 +CONFIG_NETDEVICES=y
1900 +CONFIG_MII=y
1901 +# CONFIG_NET_VENDOR_BROADCOM is not set
1902 +# CONFIG_NET_VENDOR_CIRRUS is not set
1903 +# CONFIG_NET_VENDOR_FARADAY is not set
1904 +# CONFIG_NET_VENDOR_INTEL is not set
1905 +# CONFIG_NET_VENDOR_MARVELL is not set
1906 +# CONFIG_NET_VENDOR_MICREL is not set
1907 +# CONFIG_NET_VENDOR_NATSEMI is not set
1908 +# CONFIG_NET_VENDOR_SEEQ is not set
1909 +# CONFIG_NET_VENDOR_STMICRO is not set
1910 +# CONFIG_NET_VENDOR_WIZNET is not set
1911 +CONFIG_PHYLIB=y
1912 +# CONFIG_WLAN is not set
1913 +# CONFIG_INPUT_MOUSEDEV is not set
1914 +CONFIG_INPUT_EVDEV=y
1915 +# CONFIG_INPUT_KEYBOARD is not set
1916 +# CONFIG_INPUT_MOUSE is not set
1917 +# CONFIG_SERIO is not set
1918 +CONFIG_VT_HW_CONSOLE_BINDING=y
1919 +# CONFIG_LEGACY_PTYS is not set
1920 +# CONFIG_DEVKMEM is not set
1921 +CONFIG_SERIAL_AMBA_PL011=y
1922 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1923 +CONFIG_TTY_PRINTK=y
1924 +CONFIG_RAW_DRIVER=y
1925 +CONFIG_WATCHDOG=y
1926 +CONFIG_REGULATOR=y
1927 +CONFIG_REGULATOR_DEBUG=y
1928 +CONFIG_REGULATOR_FIXED_VOLTAGE=y
1929 +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
1930 +CONFIG_REGULATOR_USERSPACE_CONSUMER=y
1931 +CONFIG_FB=y
1932 +CONFIG_FRAMEBUFFER_CONSOLE=y
1933 +CONFIG_LOGO=y
1934 +# CONFIG_LOGO_LINUX_MONO is not set
1935 +# CONFIG_LOGO_LINUX_VGA16 is not set
1936 +CONFIG_SOUND=y
1937 +CONFIG_SND=y
1938 +CONFIG_MMC=y
1939 +CONFIG_MMC_SDHCI=y
1940 +CONFIG_MMC_SDHCI_PLTFM=y
1941 +CONFIG_MMC_SDHCI_BCM2708=y
1942 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1943 +CONFIG_NEW_LEDS=y
1944 +CONFIG_LEDS_CLASS=y
1945 +CONFIG_LEDS_TRIGGERS=y
1946 +# CONFIG_IOMMU_SUPPORT is not set
1947 +CONFIG_EXT4_FS=y
1948 +CONFIG_EXT4_FS_POSIX_ACL=y
1949 +CONFIG_EXT4_FS_SECURITY=y
1950 +CONFIG_AUTOFS4_FS=y
1951 +CONFIG_FSCACHE=y
1952 +CONFIG_CACHEFILES=y
1953 +CONFIG_MSDOS_FS=y
1954 +CONFIG_VFAT_FS=y
1955 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1956 +CONFIG_TMPFS=y
1957 +CONFIG_TMPFS_POSIX_ACL=y
1958 +CONFIG_CONFIGFS_FS=y
1959 +# CONFIG_MISC_FILESYSTEMS is not set
1960 +CONFIG_NFS_FS=y
1961 +CONFIG_NFS_V3_ACL=y
1962 +CONFIG_NFS_V4=y
1963 +CONFIG_ROOT_NFS=y
1964 +CONFIG_NFS_FSCACHE=y
1965 +CONFIG_NLS_DEFAULT="utf8"
1966 +CONFIG_NLS_CODEPAGE_437=y
1967 +CONFIG_NLS_CODEPAGE_737=y
1968 +CONFIG_NLS_CODEPAGE_775=y
1969 +CONFIG_NLS_CODEPAGE_850=y
1970 +CONFIG_NLS_CODEPAGE_852=y
1971 +CONFIG_NLS_CODEPAGE_855=y
1972 +CONFIG_NLS_CODEPAGE_857=y
1973 +CONFIG_NLS_CODEPAGE_860=y
1974 +CONFIG_NLS_CODEPAGE_861=y
1975 +CONFIG_NLS_CODEPAGE_862=y
1976 +CONFIG_NLS_CODEPAGE_863=y
1977 +CONFIG_NLS_CODEPAGE_864=y
1978 +CONFIG_NLS_CODEPAGE_865=y
1979 +CONFIG_NLS_CODEPAGE_866=y
1980 +CONFIG_NLS_CODEPAGE_869=y
1981 +CONFIG_NLS_CODEPAGE_936=y
1982 +CONFIG_NLS_CODEPAGE_950=y
1983 +CONFIG_NLS_CODEPAGE_932=y
1984 +CONFIG_NLS_CODEPAGE_949=y
1985 +CONFIG_NLS_CODEPAGE_874=y
1986 +CONFIG_NLS_ISO8859_8=y
1987 +CONFIG_NLS_CODEPAGE_1250=y
1988 +CONFIG_NLS_CODEPAGE_1251=y
1989 +CONFIG_NLS_ASCII=y
1990 +CONFIG_NLS_ISO8859_1=y
1991 +CONFIG_NLS_ISO8859_2=y
1992 +CONFIG_NLS_ISO8859_3=y
1993 +CONFIG_NLS_ISO8859_4=y
1994 +CONFIG_NLS_ISO8859_5=y
1995 +CONFIG_NLS_ISO8859_6=y
1996 +CONFIG_NLS_ISO8859_7=y
1997 +CONFIG_NLS_ISO8859_9=y
1998 +CONFIG_NLS_ISO8859_13=y
1999 +CONFIG_NLS_ISO8859_14=y
2000 +CONFIG_NLS_ISO8859_15=y
2001 +CONFIG_NLS_UTF8=y
2002 +CONFIG_PRINTK_TIME=y
2003 +CONFIG_DEBUG_FS=y
2004 +# CONFIG_DEBUG_PREEMPT is not set
2005 +# CONFIG_DEBUG_BUGVERBOSE is not set
2006 +# CONFIG_FTRACE is not set
2007 +CONFIG_KGDB=y
2008 +CONFIG_KGDB_KDB=y
2009 +# CONFIG_ARM_UNWIND is not set
2010 +CONFIG_CRYPTO_CBC=y
2011 +CONFIG_CRYPTO_HMAC=y
2012 +CONFIG_CRYPTO_MD5=y
2013 +CONFIG_CRYPTO_SHA1=y
2014 +CONFIG_CRYPTO_DES=y
2015 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
2016 +# CONFIG_CRYPTO_HW is not set
2017 +CONFIG_CRC_ITU_T=y
2018 +CONFIG_LIBCRC32C=y
2019 diff --git a/arch/arm/configs/bcmrpi_sdcard_defconfig b/arch/arm/configs/bcmrpi_sdcard_defconfig
2020 new file mode 100644
2021 index 0000000..fef887a
2022 --- /dev/null
2023 +++ b/arch/arm/configs/bcmrpi_sdcard_defconfig
2024 @@ -0,0 +1,176 @@
2025 +# CONFIG_ARM_PATCH_PHYS_VIRT is not set
2026 +CONFIG_LOCALVERSION="-quick"
2027 +# CONFIG_LOCALVERSION_AUTO is not set
2028 +# CONFIG_SWAP is not set
2029 +CONFIG_SYSVIPC=y
2030 +CONFIG_POSIX_MQUEUE=y
2031 +CONFIG_NO_HZ=y
2032 +CONFIG_HIGH_RES_TIMERS=y
2033 +CONFIG_IKCONFIG=y
2034 +CONFIG_IKCONFIG_PROC=y
2035 +CONFIG_KALLSYMS_ALL=y
2036 +CONFIG_EMBEDDED=y
2037 +CONFIG_PERF_EVENTS=y
2038 +# CONFIG_COMPAT_BRK is not set
2039 +CONFIG_SLAB=y
2040 +# CONFIG_BLK_DEV_BSG is not set
2041 +CONFIG_ARCH_BCM2708=y
2042 +CONFIG_PREEMPT=y
2043 +CONFIG_AEABI=y
2044 +CONFIG_UACCESS_WITH_MEMCPY=y
2045 +CONFIG_ZBOOT_ROM_TEXT=0x0
2046 +CONFIG_ZBOOT_ROM_BSS=0x0
2047 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
2048 +CONFIG_CPU_FREQ=y
2049 +CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y
2050 +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
2051 +CONFIG_CPU_FREQ_GOV_USERSPACE=y
2052 +CONFIG_CPU_FREQ_GOV_ONDEMAND=y
2053 +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
2054 +CONFIG_CPU_IDLE=y
2055 +CONFIG_VFP=y
2056 +CONFIG_BINFMT_MISC=y
2057 +CONFIG_NET=y
2058 +CONFIG_PACKET=y
2059 +CONFIG_UNIX=y
2060 +CONFIG_INET=y
2061 +CONFIG_IP_MULTICAST=y
2062 +CONFIG_IP_PNP=y
2063 +CONFIG_IP_PNP_DHCP=y
2064 +CONFIG_IP_PNP_RARP=y
2065 +CONFIG_SYN_COOKIES=y
2066 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
2067 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
2068 +# CONFIG_INET_XFRM_MODE_BEET is not set
2069 +# CONFIG_INET_LRO is not set
2070 +# CONFIG_INET_DIAG is not set
2071 +# CONFIG_IPV6 is not set
2072 +# CONFIG_WIRELESS is not set
2073 +CONFIG_DEVTMPFS=y
2074 +CONFIG_DEVTMPFS_MOUNT=y
2075 +CONFIG_BLK_DEV_LOOP=y
2076 +CONFIG_BLK_DEV_RAM=y
2077 +CONFIG_SCSI=y
2078 +# CONFIG_SCSI_PROC_FS is not set
2079 +# CONFIG_SCSI_LOWLEVEL is not set
2080 +CONFIG_NETDEVICES=y
2081 +CONFIG_MII=y
2082 +# CONFIG_NET_VENDOR_BROADCOM is not set
2083 +# CONFIG_NET_VENDOR_CIRRUS is not set
2084 +# CONFIG_NET_VENDOR_FARADAY is not set
2085 +# CONFIG_NET_VENDOR_INTEL is not set
2086 +# CONFIG_NET_VENDOR_MARVELL is not set
2087 +# CONFIG_NET_VENDOR_MICREL is not set
2088 +# CONFIG_NET_VENDOR_NATSEMI is not set
2089 +# CONFIG_NET_VENDOR_SEEQ is not set
2090 +# CONFIG_NET_VENDOR_STMICRO is not set
2091 +# CONFIG_NET_VENDOR_WIZNET is not set
2092 +CONFIG_PHYLIB=y
2093 +# CONFIG_WLAN is not set
2094 +# CONFIG_INPUT_MOUSEDEV is not set
2095 +CONFIG_INPUT_EVDEV=y
2096 +# CONFIG_INPUT_KEYBOARD is not set
2097 +# CONFIG_INPUT_MOUSE is not set
2098 +# CONFIG_SERIO is not set
2099 +CONFIG_VT_HW_CONSOLE_BINDING=y
2100 +# CONFIG_LEGACY_PTYS is not set
2101 +# CONFIG_DEVKMEM is not set
2102 +CONFIG_SERIAL_AMBA_PL011=y
2103 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
2104 +CONFIG_TTY_PRINTK=y
2105 +CONFIG_RAW_DRIVER=y
2106 +CONFIG_WATCHDOG=y
2107 +CONFIG_REGULATOR=y
2108 +CONFIG_REGULATOR_DEBUG=y
2109 +CONFIG_REGULATOR_FIXED_VOLTAGE=y
2110 +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
2111 +CONFIG_REGULATOR_USERSPACE_CONSUMER=y
2112 +CONFIG_FB=y
2113 +CONFIG_FRAMEBUFFER_CONSOLE=y
2114 +CONFIG_LOGO=y
2115 +# CONFIG_LOGO_LINUX_MONO is not set
2116 +# CONFIG_LOGO_LINUX_VGA16 is not set
2117 +CONFIG_SOUND=y
2118 +CONFIG_SND=y
2119 +CONFIG_MMC=y
2120 +CONFIG_MMC_SDHCI=y
2121 +CONFIG_MMC_SDHCI_PLTFM=y
2122 +CONFIG_MMC_SDHCI_BCM2708=y
2123 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
2124 +CONFIG_NEW_LEDS=y
2125 +CONFIG_LEDS_CLASS=y
2126 +CONFIG_LEDS_TRIGGERS=y
2127 +# CONFIG_IOMMU_SUPPORT is not set
2128 +CONFIG_EXT4_FS=y
2129 +CONFIG_EXT4_FS_POSIX_ACL=y
2130 +CONFIG_EXT4_FS_SECURITY=y
2131 +CONFIG_AUTOFS4_FS=y
2132 +CONFIG_FSCACHE=y
2133 +CONFIG_CACHEFILES=y
2134 +CONFIG_MSDOS_FS=y
2135 +CONFIG_VFAT_FS=y
2136 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
2137 +CONFIG_TMPFS=y
2138 +CONFIG_TMPFS_POSIX_ACL=y
2139 +CONFIG_CONFIGFS_FS=y
2140 +# CONFIG_MISC_FILESYSTEMS is not set
2141 +CONFIG_NFS_FS=y
2142 +CONFIG_NFS_V3_ACL=y
2143 +CONFIG_NFS_V4=y
2144 +CONFIG_ROOT_NFS=y
2145 +CONFIG_NFS_FSCACHE=y
2146 +CONFIG_NLS_DEFAULT="utf8"
2147 +CONFIG_NLS_CODEPAGE_437=y
2148 +CONFIG_NLS_CODEPAGE_737=y
2149 +CONFIG_NLS_CODEPAGE_775=y
2150 +CONFIG_NLS_CODEPAGE_850=y
2151 +CONFIG_NLS_CODEPAGE_852=y
2152 +CONFIG_NLS_CODEPAGE_855=y
2153 +CONFIG_NLS_CODEPAGE_857=y
2154 +CONFIG_NLS_CODEPAGE_860=y
2155 +CONFIG_NLS_CODEPAGE_861=y
2156 +CONFIG_NLS_CODEPAGE_862=y
2157 +CONFIG_NLS_CODEPAGE_863=y
2158 +CONFIG_NLS_CODEPAGE_864=y
2159 +CONFIG_NLS_CODEPAGE_865=y
2160 +CONFIG_NLS_CODEPAGE_866=y
2161 +CONFIG_NLS_CODEPAGE_869=y
2162 +CONFIG_NLS_CODEPAGE_936=y
2163 +CONFIG_NLS_CODEPAGE_950=y
2164 +CONFIG_NLS_CODEPAGE_932=y
2165 +CONFIG_NLS_CODEPAGE_949=y
2166 +CONFIG_NLS_CODEPAGE_874=y
2167 +CONFIG_NLS_ISO8859_8=y
2168 +CONFIG_NLS_CODEPAGE_1250=y
2169 +CONFIG_NLS_CODEPAGE_1251=y
2170 +CONFIG_NLS_ASCII=y
2171 +CONFIG_NLS_ISO8859_1=y
2172 +CONFIG_NLS_ISO8859_2=y
2173 +CONFIG_NLS_ISO8859_3=y
2174 +CONFIG_NLS_ISO8859_4=y
2175 +CONFIG_NLS_ISO8859_5=y
2176 +CONFIG_NLS_ISO8859_6=y
2177 +CONFIG_NLS_ISO8859_7=y
2178 +CONFIG_NLS_ISO8859_9=y
2179 +CONFIG_NLS_ISO8859_13=y
2180 +CONFIG_NLS_ISO8859_14=y
2181 +CONFIG_NLS_ISO8859_15=y
2182 +CONFIG_NLS_UTF8=y
2183 +CONFIG_PRINTK_TIME=y
2184 +CONFIG_DEBUG_FS=y
2185 +CONFIG_DETECT_HUNG_TASK=y
2186 +# CONFIG_DEBUG_PREEMPT is not set
2187 +# CONFIG_DEBUG_BUGVERBOSE is not set
2188 +# CONFIG_FTRACE is not set
2189 +CONFIG_KGDB=y
2190 +CONFIG_KGDB_KDB=y
2191 +# CONFIG_ARM_UNWIND is not set
2192 +CONFIG_CRYPTO_CBC=y
2193 +CONFIG_CRYPTO_HMAC=y
2194 +CONFIG_CRYPTO_MD5=y
2195 +CONFIG_CRYPTO_SHA1=y
2196 +CONFIG_CRYPTO_DES=y
2197 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
2198 +# CONFIG_CRYPTO_HW is not set
2199 +CONFIG_CRC_ITU_T=y
2200 +CONFIG_LIBCRC32C=y
2201 diff --git a/arch/arm/configs/bcmrpi_small_defconfig b/arch/arm/configs/bcmrpi_small_defconfig
2202 new file mode 100644
2203 index 0000000..3f6e378
2204 --- /dev/null
2205 +++ b/arch/arm/configs/bcmrpi_small_defconfig
2206 @@ -0,0 +1,103 @@
2207 +CONFIG_LOCALVERSION="-quick"
2208 +# CONFIG_LOCALVERSION_AUTO is not set
2209 +# CONFIG_SWAP is not set
2210 +CONFIG_SYSVIPC=y
2211 +CONFIG_NO_HZ=y
2212 +CONFIG_HIGH_RES_TIMERS=y
2213 +CONFIG_IKCONFIG=y
2214 +CONFIG_IKCONFIG_PROC=y
2215 +CONFIG_KALLSYMS_ALL=y
2216 +CONFIG_PERF_EVENTS=y
2217 +# CONFIG_COMPAT_BRK is not set
2218 +# CONFIG_BLK_DEV_BSG is not set
2219 +CONFIG_ARCH_BCM2836=y
2220 +# CONFIG_BCM2708_GPIO is not set
2221 +# CONFIG_BCM2708_VCMEM is not set
2222 +# CONFIG_CACHE_L2X0 is not set
2223 +CONFIG_SMP=y
2224 +CONFIG_HAVE_ARM_ARCH_TIMER=y
2225 +CONFIG_PREEMPT=y
2226 +CONFIG_AEABI=y
2227 +CONFIG_ZBOOT_ROM_TEXT=0x0
2228 +CONFIG_ZBOOT_ROM_BSS=0x0
2229 +CONFIG_CMDLINE="console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext4 rootwait"
2230 +CONFIG_CPU_IDLE=y
2231 +# CONFIG_SUSPEND is not set
2232 +CONFIG_DEVTMPFS=y
2233 +CONFIG_DEVTMPFS_MOUNT=y
2234 +CONFIG_BLK_DEV_LOOP=y
2235 +CONFIG_BLK_DEV_RAM=y
2236 +# CONFIG_BCM2708_VCHIQ is not set
2237 +# CONFIG_INPUT_MOUSEDEV is not set
2238 +CONFIG_INPUT_EVDEV=y
2239 +# CONFIG_INPUT_KEYBOARD is not set
2240 +# CONFIG_INPUT_MOUSE is not set
2241 +# CONFIG_SERIO is not set
2242 +# CONFIG_LEGACY_PTYS is not set
2243 +# CONFIG_DEVKMEM is not set
2244 +CONFIG_SERIAL_AMBA_PL011=y
2245 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
2246 +CONFIG_RAW_DRIVER=y
2247 +# CONFIG_HID is not set
2248 +CONFIG_DMADEVICES=y
2249 +# CONFIG_IOMMU_SUPPORT is not set
2250 +CONFIG_TMPFS=y
2251 +CONFIG_TMPFS_POSIX_ACL=y
2252 +# CONFIG_MISC_FILESYSTEMS is not set
2253 +CONFIG_NLS=y
2254 +CONFIG_NLS_DEFAULT="utf8"
2255 +CONFIG_NLS_CODEPAGE_437=y
2256 +CONFIG_NLS_CODEPAGE_737=y
2257 +CONFIG_NLS_CODEPAGE_775=y
2258 +CONFIG_NLS_CODEPAGE_850=y
2259 +CONFIG_NLS_CODEPAGE_852=y
2260 +CONFIG_NLS_CODEPAGE_855=y
2261 +CONFIG_NLS_CODEPAGE_857=y
2262 +CONFIG_NLS_CODEPAGE_860=y
2263 +CONFIG_NLS_CODEPAGE_861=y
2264 +CONFIG_NLS_CODEPAGE_862=y
2265 +CONFIG_NLS_CODEPAGE_863=y
2266 +CONFIG_NLS_CODEPAGE_864=y
2267 +CONFIG_NLS_CODEPAGE_865=y
2268 +CONFIG_NLS_CODEPAGE_866=y
2269 +CONFIG_NLS_CODEPAGE_869=y
2270 +CONFIG_NLS_CODEPAGE_936=y
2271 +CONFIG_NLS_CODEPAGE_950=y
2272 +CONFIG_NLS_CODEPAGE_932=y
2273 +CONFIG_NLS_CODEPAGE_949=y
2274 +CONFIG_NLS_CODEPAGE_874=y
2275 +CONFIG_NLS_ISO8859_8=y
2276 +CONFIG_NLS_CODEPAGE_1250=y
2277 +CONFIG_NLS_CODEPAGE_1251=y
2278 +CONFIG_NLS_ASCII=y
2279 +CONFIG_NLS_ISO8859_1=y
2280 +CONFIG_NLS_ISO8859_2=y
2281 +CONFIG_NLS_ISO8859_3=y
2282 +CONFIG_NLS_ISO8859_4=y
2283 +CONFIG_NLS_ISO8859_5=y
2284 +CONFIG_NLS_ISO8859_6=y
2285 +CONFIG_NLS_ISO8859_7=y
2286 +CONFIG_NLS_ISO8859_9=y
2287 +CONFIG_NLS_ISO8859_13=y
2288 +CONFIG_NLS_ISO8859_14=y
2289 +CONFIG_NLS_ISO8859_15=y
2290 +CONFIG_NLS_UTF8=y
2291 +CONFIG_PRINTK_TIME=y
2292 +CONFIG_DEBUG_KERNEL=y
2293 +# CONFIG_DEBUG_PREEMPT is not set
2294 +# CONFIG_FTRACE is not set
2295 +CONFIG_KGDB=y
2296 +CONFIG_KGDB_KDB=y
2297 +# CONFIG_ARM_UNWIND is not set
2298 +CONFIG_DEBUG_LL=y
2299 +CONFIG_EARLY_PRINTK=y
2300 +CONFIG_CRYPTO_CBC=y
2301 +CONFIG_CRYPTO_HMAC=y
2302 +CONFIG_CRYPTO_MD5=y
2303 +CONFIG_CRYPTO_SHA1=y
2304 +CONFIG_CRYPTO_DES=y
2305 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
2306 +# CONFIG_CRYPTO_HW is not set
2307 +CONFIG_CRC16=y
2308 +CONFIG_CRC_ITU_T=y
2309 +CONFIG_LIBCRC32C=y
2310 diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
2311 index 664eee8..e1885fa 100644
2312 --- a/arch/arm/kernel/head.S
2313 +++ b/arch/arm/kernel/head.S
2314 @@ -673,6 +673,14 @@ ARM_BE8(rev16 ip, ip)
2315 ldrcc r7, [r4], #4 @ use branch for delay slot
2316 bcc 1b
2317 ret lr
2318 + nop
2319 + nop
2320 + nop
2321 + nop
2322 + nop
2323 + nop
2324 + nop
2325 + nop
2326 #endif
2327 ENDPROC(__fixup_a_pv_table)
2328
2329 diff --git a/arch/arm/mach-bcm2709/Kconfig b/arch/arm/mach-bcm2709/Kconfig
2330 new file mode 100644
2331 index 0000000..4fb6e1b
2332 --- /dev/null
2333 +++ b/arch/arm/mach-bcm2709/Kconfig
2334 @@ -0,0 +1,49 @@
2335 +menu "Broadcom BCM2709 Implementations"
2336 + depends on ARCH_BCM2709
2337 +
2338 +config MACH_BCM2709
2339 + bool "Broadcom BCM2709 Development Platform"
2340 + help
2341 + Include support for the Broadcom(R) BCM2709 platform.
2342 +
2343 +config BCM2709_DT
2344 + bool "BCM2709 Device Tree support"
2345 + depends on MACH_BCM2709
2346 + default n
2347 + select USE_OF
2348 + select ARCH_REQUIRE_GPIOLIB
2349 + select PINCTRL
2350 + select PINCTRL_BCM2835
2351 + help
2352 + Enable Device Tree support for BCM2709
2353 +
2354 +config BCM2708_GPIO
2355 + bool "BCM2709 gpio support"
2356 + depends on MACH_BCM2709
2357 + select ARCH_REQUIRE_GPIOLIB
2358 + default y
2359 + help
2360 + Include support for the Broadcom(R) BCM2709 gpio.
2361 +
2362 +config BCM2708_VCMEM
2363 + bool "Videocore Memory"
2364 + depends on MACH_BCM2709
2365 + default y
2366 + help
2367 + Helper for videocore memory access and total size allocation.
2368 +
2369 +config BCM2708_NOL2CACHE
2370 + bool "Videocore L2 cache disable"
2371 + depends on MACH_BCM2709
2372 + default y
2373 + help
2374 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
2375 +
2376 +config BCM2708_SPIDEV
2377 + bool "Bind spidev to SPI0 master"
2378 + depends on MACH_BCM2709
2379 + depends on SPI
2380 + default y
2381 + help
2382 + Binds spidev driver to the SPI0 master
2383 +endmenu
2384 diff --git a/arch/arm/mach-bcm2709/Makefile b/arch/arm/mach-bcm2709/Makefile
2385 new file mode 100644
2386 index 0000000..2a803bb
2387 --- /dev/null
2388 +++ b/arch/arm/mach-bcm2709/Makefile
2389 @@ -0,0 +1,7 @@
2390 +#
2391 +# Makefile for the linux kernel.
2392 +#
2393 +
2394 +obj-$(CONFIG_MACH_BCM2709) += bcm2709.o armctrl.o vcio.o power.o dma.o
2395 +obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
2396 +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
2397 diff --git a/arch/arm/mach-bcm2709/Makefile.boot b/arch/arm/mach-bcm2709/Makefile.boot
2398 new file mode 100644
2399 index 0000000..67039c3
2400 --- /dev/null
2401 +++ b/arch/arm/mach-bcm2709/Makefile.boot
2402 @@ -0,0 +1,3 @@
2403 + zreladdr-y := 0x00008000
2404 +params_phys-y := 0x00000100
2405 +initrd_phys-y := 0x00800000
2406 diff --git a/arch/arm/mach-bcm2709/armctrl.c b/arch/arm/mach-bcm2709/armctrl.c
2407 new file mode 100644
2408 index 0000000..8e69a813
2409 --- /dev/null
2410 +++ b/arch/arm/mach-bcm2709/armctrl.c
2411 @@ -0,0 +1,357 @@
2412 +/*
2413 + * linux/arch/arm/mach-bcm2708/armctrl.c
2414 + *
2415 + * Copyright (C) 2010 Broadcom
2416 + *
2417 + * This program is free software; you can redistribute it and/or modify
2418 + * it under the terms of the GNU General Public License as published by
2419 + * the Free Software Foundation; either version 2 of the License, or
2420 + * (at your option) any later version.
2421 + *
2422 + * This program is distributed in the hope that it will be useful,
2423 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2424 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2425 + * GNU General Public License for more details.
2426 + *
2427 + * You should have received a copy of the GNU General Public License
2428 + * along with this program; if not, write to the Free Software
2429 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2430 + */
2431 +#include <linux/init.h>
2432 +#include <linux/list.h>
2433 +#include <linux/io.h>
2434 +#include <linux/version.h>
2435 +#include <linux/syscore_ops.h>
2436 +#include <linux/interrupt.h>
2437 +#include <linux/irqdomain.h>
2438 +#include <linux/of.h>
2439 +
2440 +#include <asm/mach/irq.h>
2441 +#include <mach/hardware.h>
2442 +#include "armctrl.h"
2443 +
2444 +/* For support of kernels >= 3.0 assume only one VIC for now*/
2445 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
2446 + INTERRUPT_VC_JPEG,
2447 + INTERRUPT_VC_USB,
2448 + INTERRUPT_VC_3D,
2449 + INTERRUPT_VC_DMA2,
2450 + INTERRUPT_VC_DMA3,
2451 + INTERRUPT_VC_I2C,
2452 + INTERRUPT_VC_SPI,
2453 + INTERRUPT_VC_I2SPCM,
2454 + INTERRUPT_VC_SDIO,
2455 + INTERRUPT_VC_UART,
2456 + INTERRUPT_VC_ARASANSDIO
2457 +};
2458 +
2459 +static void armctrl_mask_irq(struct irq_data *d)
2460 +{
2461 + static const unsigned int disables[4] = {
2462 + ARM_IRQ_DIBL1,
2463 + ARM_IRQ_DIBL2,
2464 + ARM_IRQ_DIBL3,
2465 + 0
2466 + };
2467 + int i;
2468 + if (d->irq >= FIQ_START) {
2469 + writel(0, __io_address(ARM_IRQ_FAST));
2470 + } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
2471 +#if 1
2472 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
2473 + for (i=0; i<4; i++) // i = raw_smp_processor_id(); //
2474 + {
2475 + unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2476 + writel(val &~ (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2477 + }
2478 +#endif
2479 + } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
2480 +#if 0
2481 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
2482 + for (i=0; i<4; i++) {
2483 + unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2484 + writel(val &~ (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2485 + }
2486 +#endif
2487 + } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
2488 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2489 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
2490 + } else { printk("%s: %d\n", __func__, d->irq); BUG(); }
2491 +}
2492 +
2493 +static void armctrl_unmask_irq(struct irq_data *d)
2494 +{
2495 + static const unsigned int enables[4] = {
2496 + ARM_IRQ_ENBL1,
2497 + ARM_IRQ_ENBL2,
2498 + ARM_IRQ_ENBL3,
2499 + 0
2500 + };
2501 + int i;
2502 + if (d->irq >= FIQ_START) {
2503 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
2504 + writel(0x80 | data, __io_address(ARM_IRQ_FAST));
2505 + } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
2506 +#if 1
2507 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_CNTPSIRQ;
2508 + for (i=0; i<4; i++) // i = raw_smp_processor_id();
2509 + {
2510 + unsigned int val = readl(__io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2511 + writel(val | (1 << data), __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 4*i));
2512 + }
2513 +#endif
2514 + } else if (d->irq >= IRQ_ARM_LOCAL_MAILBOX0 && d->irq < IRQ_ARM_LOCAL_MAILBOX0 + 4) {
2515 +#if 0
2516 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - IRQ_ARM_LOCAL_MAILBOX0;
2517 + for (i=0; i<4; i++) {
2518 + unsigned int val = readl(__io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2519 + writel(val | (1 << data), __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 4*i));
2520 + }
2521 +#endif
2522 + } else if (d->irq >= ARM_IRQ1_BASE && d->irq < ARM_IRQ_LOCAL_BASE) {
2523 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
2524 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
2525 + } else { printk("%s: %d\n", __func__, d->irq); BUG(); }
2526 +}
2527 +
2528 +#ifdef CONFIG_OF
2529 +
2530 +#define NR_IRQS_BANK0 21
2531 +#define NR_BANKS 4
2532 +#define IRQS_PER_BANK 32
2533 +
2534 +/* from drivers/irqchip/irq-bcm2835.c */
2535 +static int armctrl_xlate(struct irq_domain *d, struct device_node *ctrlr,
2536 + const u32 *intspec, unsigned int intsize,
2537 + unsigned long *out_hwirq, unsigned int *out_type)
2538 +{
2539 + if (WARN_ON(intsize != 2))
2540 + return -EINVAL;
2541 +
2542 + if (WARN_ON(intspec[0] >= NR_BANKS))
2543 + return -EINVAL;
2544 +
2545 + if (WARN_ON(intspec[1] >= IRQS_PER_BANK))
2546 + return -EINVAL;
2547 +
2548 + if (WARN_ON(intspec[0] == 0 && intspec[1] >= NR_IRQS_BANK0))
2549 + return -EINVAL;
2550 +
2551 + if (WARN_ON(intspec[0] == 3 && intspec[1] > 3 && intspec[1] != 5))
2552 + return -EINVAL;
2553 +
2554 + if (intspec[0] == 0)
2555 + *out_hwirq = ARM_IRQ0_BASE + intspec[1];
2556 + else if (intspec[0] == 1)
2557 + *out_hwirq = ARM_IRQ1_BASE + intspec[1];
2558 + else if (intspec[0] == 2)
2559 + *out_hwirq = ARM_IRQ2_BASE + intspec[1];
2560 + else
2561 + *out_hwirq = ARM_IRQ_LOCAL_BASE + intspec[1];
2562 +
2563 + /* reverse remap_irqs[] */
2564 + switch (*out_hwirq) {
2565 + case INTERRUPT_VC_JPEG:
2566 + *out_hwirq = INTERRUPT_JPEG;
2567 + break;
2568 + case INTERRUPT_VC_USB:
2569 + *out_hwirq = INTERRUPT_USB;
2570 + break;
2571 + case INTERRUPT_VC_3D:
2572 + *out_hwirq = INTERRUPT_3D;
2573 + break;
2574 + case INTERRUPT_VC_DMA2:
2575 + *out_hwirq = INTERRUPT_DMA2;
2576 + break;
2577 + case INTERRUPT_VC_DMA3:
2578 + *out_hwirq = INTERRUPT_DMA3;
2579 + break;
2580 + case INTERRUPT_VC_I2C:
2581 + *out_hwirq = INTERRUPT_I2C;
2582 + break;
2583 + case INTERRUPT_VC_SPI:
2584 + *out_hwirq = INTERRUPT_SPI;
2585 + break;
2586 + case INTERRUPT_VC_I2SPCM:
2587 + *out_hwirq = INTERRUPT_I2SPCM;
2588 + break;
2589 + case INTERRUPT_VC_SDIO:
2590 + *out_hwirq = INTERRUPT_SDIO;
2591 + break;
2592 + case INTERRUPT_VC_UART:
2593 + *out_hwirq = INTERRUPT_UART;
2594 + break;
2595 + case INTERRUPT_VC_ARASANSDIO:
2596 + *out_hwirq = INTERRUPT_ARASANSDIO;
2597 + break;
2598 + }
2599 +
2600 + *out_type = IRQ_TYPE_NONE;
2601 + return 0;
2602 +}
2603 +
2604 +static struct irq_domain_ops armctrl_ops = {
2605 + .xlate = armctrl_xlate
2606 +};
2607 +
2608 +void __init armctrl_dt_init(void)
2609 +{
2610 + struct device_node *np;
2611 + struct irq_domain *domain;
2612 +
2613 + np = of_find_compatible_node(NULL, NULL, "brcm,bcm2708-armctrl-ic");
2614 + if (!np)
2615 + return;
2616 +
2617 + domain = irq_domain_add_legacy(np, BCM2708_ALLOC_IRQS,
2618 + IRQ_ARMCTRL_START, 0,
2619 + &armctrl_ops, NULL);
2620 + WARN_ON(!domain);
2621 +}
2622 +#else
2623 +void __init armctrl_dt_init(void) { }
2624 +#endif /* CONFIG_OF */
2625 +
2626 +#if defined(CONFIG_PM)
2627 +
2628 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
2629 +
2630 +/* Static defines
2631 + * struct armctrl_device - VIC PM device (< 3.xx)
2632 + * @sysdev: The system device which is registered. (< 3.xx)
2633 + * @irq: The IRQ number for the base of the VIC.
2634 + * @base: The register base for the VIC.
2635 + * @resume_sources: A bitmask of interrupts for resume.
2636 + * @resume_irqs: The IRQs enabled for resume.
2637 + * @int_select: Save for VIC_INT_SELECT.
2638 + * @int_enable: Save for VIC_INT_ENABLE.
2639 + * @soft_int: Save for VIC_INT_SOFT.
2640 + * @protect: Save for VIC_PROTECT.
2641 + */
2642 +struct armctrl_info {
2643 + void __iomem *base;
2644 + int irq;
2645 + u32 resume_sources;
2646 + u32 resume_irqs;
2647 + u32 int_select;
2648 + u32 int_enable;
2649 + u32 soft_int;
2650 + u32 protect;
2651 +} armctrl;
2652 +
2653 +static int armctrl_suspend(void)
2654 +{
2655 + return 0;
2656 +}
2657 +
2658 +static void armctrl_resume(void)
2659 +{
2660 + return;
2661 +}
2662 +
2663 +/**
2664 + * armctrl_pm_register - Register a VIC for later power management control
2665 + * @base: The base address of the VIC.
2666 + * @irq: The base IRQ for the VIC.
2667 + * @resume_sources: bitmask of interrupts allowed for resume sources.
2668 + *
2669 + * For older kernels (< 3.xx) do -
2670 + * Register the VIC with the system device tree so that it can be notified
2671 + * of suspend and resume requests and ensure that the correct actions are
2672 + * taken to re-instate the settings on resume.
2673 + */
2674 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
2675 + u32 resume_sources)
2676 +{
2677 + armctrl.base = base;
2678 + armctrl.resume_sources = resume_sources;
2679 + armctrl.irq = irq;
2680 +}
2681 +
2682 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
2683 +{
2684 + unsigned int off = d->irq & 31;
2685 + u32 bit = 1 << off;
2686 +
2687 + if (!(bit & armctrl.resume_sources))
2688 + return -EINVAL;
2689 +
2690 + if (on)
2691 + armctrl.resume_irqs |= bit;
2692 + else
2693 + armctrl.resume_irqs &= ~bit;
2694 +
2695 + return 0;
2696 +}
2697 +
2698 +#else
2699 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
2700 + u32 arg1)
2701 +{
2702 +}
2703 +
2704 +#define armctrl_suspend NULL
2705 +#define armctrl_resume NULL
2706 +#define armctrl_set_wake NULL
2707 +#endif /* CONFIG_PM */
2708 +
2709 +static struct syscore_ops armctrl_syscore_ops = {
2710 + .suspend = armctrl_suspend,
2711 + .resume = armctrl_resume,
2712 +};
2713 +
2714 +/**
2715 + * armctrl_syscore_init - initicall to register VIC pm functions
2716 + *
2717 + * This is called via late_initcall() to register
2718 + * the resources for the VICs due to the early
2719 + * nature of the VIC's registration.
2720 +*/
2721 +static int __init armctrl_syscore_init(void)
2722 +{
2723 + register_syscore_ops(&armctrl_syscore_ops);
2724 + return 0;
2725 +}
2726 +
2727 +late_initcall(armctrl_syscore_init);
2728 +
2729 +static struct irq_chip armctrl_chip = {
2730 + .name = "ARMCTRL",
2731 + .irq_ack = NULL,
2732 + .irq_mask = armctrl_mask_irq,
2733 + .irq_unmask = armctrl_unmask_irq,
2734 + .irq_set_wake = armctrl_set_wake,
2735 +};
2736 +
2737 +/**
2738 + * armctrl_init - initialise a vectored interrupt controller
2739 + * @base: iomem base address
2740 + * @irq_start: starting interrupt number, must be muliple of 32
2741 + * @armctrl_sources: bitmask of interrupt sources to allow
2742 + * @resume_sources: bitmask of interrupt sources to allow for resume
2743 + */
2744 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
2745 + u32 armctrl_sources, u32 resume_sources)
2746 +{
2747 + unsigned int irq;
2748 +
2749 + for (irq = 0; irq < BCM2708_ALLOC_IRQS; irq++) {
2750 + unsigned int data = irq;
2751 + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
2752 + data = remap_irqs[irq - INTERRUPT_JPEG];
2753 + if (irq >= IRQ_ARM_LOCAL_CNTPSIRQ && irq <= IRQ_ARM_LOCAL_TIMER) {
2754 + irq_set_percpu_devid(irq);
2755 + irq_set_chip_and_handler(irq, &armctrl_chip, handle_percpu_devid_irq);
2756 + set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
2757 + } else {
2758 + irq_set_chip_and_handler(irq, &armctrl_chip, handle_level_irq);
2759 + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
2760 + }
2761 + irq_set_chip_data(irq, (void *)data);
2762 + }
2763 +
2764 + armctrl_pm_register(base, irq_start, resume_sources);
2765 + init_FIQ(FIQ_START);
2766 + armctrl_dt_init();
2767 + return 0;
2768 +}
2769 diff --git a/arch/arm/mach-bcm2709/armctrl.h b/arch/arm/mach-bcm2709/armctrl.h
2770 new file mode 100644
2771 index 0000000..0aa916e
2772 --- /dev/null
2773 +++ b/arch/arm/mach-bcm2709/armctrl.h
2774 @@ -0,0 +1,27 @@
2775 +/*
2776 + * linux/arch/arm/mach-bcm2708/armctrl.h
2777 + *
2778 + * Copyright (C) 2010 Broadcom
2779 + *
2780 + * This program is free software; you can redistribute it and/or modify
2781 + * it under the terms of the GNU General Public License as published by
2782 + * the Free Software Foundation; either version 2 of the License, or
2783 + * (at your option) any later version.
2784 + *
2785 + * This program is distributed in the hope that it will be useful,
2786 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2787 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2788 + * GNU General Public License for more details.
2789 + *
2790 + * You should have received a copy of the GNU General Public License
2791 + * along with this program; if not, write to the Free Software
2792 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2793 + */
2794 +
2795 +#ifndef __BCM2708_ARMCTRL_H
2796 +#define __BCM2708_ARMCTRL_H
2797 +
2798 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
2799 + u32 armctrl_sources, u32 resume_sources);
2800 +
2801 +#endif
2802 diff --git a/arch/arm/mach-bcm2709/bcm2708_gpio.c b/arch/arm/mach-bcm2709/bcm2708_gpio.c
2803 new file mode 100644
2804 index 0000000..c1e9254
2805 --- /dev/null
2806 +++ b/arch/arm/mach-bcm2709/bcm2708_gpio.c
2807 @@ -0,0 +1,426 @@
2808 +/*
2809 + * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
2810 + *
2811 + * Copyright (C) 2010 Broadcom
2812 + *
2813 + * This program is free software; you can redistribute it and/or modify
2814 + * it under the terms of the GNU General Public License version 2 as
2815 + * published by the Free Software Foundation.
2816 + *
2817 + */
2818 +
2819 +#include <linux/spinlock.h>
2820 +#include <linux/module.h>
2821 +#include <linux/delay.h>
2822 +#include <linux/list.h>
2823 +#include <linux/io.h>
2824 +#include <linux/irq.h>
2825 +#include <linux/interrupt.h>
2826 +#include <linux/slab.h>
2827 +#include <mach/gpio.h>
2828 +#include <linux/gpio.h>
2829 +#include <linux/platform_device.h>
2830 +#include <mach/platform.h>
2831 +#include <linux/pinctrl/consumer.h>
2832 +
2833 +#include <linux/platform_data/bcm2708.h>
2834 +
2835 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2836 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
2837 +#define BCM_GPIO_USE_IRQ 1
2838 +
2839 +#define GPIOFSEL(x) (0x00+(x)*4)
2840 +#define GPIOSET(x) (0x1c+(x)*4)
2841 +#define GPIOCLR(x) (0x28+(x)*4)
2842 +#define GPIOLEV(x) (0x34+(x)*4)
2843 +#define GPIOEDS(x) (0x40+(x)*4)
2844 +#define GPIOREN(x) (0x4c+(x)*4)
2845 +#define GPIOFEN(x) (0x58+(x)*4)
2846 +#define GPIOHEN(x) (0x64+(x)*4)
2847 +#define GPIOLEN(x) (0x70+(x)*4)
2848 +#define GPIOAREN(x) (0x7c+(x)*4)
2849 +#define GPIOAFEN(x) (0x88+(x)*4)
2850 +#define GPIOUD(x) (0x94+(x)*4)
2851 +#define GPIOUDCLK(x) (0x98+(x)*4)
2852 +
2853 +#define GPIO_BANKS 2
2854 +
2855 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
2856 + GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
2857 + GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
2858 + GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
2859 +};
2860 +
2861 + /* Each of the two spinlocks protects a different set of hardware
2862 + * regiters and data structurs. This decouples the code of the IRQ from
2863 + * the GPIO code. This also makes the case of a GPIO routine call from
2864 + * the IRQ code simpler.
2865 + */
2866 +static DEFINE_SPINLOCK(lock); /* GPIO registers */
2867 +
2868 +struct bcm2708_gpio {
2869 + struct list_head list;
2870 + void __iomem *base;
2871 + struct gpio_chip gc;
2872 + unsigned long rising[(BCM2708_NR_GPIOS + 31) / 32];
2873 + unsigned long falling[(BCM2708_NR_GPIOS + 31) / 32];
2874 + unsigned long high[(BCM2708_NR_GPIOS + 31) / 32];
2875 + unsigned long low[(BCM2708_NR_GPIOS + 31) / 32];
2876 +};
2877 +
2878 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
2879 + int function)
2880 +{
2881 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2882 + unsigned long flags;
2883 + unsigned gpiodir;
2884 + unsigned gpio_bank = offset / 10;
2885 + unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
2886 +
2887 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
2888 + if (offset >= BCM2708_NR_GPIOS)
2889 + return -EINVAL;
2890 +
2891 + spin_lock_irqsave(&lock, flags);
2892 +
2893 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2894 + gpiodir &= ~(7 << gpio_field_offset);
2895 + gpiodir |= function << gpio_field_offset;
2896 + writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
2897 + spin_unlock_irqrestore(&lock, flags);
2898 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2899 +
2900 + return 0;
2901 +}
2902 +
2903 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
2904 +{
2905 + return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
2906 +}
2907 +
2908 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2909 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
2910 + int value)
2911 +{
2912 + int ret;
2913 + ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
2914 + if (ret >= 0)
2915 + bcm2708_gpio_set(gc, offset, value);
2916 + return ret;
2917 +}
2918 +
2919 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
2920 +{
2921 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2922 + unsigned gpio_bank = offset / 32;
2923 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2924 + unsigned lev;
2925 +
2926 + if (offset >= BCM2708_NR_GPIOS)
2927 + return 0;
2928 + lev = readl(gpio->base + GPIOLEV(gpio_bank));
2929 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
2930 + return 0x1 & (lev >> gpio_field_offset);
2931 +}
2932 +
2933 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2934 +{
2935 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2936 + unsigned gpio_bank = offset / 32;
2937 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2938 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
2939 + if (offset >= BCM2708_NR_GPIOS)
2940 + return;
2941 + if (value)
2942 + writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
2943 + else
2944 + writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
2945 +}
2946 +
2947 +/**********************
2948 + * extension to configure pullups
2949 + */
2950 +int bcm2708_gpio_setpull(struct gpio_chip *gc, unsigned offset,
2951 + bcm2708_gpio_pull_t value)
2952 +{
2953 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2954 + unsigned gpio_bank = offset / 32;
2955 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2956 +
2957 + if (offset >= BCM2708_NR_GPIOS)
2958 + return -EINVAL;
2959 +
2960 + switch (value) {
2961 + case BCM2708_PULL_UP:
2962 + writel(2, gpio->base + GPIOUD(0));
2963 + break;
2964 + case BCM2708_PULL_DOWN:
2965 + writel(1, gpio->base + GPIOUD(0));
2966 + break;
2967 + case BCM2708_PULL_OFF:
2968 + writel(0, gpio->base + GPIOUD(0));
2969 + break;
2970 + }
2971 +
2972 + udelay(5);
2973 + writel(1 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
2974 + udelay(5);
2975 + writel(0, gpio->base + GPIOUD(0));
2976 + writel(0 << gpio_field_offset, gpio->base + GPIOUDCLK(gpio_bank));
2977 +
2978 + return 0;
2979 +}
2980 +EXPORT_SYMBOL(bcm2708_gpio_setpull);
2981 +
2982 +/*************************************************************************************************************************
2983 + * bcm2708 GPIO IRQ
2984 + */
2985 +
2986 +#if BCM_GPIO_USE_IRQ
2987 +
2988 +static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
2989 +{
2990 + return gpio_to_irq(gpio);
2991 +}
2992 +
2993 +static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
2994 +{
2995 + unsigned irq = d->irq;
2996 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2997 + unsigned gn = irq_to_gpio(irq);
2998 + unsigned gb = gn / 32;
2999 + unsigned go = gn % 32;
3000 +
3001 + gpio->rising[gb] &= ~(1 << go);
3002 + gpio->falling[gb] &= ~(1 << go);
3003 + gpio->high[gb] &= ~(1 << go);
3004 + gpio->low[gb] &= ~(1 << go);
3005 +
3006 + if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
3007 + return -EINVAL;
3008 +
3009 + if (type & IRQ_TYPE_EDGE_RISING)
3010 + gpio->rising[gb] |= (1 << go);
3011 + if (type & IRQ_TYPE_EDGE_FALLING)
3012 + gpio->falling[gb] |= (1 << go);
3013 + if (type & IRQ_TYPE_LEVEL_HIGH)
3014 + gpio->high[gb] |= (1 << go);
3015 + if (type & IRQ_TYPE_LEVEL_LOW)
3016 + gpio->low[gb] |= (1 << go);
3017 + return 0;
3018 +}
3019 +
3020 +static void bcm2708_gpio_irq_mask(struct irq_data *d)
3021 +{
3022 + unsigned irq = d->irq;
3023 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3024 + unsigned gn = irq_to_gpio(irq);
3025 + unsigned gb = gn / 32;
3026 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
3027 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
3028 + unsigned long high = readl(gpio->base + GPIOHEN(gb));
3029 + unsigned long low = readl(gpio->base + GPIOLEN(gb));
3030 +
3031 + gn = gn % 32;
3032 +
3033 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
3034 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
3035 + writel(high & ~(1 << gn), gpio->base + GPIOHEN(gb));
3036 + writel(low & ~(1 << gn), gpio->base + GPIOLEN(gb));
3037 +}
3038 +
3039 +static void bcm2708_gpio_irq_unmask(struct irq_data *d)
3040 +{
3041 + unsigned irq = d->irq;
3042 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
3043 + unsigned gn = irq_to_gpio(irq);
3044 + unsigned gb = gn / 32;
3045 + unsigned go = gn % 32;
3046 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
3047 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
3048 + unsigned long high = readl(gpio->base + GPIOHEN(gb));
3049 + unsigned long low = readl(gpio->base + GPIOLEN(gb));
3050 +
3051 + if (gpio->rising[gb] & (1 << go)) {
3052 + writel(rising | (1 << go), gpio->base + GPIOREN(gb));
3053 + } else {
3054 + writel(rising & ~(1 << go), gpio->base + GPIOREN(gb));
3055 + }
3056 +
3057 + if (gpio->falling[gb] & (1 << go)) {
3058 + writel(falling | (1 << go), gpio->base + GPIOFEN(gb));
3059 + } else {
3060 + writel(falling & ~(1 << go), gpio->base + GPIOFEN(gb));
3061 + }
3062 +
3063 + if (gpio->high[gb] & (1 << go)) {
3064 + writel(high | (1 << go), gpio->base + GPIOHEN(gb));
3065 + } else {
3066 + writel(high & ~(1 << go), gpio->base + GPIOHEN(gb));
3067 + }
3068 +
3069 + if (gpio->low[gb] & (1 << go)) {
3070 + writel(low | (1 << go), gpio->base + GPIOLEN(gb));
3071 + } else {
3072 + writel(low & ~(1 << go), gpio->base + GPIOLEN(gb));
3073 + }
3074 +}
3075 +
3076 +static struct irq_chip bcm2708_irqchip = {
3077 + .name = "GPIO",
3078 + .irq_enable = bcm2708_gpio_irq_unmask,
3079 + .irq_disable = bcm2708_gpio_irq_mask,
3080 + .irq_unmask = bcm2708_gpio_irq_unmask,
3081 + .irq_mask = bcm2708_gpio_irq_mask,
3082 + .irq_set_type = bcm2708_gpio_irq_set_type,
3083 +};
3084 +
3085 +static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
3086 +{
3087 + unsigned long edsr;
3088 + unsigned bank;
3089 + int i;
3090 + unsigned gpio;
3091 + unsigned level_bits;
3092 + struct bcm2708_gpio *gpio_data = dev_id;
3093 +
3094 + for (bank = 0; bank < GPIO_BANKS; bank++) {
3095 + edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
3096 + level_bits = gpio_data->high[bank] | gpio_data->low[bank];
3097 +
3098 + for_each_set_bit(i, &edsr, 32) {
3099 + gpio = i + bank * 32;
3100 + /* ack edge triggered IRQs immediately */
3101 + if (!(level_bits & (1<<i)))
3102 + writel(1<<i,
3103 + __io_address(GPIO_BASE) + GPIOEDS(bank));
3104 + generic_handle_irq(gpio_to_irq(gpio));
3105 + /* ack level triggered IRQ after handling them */
3106 + if (level_bits & (1<<i))
3107 + writel(1<<i,
3108 + __io_address(GPIO_BASE) + GPIOEDS(bank));
3109 + }
3110 + }
3111 + return IRQ_HANDLED;
3112 +}
3113 +
3114 +static struct irqaction bcm2708_gpio_irq = {
3115 + .name = "BCM2708 GPIO catchall handler",
3116 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
3117 + .handler = bcm2708_gpio_interrupt,
3118 +};
3119 +
3120 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3121 +{
3122 + unsigned irq;
3123 +
3124 + ucb->gc.to_irq = bcm2708_gpio_to_irq;
3125 +
3126 + for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
3127 + irq_set_chip_data(irq, ucb);
3128 + irq_set_chip_and_handler(irq, &bcm2708_irqchip,
3129 + handle_simple_irq);
3130 + set_irq_flags(irq, IRQF_VALID);
3131 + }
3132 +
3133 + bcm2708_gpio_irq.dev_id = ucb;
3134 + setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
3135 +}
3136 +
3137 +#else
3138 +
3139 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3140 +{
3141 +}
3142 +
3143 +#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
3144 +
3145 +static int bcm2708_gpio_probe(struct platform_device *dev)
3146 +{
3147 + struct bcm2708_gpio *ucb;
3148 + struct resource *res;
3149 + int bank;
3150 + int err = 0;
3151 +
3152 + printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
3153 +
3154 + ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
3155 + if (NULL == ucb) {
3156 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3157 + "mailbox memory\n");
3158 + err = -ENOMEM;
3159 + goto err;
3160 + }
3161 +
3162 + res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3163 +
3164 + platform_set_drvdata(dev, ucb);
3165 + ucb->base = __io_address(GPIO_BASE);
3166 +
3167 + ucb->gc.label = "bcm2708_gpio";
3168 + ucb->gc.base = 0;
3169 + ucb->gc.ngpio = BCM2708_NR_GPIOS;
3170 + ucb->gc.owner = THIS_MODULE;
3171 +
3172 + ucb->gc.direction_input = bcm2708_gpio_dir_in;
3173 + ucb->gc.direction_output = bcm2708_gpio_dir_out;
3174 + ucb->gc.get = bcm2708_gpio_get;
3175 + ucb->gc.set = bcm2708_gpio_set;
3176 + ucb->gc.can_sleep = 0;
3177 +
3178 + for (bank = 0; bank < GPIO_BANKS; bank++) {
3179 + writel(0, ucb->base + GPIOREN(bank));
3180 + writel(0, ucb->base + GPIOFEN(bank));
3181 + writel(0, ucb->base + GPIOHEN(bank));
3182 + writel(0, ucb->base + GPIOLEN(bank));
3183 + writel(0, ucb->base + GPIOAREN(bank));
3184 + writel(0, ucb->base + GPIOAFEN(bank));
3185 + writel(~0, ucb->base + GPIOEDS(bank));
3186 + }
3187 +
3188 + bcm2708_gpio_irq_init(ucb);
3189 +
3190 + err = gpiochip_add(&ucb->gc);
3191 +
3192 +err:
3193 + return err;
3194 +
3195 +}
3196 +
3197 +static int bcm2708_gpio_remove(struct platform_device *dev)
3198 +{
3199 + int err = 0;
3200 + struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
3201 +
3202 + printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
3203 +
3204 + gpiochip_remove(&ucb->gc);
3205 +
3206 + platform_set_drvdata(dev, NULL);
3207 + kfree(ucb);
3208 +
3209 + return err;
3210 +}
3211 +
3212 +static struct platform_driver bcm2708_gpio_driver = {
3213 + .probe = bcm2708_gpio_probe,
3214 + .remove = bcm2708_gpio_remove,
3215 + .driver = {
3216 + .name = "bcm2708_gpio"},
3217 +};
3218 +
3219 +static int __init bcm2708_gpio_init(void)
3220 +{
3221 + return platform_driver_register(&bcm2708_gpio_driver);
3222 +}
3223 +
3224 +static void __exit bcm2708_gpio_exit(void)
3225 +{
3226 + platform_driver_unregister(&bcm2708_gpio_driver);
3227 +}
3228 +
3229 +module_init(bcm2708_gpio_init);
3230 +module_exit(bcm2708_gpio_exit);
3231 +
3232 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
3233 +MODULE_LICENSE("GPL");
3234 diff --git a/arch/arm/mach-bcm2709/bcm2709.c b/arch/arm/mach-bcm2709/bcm2709.c
3235 new file mode 100644
3236 index 0000000..a1058ad
3237 --- /dev/null
3238 +++ b/arch/arm/mach-bcm2709/bcm2709.c
3239 @@ -0,0 +1,1237 @@
3240 +/*
3241 + * linux/arch/arm/mach-bcm2709/bcm2709.c
3242 + *
3243 + * Copyright (C) 2010 Broadcom
3244 + *
3245 + * This program is free software; you can redistribute it and/or modify
3246 + * it under the terms of the GNU General Public License as published by
3247 + * the Free Software Foundation; either version 2 of the License, or
3248 + * (at your option) any later version.
3249 + *
3250 + * This program is distributed in the hope that it will be useful,
3251 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3252 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3253 + * GNU General Public License for more details.
3254 + *
3255 + * You should have received a copy of the GNU General Public License
3256 + * along with this program; if not, write to the Free Software
3257 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3258 + */
3259 +
3260 +#include <linux/init.h>
3261 +#include <linux/device.h>
3262 +#include <linux/dma-mapping.h>
3263 +#include <linux/serial_8250.h>
3264 +#include <linux/platform_device.h>
3265 +#include <linux/syscore_ops.h>
3266 +#include <linux/interrupt.h>
3267 +#include <linux/amba/bus.h>
3268 +#include <linux/amba/clcd.h>
3269 +#include <linux/clk-provider.h>
3270 +#include <linux/clkdev.h>
3271 +#include <linux/clockchips.h>
3272 +#include <linux/cnt32_to_63.h>
3273 +#include <linux/io.h>
3274 +#include <linux/module.h>
3275 +#include <linux/of_platform.h>
3276 +#include <linux/spi/spi.h>
3277 +#include <linux/gpio/machine.h>
3278 +#include <linux/w1-gpio.h>
3279 +
3280 +#include <linux/version.h>
3281 +#include <linux/clkdev.h>
3282 +#include <asm/system_info.h>
3283 +#include <mach/hardware.h>
3284 +#include <asm/irq.h>
3285 +#include <linux/leds.h>
3286 +#include <asm/mach-types.h>
3287 +#include <asm/cputype.h>
3288 +#include <linux/sched_clock.h>
3289 +
3290 +#include <asm/mach/arch.h>
3291 +#include <asm/mach/flash.h>
3292 +#include <asm/mach/irq.h>
3293 +#include <asm/mach/time.h>
3294 +#include <asm/mach/map.h>
3295 +
3296 +#include <mach/timex.h>
3297 +#include <mach/dma.h>
3298 +#include <mach/vcio.h>
3299 +#include <mach/system.h>
3300 +
3301 +#include <linux/delay.h>
3302 +
3303 +#include "bcm2709.h"
3304 +#include "armctrl.h"
3305 +
3306 +#ifdef CONFIG_BCM_VC_CMA
3307 +#include <linux/broadcom/vc_cma.h>
3308 +#endif
3309 +
3310 +//#define SYSTEM_TIMER
3311 +
3312 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
3313 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
3314 + * represent this window by setting our dmamasks to 26 bits but, in fact
3315 + * we're not going to use addresses outside this range (they're not in real
3316 + * memory) so we don't bother.
3317 + *
3318 + * In the future we might include code to use this IOMMU to remap other
3319 + * physical addresses onto VideoCore memory then the use of 32-bits would be
3320 + * more legitimate.
3321 + */
3322 +#define DMA_MASK_BITS_COMMON 32
3323 +
3324 +// use GPIO 4 for the one-wire GPIO pin, if enabled
3325 +#define W1_GPIO 4
3326 +// ensure one-wire GPIO pullup is disabled by default
3327 +#define W1_PULLUP -1
3328 +
3329 +/* command line parameters */
3330 +static unsigned boardrev, serial;
3331 +static unsigned uart_clock = UART0_CLOCK;
3332 +static unsigned disk_led_gpio = 16;
3333 +static unsigned disk_led_active_low = 1;
3334 +static unsigned reboot_part = 0;
3335 +static unsigned w1_gpio_pin = W1_GPIO;
3336 +static unsigned w1_gpio_pullup = W1_PULLUP;
3337 +
3338 +static unsigned use_dt = 0;
3339 +
3340 +static void __init bcm2709_init_led(void);
3341 +
3342 +void __init bcm2709_init_irq(void)
3343 +{
3344 + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
3345 +}
3346 +
3347 +static struct map_desc bcm2709_io_desc[] __initdata = {
3348 + {
3349 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
3350 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
3351 + .length = SZ_4K,
3352 + .type = MT_DEVICE},
3353 + {
3354 + .virtual = IO_ADDRESS(UART0_BASE),
3355 + .pfn = __phys_to_pfn(UART0_BASE),
3356 + .length = SZ_4K,
3357 + .type = MT_DEVICE},
3358 + {
3359 + .virtual = IO_ADDRESS(UART1_BASE),
3360 + .pfn = __phys_to_pfn(UART1_BASE),
3361 + .length = SZ_4K,
3362 + .type = MT_DEVICE},
3363 + {
3364 + .virtual = IO_ADDRESS(DMA_BASE),
3365 + .pfn = __phys_to_pfn(DMA_BASE),
3366 + .length = SZ_4K,
3367 + .type = MT_DEVICE},
3368 + {
3369 + .virtual = IO_ADDRESS(MCORE_BASE),
3370 + .pfn = __phys_to_pfn(MCORE_BASE),
3371 + .length = SZ_4K,
3372 + .type = MT_DEVICE},
3373 + {
3374 + .virtual = IO_ADDRESS(ST_BASE),
3375 + .pfn = __phys_to_pfn(ST_BASE),
3376 + .length = SZ_4K,
3377 + .type = MT_DEVICE},
3378 + {
3379 + .virtual = IO_ADDRESS(USB_BASE),
3380 + .pfn = __phys_to_pfn(USB_BASE),
3381 + .length = SZ_128K,
3382 + .type = MT_DEVICE},
3383 + {
3384 + .virtual = IO_ADDRESS(PM_BASE),
3385 + .pfn = __phys_to_pfn(PM_BASE),
3386 + .length = SZ_4K,
3387 + .type = MT_DEVICE},
3388 + {
3389 + .virtual = IO_ADDRESS(GPIO_BASE),
3390 + .pfn = __phys_to_pfn(GPIO_BASE),
3391 + .length = SZ_4K,
3392 + .type = MT_DEVICE},
3393 + {
3394 + .virtual = IO_ADDRESS(ARM_LOCAL_BASE),
3395 + .pfn = __phys_to_pfn(ARM_LOCAL_BASE),
3396 + .length = SZ_4K,
3397 + .type = MT_DEVICE},
3398 +};
3399 +
3400 +void __init bcm2709_map_io(void)
3401 +{
3402 + iotable_init(bcm2709_io_desc, ARRAY_SIZE(bcm2709_io_desc));
3403 +}
3404 +
3405 +#ifdef SYSTEM_TIMER
3406 +
3407 +/* The STC is a free running counter that increments at the rate of 1MHz */
3408 +#define STC_FREQ_HZ 1000000
3409 +
3410 +static inline uint32_t timer_read(void)
3411 +{
3412 + /* STC: a free running counter that increments at the rate of 1MHz */
3413 + return readl(__io_address(ST_BASE + 0x04));
3414 +}
3415 +
3416 +static unsigned long bcm2709_read_current_timer(void)
3417 +{
3418 + return timer_read();
3419 +}
3420 +
3421 +static u64 notrace bcm2709_read_sched_clock(void)
3422 +{
3423 + return timer_read();
3424 +}
3425 +
3426 +static cycle_t clksrc_read(struct clocksource *cs)
3427 +{
3428 + return timer_read();
3429 +}
3430 +
3431 +static struct clocksource clocksource_stc = {
3432 + .name = "stc",
3433 + .rating = 300,
3434 + .read = clksrc_read,
3435 + .mask = CLOCKSOURCE_MASK(32),
3436 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
3437 +};
3438 +
3439 +unsigned long frc_clock_ticks32(void)
3440 +{
3441 + return timer_read();
3442 +}
3443 +
3444 +static void __init bcm2709_clocksource_init(void)
3445 +{
3446 + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
3447 + printk(KERN_ERR "timer: failed to initialize clock "
3448 + "source %s\n", clocksource_stc.name);
3449 + }
3450 +}
3451 +#endif
3452 +
3453 +struct clk __init *bcm2709_clk_register(const char *name, unsigned long fixed_rate)
3454 +{
3455 + struct clk *clk;
3456 +
3457 + clk = clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT,
3458 + fixed_rate);
3459 + if (IS_ERR(clk))
3460 + pr_err("%s not registered\n", name);
3461 +
3462 + return clk;
3463 +}
3464 +
3465 +void __init bcm2709_register_clkdev(struct clk *clk, const char *name)
3466 +{
3467 + int ret;
3468 +
3469 + ret = clk_register_clkdev(clk, NULL, name);
3470 + if (ret)
3471 + pr_err("%s alias not registered\n", name);
3472 +}
3473 +
3474 +void __init bcm2709_init_clocks(void)
3475 +{
3476 + struct clk *clk;
3477 +
3478 + clk = bcm2709_clk_register("uart0_clk", uart_clock);
3479 + bcm2709_register_clkdev(clk, "dev:f1");
3480 +
3481 + clk = bcm2709_clk_register("sdhost_clk", 250000000);
3482 + bcm2709_register_clkdev(clk, "bcm2708_spi.0");
3483 + bcm2709_register_clkdev(clk, "bcm2708_i2c.0");
3484 + bcm2709_register_clkdev(clk, "bcm2708_i2c.1");
3485 +}
3486 +
3487 +#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
3488 +#define UART0_DMA { 15, 14 }
3489 +
3490 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
3491 +
3492 +static struct amba_device *amba_devs[] __initdata = {
3493 + &uart0_device,
3494 +};
3495 +
3496 +static struct resource bcm2708_dmaman_resources[] = {
3497 + {
3498 + .start = DMA_BASE,
3499 + .end = DMA_BASE + SZ_4K - 1,
3500 + .flags = IORESOURCE_MEM,
3501 + }
3502 +};
3503 +
3504 +static struct platform_device bcm2708_dmaman_device = {
3505 + .name = BCM_DMAMAN_DRIVER_NAME,
3506 + .id = 0, /* first bcm2708_dma */
3507 + .resource = bcm2708_dmaman_resources,
3508 + .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
3509 +};
3510 +
3511 +#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
3512 +static struct w1_gpio_platform_data w1_gpio_pdata = {
3513 + .pin = W1_GPIO,
3514 + .ext_pullup_enable_pin = W1_PULLUP,
3515 + .is_open_drain = 0,
3516 +};
3517 +
3518 +static struct platform_device w1_device = {
3519 + .name = "w1-gpio",
3520 + .id = -1,
3521 + .dev.platform_data = &w1_gpio_pdata,
3522 +};
3523 +#endif
3524 +
3525 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3526 +
3527 +static struct platform_device bcm2708_fb_device = {
3528 + .name = "bcm2708_fb",
3529 + .id = -1, /* only one bcm2708_fb */
3530 + .resource = NULL,
3531 + .num_resources = 0,
3532 + .dev = {
3533 + .dma_mask = &fb_dmamask,
3534 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3535 + },
3536 +};
3537 +
3538 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
3539 + {
3540 + .mapbase = UART1_BASE + 0x40,
3541 + .irq = IRQ_AUX,
3542 + .uartclk = 125000000,
3543 + .regshift = 2,
3544 + .iotype = UPIO_MEM,
3545 + .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
3546 + .type = PORT_8250,
3547 + },
3548 + {},
3549 +};
3550 +
3551 +static struct platform_device bcm2708_uart1_device = {
3552 + .name = "serial8250",
3553 + .id = PLAT8250_DEV_PLATFORM,
3554 + .dev = {
3555 + .platform_data = bcm2708_uart1_platform_data,
3556 + },
3557 +};
3558 +
3559 +static struct resource bcm2708_usb_resources[] = {
3560 + [0] = {
3561 + .start = USB_BASE,
3562 + .end = USB_BASE + SZ_128K - 1,
3563 + .flags = IORESOURCE_MEM,
3564 + },
3565 + [1] = {
3566 + .start = MPHI_BASE,
3567 + .end = MPHI_BASE + SZ_4K - 1,
3568 + .flags = IORESOURCE_MEM,
3569 + },
3570 + [2] = {
3571 + .start = IRQ_HOSTPORT,
3572 + .end = IRQ_HOSTPORT,
3573 + .flags = IORESOURCE_IRQ,
3574 + },
3575 + [3] = {
3576 + .start = IRQ_USB,
3577 + .end = IRQ_USB,
3578 + .flags = IORESOURCE_IRQ,
3579 + },
3580 +};
3581 +
3582 +
3583 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3584 +
3585 +static struct platform_device bcm2708_usb_device = {
3586 + .name = "bcm2708_usb",
3587 + .id = -1, /* only one bcm2708_usb */
3588 + .resource = bcm2708_usb_resources,
3589 + .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
3590 + .dev = {
3591 + .dma_mask = &usb_dmamask,
3592 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3593 + },
3594 +};
3595 +
3596 +static struct resource bcm2708_vcio_resources[] = {
3597 + [0] = { /* mailbox/semaphore/doorbell access */
3598 + .start = MCORE_BASE,
3599 + .end = MCORE_BASE + SZ_4K - 1,
3600 + .flags = IORESOURCE_MEM,
3601 + },
3602 +};
3603 +
3604 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3605 +
3606 +static struct platform_device bcm2708_vcio_device = {
3607 + .name = BCM_VCIO_DRIVER_NAME,
3608 + .id = -1, /* only one VideoCore I/O area */
3609 + .resource = bcm2708_vcio_resources,
3610 + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
3611 + .dev = {
3612 + .dma_mask = &vcio_dmamask,
3613 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3614 + },
3615 +};
3616 +
3617 +#ifdef CONFIG_BCM2708_GPIO
3618 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
3619 +
3620 +static struct resource bcm2708_gpio_resources[] = {
3621 + [0] = { /* general purpose I/O */
3622 + .start = GPIO_BASE,
3623 + .end = GPIO_BASE + SZ_4K - 1,
3624 + .flags = IORESOURCE_MEM,
3625 + },
3626 +};
3627 +
3628 +static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3629 +
3630 +static struct platform_device bcm2708_gpio_device = {
3631 + .name = BCM_GPIO_DRIVER_NAME,
3632 + .id = -1, /* only one VideoCore I/O area */
3633 + .resource = bcm2708_gpio_resources,
3634 + .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
3635 + .dev = {
3636 + .dma_mask = &gpio_dmamask,
3637 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3638 + },
3639 +};
3640 +#endif
3641 +
3642 +#ifdef SYSTEM_TIMER
3643 +static struct resource bcm2708_systemtimer_resources[] = {
3644 + [0] = { /* system timer access */
3645 + .start = ST_BASE,
3646 + .end = ST_BASE + SZ_4K - 1,
3647 + .flags = IORESOURCE_MEM,
3648 + },
3649 + {
3650 + .start = IRQ_TIMER3,
3651 + .end = IRQ_TIMER3,
3652 + .flags = IORESOURCE_IRQ,
3653 + }
3654 +
3655 +};
3656 +
3657 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3658 +
3659 +static struct platform_device bcm2708_systemtimer_device = {
3660 + .name = "bcm2708_systemtimer",
3661 + .id = -1, /* only one VideoCore I/O area */
3662 + .resource = bcm2708_systemtimer_resources,
3663 + .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
3664 + .dev = {
3665 + .dma_mask = &systemtimer_dmamask,
3666 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
3667 + },
3668 +};
3669 +#endif
3670 +
3671 +#ifdef CONFIG_MMC_BCM2835 /* Arasan emmc SD (new) */
3672 +static struct resource bcm2835_emmc_resources[] = {
3673 + [0] = {
3674 + .start = EMMC_BASE,
3675 + .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
3676 + /* the memory map actually makes SZ_4K available */
3677 + .flags = IORESOURCE_MEM,
3678 + },
3679 + [1] = {
3680 + .start = IRQ_ARASANSDIO,
3681 + .end = IRQ_ARASANSDIO,
3682 + .flags = IORESOURCE_IRQ,
3683 + },
3684 +};
3685 +
3686 +static u64 bcm2835_emmc_dmamask = 0xffffffffUL;
3687 +
3688 +struct platform_device bcm2835_emmc_device = {
3689 + .name = "mmc-bcm2835",
3690 + .id = 0,
3691 + .num_resources = ARRAY_SIZE(bcm2835_emmc_resources),
3692 + .resource = bcm2835_emmc_resources,
3693 + .dev = {
3694 + .dma_mask = &bcm2835_emmc_dmamask,
3695 + .coherent_dma_mask = 0xffffffffUL},
3696 +};
3697 +#endif /* CONFIG_MMC_BCM2835 */
3698 +
3699 +static struct resource bcm2708_powerman_resources[] = {
3700 + [0] = {
3701 + .start = PM_BASE,
3702 + .end = PM_BASE + SZ_256 - 1,
3703 + .flags = IORESOURCE_MEM,
3704 + },
3705 +};
3706 +
3707 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3708 +
3709 +struct platform_device bcm2708_powerman_device = {
3710 + .name = "bcm2708_powerman",
3711 + .id = 0,
3712 + .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
3713 + .resource = bcm2708_powerman_resources,
3714 + .dev = {
3715 + .dma_mask = &powerman_dmamask,
3716 + .coherent_dma_mask = 0xffffffffUL},
3717 +};
3718 +
3719 +
3720 +static struct platform_device bcm2708_alsa_devices[] = {
3721 + [0] = {
3722 + .name = "bcm2835_AUD0",
3723 + .id = 0, /* first audio device */
3724 + .resource = 0,
3725 + .num_resources = 0,
3726 + },
3727 + [1] = {
3728 + .name = "bcm2835_AUD1",
3729 + .id = 1, /* second audio device */
3730 + .resource = 0,
3731 + .num_resources = 0,
3732 + },
3733 + [2] = {
3734 + .name = "bcm2835_AUD2",
3735 + .id = 2, /* third audio device */
3736 + .resource = 0,
3737 + .num_resources = 0,
3738 + },
3739 + [3] = {
3740 + .name = "bcm2835_AUD3",
3741 + .id = 3, /* forth audio device */
3742 + .resource = 0,
3743 + .num_resources = 0,
3744 + },
3745 + [4] = {
3746 + .name = "bcm2835_AUD4",
3747 + .id = 4, /* fifth audio device */
3748 + .resource = 0,
3749 + .num_resources = 0,
3750 + },
3751 + [5] = {
3752 + .name = "bcm2835_AUD5",
3753 + .id = 5, /* sixth audio device */
3754 + .resource = 0,
3755 + .num_resources = 0,
3756 + },
3757 + [6] = {
3758 + .name = "bcm2835_AUD6",
3759 + .id = 6, /* seventh audio device */
3760 + .resource = 0,
3761 + .num_resources = 0,
3762 + },
3763 + [7] = {
3764 + .name = "bcm2835_AUD7",
3765 + .id = 7, /* eighth audio device */
3766 + .resource = 0,
3767 + .num_resources = 0,
3768 + },
3769 +};
3770 +
3771 +static struct resource bcm2708_spi_resources[] = {
3772 + {
3773 + .start = SPI0_BASE,
3774 + .end = SPI0_BASE + SZ_256 - 1,
3775 + .flags = IORESOURCE_MEM,
3776 + }, {
3777 + .start = IRQ_SPI,
3778 + .end = IRQ_SPI,
3779 + .flags = IORESOURCE_IRQ,
3780 + }
3781 +};
3782 +
3783 +
3784 +static u64 bcm2708_spi_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
3785 +static struct platform_device bcm2708_spi_device = {
3786 + .name = "bcm2708_spi",
3787 + .id = 0,
3788 + .num_resources = ARRAY_SIZE(bcm2708_spi_resources),
3789 + .resource = bcm2708_spi_resources,
3790 + .dev = {
3791 + .dma_mask = &bcm2708_spi_dmamask,
3792 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON)},
3793 +};
3794 +
3795 +#ifdef CONFIG_BCM2708_SPIDEV
3796 +static struct spi_board_info bcm2708_spi_devices[] = {
3797 +#ifdef CONFIG_SPI_SPIDEV
3798 + {
3799 + .modalias = "spidev",
3800 + .max_speed_hz = 500000,
3801 + .bus_num = 0,
3802 + .chip_select = 0,
3803 + .mode = SPI_MODE_0,
3804 + }, {
3805 + .modalias = "spidev",
3806 + .max_speed_hz = 500000,
3807 + .bus_num = 0,
3808 + .chip_select = 1,
3809 + .mode = SPI_MODE_0,
3810 + }
3811 +#endif
3812 +};
3813 +#endif
3814 +
3815 +static struct resource bcm2708_bsc0_resources[] = {
3816 + {
3817 + .start = BSC0_BASE,
3818 + .end = BSC0_BASE + SZ_256 - 1,
3819 + .flags = IORESOURCE_MEM,
3820 + }, {
3821 + .start = INTERRUPT_I2C,
3822 + .end = INTERRUPT_I2C,
3823 + .flags = IORESOURCE_IRQ,
3824 + }
3825 +};
3826 +
3827 +static struct platform_device bcm2708_bsc0_device = {
3828 + .name = "bcm2708_i2c",
3829 + .id = 0,
3830 + .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources),
3831 + .resource = bcm2708_bsc0_resources,
3832 +};
3833 +
3834 +
3835 +static struct resource bcm2708_bsc1_resources[] = {
3836 + {
3837 + .start = BSC1_BASE,
3838 + .end = BSC1_BASE + SZ_256 - 1,
3839 + .flags = IORESOURCE_MEM,
3840 + }, {
3841 + .start = INTERRUPT_I2C,
3842 + .end = INTERRUPT_I2C,
3843 + .flags = IORESOURCE_IRQ,
3844 + }
3845 +};
3846 +
3847 +static struct platform_device bcm2708_bsc1_device = {
3848 + .name = "bcm2708_i2c",
3849 + .id = 1,
3850 + .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources),
3851 + .resource = bcm2708_bsc1_resources,
3852 +};
3853 +
3854 +static struct platform_device bcm2835_hwmon_device = {
3855 + .name = "bcm2835_hwmon",
3856 +};
3857 +
3858 +static struct platform_device bcm2835_thermal_device = {
3859 + .name = "bcm2835_thermal",
3860 +};
3861 +
3862 +#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
3863 +static struct resource bcm2708_i2s_resources[] = {
3864 + {
3865 + .start = I2S_BASE,
3866 + .end = I2S_BASE + 0x20,
3867 + .flags = IORESOURCE_MEM,
3868 + },
3869 + {
3870 + .start = PCM_CLOCK_BASE,
3871 + .end = PCM_CLOCK_BASE + 0x02,
3872 + .flags = IORESOURCE_MEM,
3873 + }
3874 +};
3875 +
3876 +static struct platform_device bcm2708_i2s_device = {
3877 + .name = "bcm2708-i2s",
3878 + .id = 0,
3879 + .num_resources = ARRAY_SIZE(bcm2708_i2s_resources),
3880 + .resource = bcm2708_i2s_resources,
3881 +};
3882 +#endif
3883 +
3884 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
3885 +static struct platform_device snd_hifiberry_dac_device = {
3886 + .name = "snd-hifiberry-dac",
3887 + .id = 0,
3888 + .num_resources = 0,
3889 +};
3890 +
3891 +static struct platform_device snd_pcm5102a_codec_device = {
3892 + .name = "pcm5102a-codec",
3893 + .id = -1,
3894 + .num_resources = 0,
3895 +};
3896 +#endif
3897 +
3898 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
3899 +static struct platform_device snd_rpi_hifiberry_dacplus_device = {
3900 + .name = "snd-rpi-hifiberry-dacplus",
3901 + .id = 0,
3902 + .num_resources = 0,
3903 +};
3904 +
3905 +static struct i2c_board_info __initdata snd_pcm512x_hbdacplus_i2c_devices[] = {
3906 + {
3907 + I2C_BOARD_INFO("pcm5122", 0x4d)
3908 + },
3909 +};
3910 +#endif
3911 +
3912 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
3913 +static struct platform_device snd_hifiberry_digi_device = {
3914 + .name = "snd-hifiberry-digi",
3915 + .id = 0,
3916 + .num_resources = 0,
3917 +};
3918 +
3919 +static struct i2c_board_info __initdata snd_wm8804_i2c_devices[] = {
3920 + {
3921 + I2C_BOARD_INFO("wm8804", 0x3b)
3922 + },
3923 +};
3924 +
3925 +#endif
3926 +
3927 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
3928 +static struct platform_device snd_hifiberry_amp_device = {
3929 + .name = "snd-hifiberry-amp",
3930 + .id = 0,
3931 + .num_resources = 0,
3932 +};
3933 +
3934 +static struct i2c_board_info __initdata snd_tas5713_i2c_devices[] = {
3935 + {
3936 + I2C_BOARD_INFO("tas5713", 0x1b)
3937 + },
3938 +};
3939 +#endif
3940 +
3941 +#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
3942 +static struct platform_device snd_rpi_dac_device = {
3943 + .name = "snd-rpi-dac",
3944 + .id = 0,
3945 + .num_resources = 0,
3946 +};
3947 +
3948 +static struct platform_device snd_pcm1794a_codec_device = {
3949 + .name = "pcm1794a-codec",
3950 + .id = -1,
3951 + .num_resources = 0,
3952 +};
3953 +#endif
3954 +
3955 +
3956 +#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
3957 +static struct platform_device snd_rpi_iqaudio_dac_device = {
3958 + .name = "snd-rpi-iqaudio-dac",
3959 + .id = 0,
3960 + .num_resources = 0,
3961 +};
3962 +
3963 +// Use the actual device name rather than generic driver name
3964 +static struct i2c_board_info __initdata snd_pcm512x_i2c_devices[] = {
3965 + {
3966 + I2C_BOARD_INFO("pcm5122", 0x4c)
3967 + },
3968 +};
3969 +#endif
3970 +
3971 +int __init bcm_register_device(struct platform_device *pdev)
3972 +{
3973 + int ret;
3974 +
3975 + ret = platform_device_register(pdev);
3976 + if (ret)
3977 + pr_debug("Unable to register platform device '%s': %d\n",
3978 + pdev->name, ret);
3979 +
3980 + return ret;
3981 +}
3982 +
3983 +/*
3984 + * Use these macros for platform and i2c devices that are present in the
3985 + * Device Tree. This way the devices are only added on non-DT systems.
3986 + */
3987 +#define bcm_register_device_dt(pdev) \
3988 + if (!use_dt) bcm_register_device(pdev)
3989 +
3990 +#define i2c_register_board_info_dt(busnum, info, n) \
3991 + if (!use_dt) i2c_register_board_info(busnum, info, n)
3992 +
3993 +int calc_rsts(int partition)
3994 +{
3995 + return PM_PASSWORD |
3996 + ((partition & (1 << 0)) << 0) |
3997 + ((partition & (1 << 1)) << 1) |
3998 + ((partition & (1 << 2)) << 2) |
3999 + ((partition & (1 << 3)) << 3) |
4000 + ((partition & (1 << 4)) << 4) |
4001 + ((partition & (1 << 5)) << 5);
4002 +}
4003 +
4004 +static void bcm2709_restart(enum reboot_mode mode, const char *cmd)
4005 +{
4006 + extern char bcm2708_reboot_mode;
4007 + uint32_t pm_rstc, pm_wdog;
4008 + uint32_t timeout = 10;
4009 + uint32_t pm_rsts = 0;
4010 +
4011 + if(bcm2708_reboot_mode == 'q')
4012 + {
4013 + // NOOBS < 1.3 booting with reboot=q
4014 + pm_rsts = readl(__io_address(PM_RSTS));
4015 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
4016 + }
4017 + else if(bcm2708_reboot_mode == 'p')
4018 + {
4019 + // NOOBS < 1.3 halting
4020 + pm_rsts = readl(__io_address(PM_RSTS));
4021 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
4022 + }
4023 + else
4024 + {
4025 + pm_rsts = calc_rsts(reboot_part);
4026 + }
4027 +
4028 + writel(pm_rsts, __io_address(PM_RSTS));
4029 +
4030 + /* Setup watchdog for reset */
4031 + pm_rstc = readl(__io_address(PM_RSTC));
4032 +
4033 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
4034 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
4035 +
4036 + writel(pm_wdog, __io_address(PM_WDOG));
4037 + writel(pm_rstc, __io_address(PM_RSTC));
4038 +}
4039 +
4040 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
4041 +static void bcm2709_power_off(void)
4042 +{
4043 + extern char bcm2708_reboot_mode;
4044 + if(bcm2708_reboot_mode == 'q')
4045 + {
4046 + // NOOBS < v1.3
4047 + bcm2709_restart('p', "");
4048 + }
4049 + else
4050 + {
4051 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
4052 + reboot_part = 63;
4053 + /* continue with normal reset mechanism */
4054 + bcm2709_restart(0, "");
4055 + }
4056 +}
4057 +
4058 +#ifdef CONFIG_OF
4059 +static void __init bcm2709_dt_init(void)
4060 +{
4061 + int ret;
4062 +
4063 + ret = of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
4064 + if (ret) {
4065 + pr_err("of_platform_populate failed: %d\n", ret);
4066 + use_dt = 0;
4067 + }
4068 +}
4069 +#else
4070 +static void __init bcm2709_dt_init(void) { }
4071 +#endif /* CONFIG_OF */
4072 +
4073 +void __init bcm2709_init(void)
4074 +{
4075 + int i;
4076 +
4077 +#if defined(CONFIG_BCM_VC_CMA)
4078 + vc_cma_early_init();
4079 +#endif
4080 + printk("bcm2709.uart_clock = %d\n", uart_clock);
4081 + pm_power_off = bcm2709_power_off;
4082 +
4083 + bcm2709_init_clocks();
4084 + if (use_dt)
4085 + bcm2709_dt_init();
4086 +
4087 + bcm_register_device(&bcm2708_dmaman_device);
4088 + bcm_register_device(&bcm2708_vcio_device);
4089 +#ifdef CONFIG_BCM2708_GPIO
4090 + bcm_register_device_dt(&bcm2708_gpio_device);
4091 +#endif
4092 +#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE)
4093 + w1_gpio_pdata.pin = w1_gpio_pin;
4094 + w1_gpio_pdata.ext_pullup_enable_pin = w1_gpio_pullup;
4095 + bcm_register_device_dt(&w1_device);
4096 +#endif
4097 +#ifdef SYSTEM_TIMER
4098 + bcm_register_device(&bcm2708_systemtimer_device);
4099 +#endif
4100 + bcm_register_device(&bcm2708_fb_device);
4101 + bcm_register_device(&bcm2708_usb_device);
4102 + bcm_register_device(&bcm2708_uart1_device);
4103 + bcm_register_device(&bcm2708_powerman_device);
4104 +
4105 +#ifdef CONFIG_MMC_BCM2835
4106 + bcm_register_device(&bcm2835_emmc_device);
4107 +#endif
4108 + bcm2709_init_led();
4109 + for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++)
4110 + bcm_register_device(&bcm2708_alsa_devices[i]);
4111 +
4112 + bcm_register_device(&bcm2835_hwmon_device);
4113 + bcm_register_device(&bcm2835_thermal_device);
4114 +
4115 + bcm_register_device_dt(&bcm2708_spi_device);
4116 + bcm_register_device_dt(&bcm2708_bsc0_device);
4117 + bcm_register_device_dt(&bcm2708_bsc1_device);
4118 +
4119 +#if defined(CONFIG_SND_BCM2708_SOC_I2S) || defined(CONFIG_SND_BCM2708_SOC_I2S_MODULE)
4120 + bcm_register_device_dt(&bcm2708_i2s_device);
4121 +#endif
4122 +
4123 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DAC_MODULE)
4124 + bcm_register_device_dt(&snd_hifiberry_dac_device);
4125 + bcm_register_device_dt(&snd_pcm5102a_codec_device);
4126 +#endif
4127 +
4128 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DACPLUS_MODULE)
4129 + bcm_register_device_dt(&snd_rpi_hifiberry_dacplus_device);
4130 + i2c_register_board_info_dt(1, snd_pcm512x_hbdacplus_i2c_devices, ARRAY_SIZE(snd_pcm512x_hbdacplus_i2c_devices));
4131 +#endif
4132 +
4133 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_DIGI_MODULE)
4134 + bcm_register_device_dt(&snd_hifiberry_digi_device);
4135 + i2c_register_board_info_dt(1, snd_wm8804_i2c_devices, ARRAY_SIZE(snd_wm8804_i2c_devices));
4136 +#endif
4137 +
4138 +#if defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP) || defined(CONFIG_SND_BCM2708_SOC_HIFIBERRY_AMP_MODULE)
4139 + bcm_register_device_dt(&snd_hifiberry_amp_device);
4140 + i2c_register_board_info_dt(1, snd_tas5713_i2c_devices, ARRAY_SIZE(snd_tas5713_i2c_devices));
4141 +#endif
4142 +
4143 +#if defined(CONFIG_SND_BCM2708_SOC_RPI_DAC) || defined(CONFIG_SND_BCM2708_SOC_RPI_DAC_MODULE)
4144 + bcm_register_device_dt(&snd_rpi_dac_device);
4145 + bcm_register_device_dt(&snd_pcm1794a_codec_device);
4146 +#endif
4147 +
4148 +#if defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC) || defined(CONFIG_SND_BCM2708_SOC_IQAUDIO_DAC_MODULE)
4149 + bcm_register_device_dt(&snd_rpi_iqaudio_dac_device);
4150 + i2c_register_board_info_dt(1, snd_pcm512x_i2c_devices, ARRAY_SIZE(snd_pcm512x_i2c_devices));
4151 +#endif
4152 +
4153 +
4154 + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
4155 + struct amba_device *d = amba_devs[i];
4156 + amba_device_register(d, &iomem_resource);
4157 + }
4158 + system_rev = boardrev;
4159 + system_serial_low = serial;
4160 +
4161 +#ifdef CONFIG_BCM2708_SPIDEV
4162 + if (!use_dt)
4163 + spi_register_board_info(bcm2708_spi_devices,
4164 + ARRAY_SIZE(bcm2708_spi_devices));
4165 +#endif
4166 +}
4167 +
4168 +#ifdef SYSTEM_TIMER
4169 +static void timer_set_mode(enum clock_event_mode mode,
4170 + struct clock_event_device *clk)
4171 +{
4172 + switch (mode) {
4173 + case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
4174 + case CLOCK_EVT_MODE_SHUTDOWN:
4175 + break;
4176 + case CLOCK_EVT_MODE_PERIODIC:
4177 +
4178 + case CLOCK_EVT_MODE_UNUSED:
4179 + case CLOCK_EVT_MODE_RESUME:
4180 +
4181 + default:
4182 + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
4183 + (int)mode);
4184 + break;
4185 + }
4186 +
4187 +}
4188 +
4189 +static int timer_set_next_event(unsigned long cycles,
4190 + struct clock_event_device *unused)
4191 +{
4192 + unsigned long stc;
4193 + do {
4194 + stc = readl(__io_address(ST_BASE + 0x04));
4195 + /* We could take a FIQ here, which may push ST above STC3 */
4196 + writel(stc + cycles, __io_address(ST_BASE + 0x18));
4197 + } while ((signed long) cycles >= 0 &&
4198 + (signed long) (readl(__io_address(ST_BASE + 0x04)) - stc)
4199 + >= (signed long) cycles);
4200 + return 0;
4201 +}
4202 +
4203 +static struct clock_event_device timer0_clockevent = {
4204 + .name = "timer0",
4205 + .shift = 32,
4206 + .features = CLOCK_EVT_FEAT_ONESHOT,
4207 + .set_mode = timer_set_mode,
4208 + .set_next_event = timer_set_next_event,
4209 +};
4210 +
4211 +/*
4212 + * IRQ handler for the timer
4213 + */
4214 +static irqreturn_t bcm2709_timer_interrupt(int irq, void *dev_id)
4215 +{
4216 + struct clock_event_device *evt = &timer0_clockevent;
4217 +
4218 + writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
4219 +
4220 + evt->event_handler(evt);
4221 +
4222 + return IRQ_HANDLED;
4223 +}
4224 +
4225 +static struct irqaction bcm2709_timer_irq = {
4226 + .name = "BCM2709 Timer Tick",
4227 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
4228 + .handler = bcm2709_timer_interrupt,
4229 +};
4230 +
4231 +/*
4232 + * Set up timer interrupt, and return the current time in seconds.
4233 + */
4234 +
4235 +static struct delay_timer bcm2709_delay_timer = {
4236 + .read_current_timer = bcm2709_read_current_timer,
4237 + .freq = STC_FREQ_HZ,
4238 +};
4239 +
4240 +static void __init bcm2709_timer_init(void)
4241 +{
4242 + /* init high res timer */
4243 + bcm2709_clocksource_init();
4244 +
4245 + /*
4246 + * Make irqs happen for the system timer
4247 + */
4248 + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
4249 +
4250 + sched_clock_register(bcm2709_read_sched_clock, 32, STC_FREQ_HZ);
4251 +
4252 + timer0_clockevent.mult =
4253 + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
4254 + timer0_clockevent.max_delta_ns =
4255 + clockevent_delta2ns(0xffffffff, &timer0_clockevent);
4256 + timer0_clockevent.min_delta_ns =
4257 + clockevent_delta2ns(0xf, &timer0_clockevent);
4258 +
4259 + timer0_clockevent.cpumask = cpumask_of(0);
4260 + clockevents_register_device(&timer0_clockevent);
4261 +
4262 + register_current_timer_delay(&bcm2708_delay_timer);
4263 +}
4264 +
4265 +#else
4266 +
4267 +static void __init bcm2709_timer_init(void)
4268 +{
4269 + extern void dc4_arch_timer_init(void);
4270 + // timer control
4271 + writel(0, __io_address(ARM_LOCAL_CONTROL));
4272 + // timer pre_scaler
4273 + writel(0x80000000, __io_address(ARM_LOCAL_PRESCALER)); // 19.2MHz
4274 + //writel(0x06AAAAAB, __io_address(ARM_LOCAL_PRESCALER)); // 1MHz
4275 +
4276 + if (use_dt)
4277 + {
4278 + of_clk_init(NULL);
4279 + clocksource_of_init();
4280 + }
4281 + else
4282 + dc4_arch_timer_init();
4283 +}
4284 +
4285 +#endif
4286 +
4287 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
4288 +#include <linux/leds.h>
4289 +
4290 +static struct gpio_led bcm2709_leds[] = {
4291 + [0] = {
4292 + .gpio = 16,
4293 + .name = "led0",
4294 + .default_trigger = "mmc0",
4295 + .active_low = 1,
4296 + },
4297 +};
4298 +
4299 +static struct gpio_led_platform_data bcm2709_led_pdata = {
4300 + .num_leds = ARRAY_SIZE(bcm2709_leds),
4301 + .leds = bcm2709_leds,
4302 +};
4303 +
4304 +static struct platform_device bcm2709_led_device = {
4305 + .name = "leds-gpio",
4306 + .id = -1,
4307 + .dev = {
4308 + .platform_data = &bcm2709_led_pdata,
4309 + },
4310 +};
4311 +
4312 +static void __init bcm2709_init_led(void)
4313 +{
4314 + bcm2709_leds[0].gpio = disk_led_gpio;
4315 + bcm2709_leds[0].active_low = disk_led_active_low;
4316 + bcm_register_device_dt(&bcm2709_led_device);
4317 +}
4318 +#else
4319 +static inline void bcm2709_init_led(void)
4320 +{
4321 +}
4322 +#endif
4323 +
4324 +void __init bcm2709_init_early(void)
4325 +{
4326 + /*
4327 + * Some devices allocate their coherent buffers from atomic
4328 + * context. Increase size of atomic coherent pool to make sure such
4329 + * the allocations won't fail.
4330 + */
4331 + init_dma_coherent_pool_size(SZ_4M);
4332 +
4333 +#ifdef CONFIG_OF
4334 + if (of_allnodes)
4335 + use_dt = 1;
4336 +#endif
4337 +}
4338 +
4339 +static void __init board_reserve(void)
4340 +{
4341 +#if defined(CONFIG_BCM_VC_CMA)
4342 + vc_cma_reserve();
4343 +#endif
4344 +}
4345 +
4346 +
4347 +#include <linux/smp.h>
4348 +
4349 +#include <mach/hardware.h>
4350 +#include <asm/cacheflush.h>
4351 +#include <asm/smp_plat.h>
4352 +int dc4=0;
4353 +//void dc4_log(unsigned x) { if (dc4) writel((x), __io_address(ST_BASE+10 + raw_smp_processor_id()*4)); }
4354 +void dc4_log_dead(unsigned x) { if (dc4) writel((readl(__io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)) & 0xffff) | ((x)<<16), __io_address(ST_BASE+0x10 + raw_smp_processor_id()*4)); }
4355 +
4356 +static void bcm2835_send_doorbell(const struct cpumask *mask, unsigned int irq)
4357 +{
4358 + int cpu;
4359 + /*
4360 + * Ensure that stores to Normal memory are visible to the
4361 + * other CPUs before issuing the IPI.
4362 + */
4363 + dsb();
4364 +
4365 + /* Convert our logical CPU mask into a physical one. */
4366 + for_each_cpu(cpu, mask)
4367 + {
4368 + /* submit softirq */
4369 + writel(1<<irq, __io_address(ARM_LOCAL_MAILBOX0_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0)));
4370 + }
4371 +}
4372 +
4373 +void __init bcm2709_smp_init_cpus(void)
4374 +{
4375 + void secondary_startup(void);
4376 + unsigned int i, ncores;
4377 +
4378 + ncores = 4; // xxx scu_get_core_count(NULL);
4379 + printk("[%s] enter (%x->%x)\n", __FUNCTION__, (unsigned)virt_to_phys((void *)secondary_startup), (unsigned)__io_address(ST_BASE + 0x10));
4380 + printk("[%s] ncores=%d\n", __FUNCTION__, ncores);
4381 +
4382 + for (i = 0; i < ncores; i++) {
4383 + set_cpu_possible(i, true);
4384 + /* enable IRQ (not FIQ) */
4385 + writel(0x1, __io_address(ARM_LOCAL_MAILBOX_INT_CONTROL0 + 0x4 * i));
4386 + //writel(0xf, __io_address(ARM_LOCAL_TIMER_INT_CONTROL0 + 0x4 * i));
4387 + }
4388 + set_smp_cross_call(bcm2835_send_doorbell);
4389 +}
4390 +
4391 +/*
4392 + * for arch/arm/kernel/smp.c:smp_prepare_cpus(unsigned int max_cpus)
4393 + */
4394 +void __init bcm2709_smp_prepare_cpus(unsigned int max_cpus)
4395 +{
4396 + //void __iomem *scu_base;
4397 +
4398 + printk("[%s] enter\n", __FUNCTION__);
4399 + //scu_base = scu_base_addr();
4400 + //scu_enable(scu_base);
4401 +}
4402 +
4403 +/*
4404 + * for linux/arch/arm/kernel/smp.c:secondary_start_kernel(void)
4405 + */
4406 +void __cpuinit bcm2709_secondary_init(unsigned int cpu)
4407 +{
4408 + printk("[%s] enter cpu:%d\n", __FUNCTION__, cpu);
4409 + //gic_secondary_init(0);
4410 +}
4411 +
4412 +/*
4413 + * for linux/arch/arm/kernel/smp.c:__cpu_up(..)
4414 + */
4415 +int __cpuinit bcm2709_boot_secondary(unsigned int cpu, struct task_struct *idle)
4416 +{
4417 + void secondary_startup(void);
4418 + void *mbox_set = __io_address(ARM_LOCAL_MAILBOX3_SET0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
4419 + void *mbox_clr = __io_address(ARM_LOCAL_MAILBOX3_CLR0 + 0x10 * MPIDR_AFFINITY_LEVEL(cpu_logical_map(cpu), 0));
4420 + unsigned secondary_boot = (unsigned)virt_to_phys((void *)secondary_startup);
4421 + int timeout=20;
4422 + unsigned t = -1;
4423 + //printk("[%s] enter cpu:%d (%x->%p) %x\n", __FUNCTION__, cpu, secondary_boot, wake, readl(wake));
4424 +
4425 + dsb();
4426 + BUG_ON(readl(mbox_clr) != 0);
4427 + writel(secondary_boot, mbox_set);
4428 +
4429 + while (--timeout > 0) {
4430 + t = readl(mbox_clr);
4431 + if (t == 0) break;
4432 + cpu_relax();
4433 + }
4434 + if (timeout==0)
4435 + printk("[%s] cpu:%d failed to start (%x)\n", __FUNCTION__, cpu, t);
4436 + else
4437 + printk("[%s] cpu:%d started (%x) %d\n", __FUNCTION__, cpu, t, timeout);
4438 +
4439 + return 0;
4440 +}
4441 +
4442 +
4443 +struct smp_operations bcm2709_smp_ops __initdata = {
4444 + .smp_init_cpus = bcm2709_smp_init_cpus,
4445 + .smp_prepare_cpus = bcm2709_smp_prepare_cpus,
4446 + .smp_secondary_init = bcm2709_secondary_init,
4447 + .smp_boot_secondary = bcm2709_boot_secondary,
4448 +};
4449 +
4450 +static const char * const bcm2709_compat[] = {
4451 + "brcm,bcm2709",
4452 + "brcm,bcm2708", /* Could use bcm2708 in a pinch */
4453 + NULL
4454 +};
4455 +
4456 +MACHINE_START(BCM2709, "BCM2709")
4457 + /* Maintainer: Broadcom Europe Ltd. */
4458 + .smp = smp_ops(bcm2709_smp_ops),
4459 + .map_io = bcm2709_map_io,
4460 + .init_irq = bcm2709_init_irq,
4461 + .init_time = bcm2709_timer_init,
4462 + .init_machine = bcm2709_init,
4463 + .init_early = bcm2709_init_early,
4464 + .reserve = board_reserve,
4465 + .restart = bcm2709_restart,
4466 + .dt_compat = bcm2709_compat,
4467 +MACHINE_END
4468 +
4469 +module_param(boardrev, uint, 0644);
4470 +module_param(serial, uint, 0644);
4471 +module_param(uart_clock, uint, 0644);
4472 +module_param(disk_led_gpio, uint, 0644);
4473 +module_param(disk_led_active_low, uint, 0644);
4474 +module_param(reboot_part, uint, 0644);
4475 +module_param(w1_gpio_pin, uint, 0644);
4476 +module_param(w1_gpio_pullup, uint, 0644);
4477 diff --git a/arch/arm/mach-bcm2709/bcm2709.h b/arch/arm/mach-bcm2709/bcm2709.h
4478 new file mode 100644
4479 index 0000000..e339a93
4480 --- /dev/null
4481 +++ b/arch/arm/mach-bcm2709/bcm2709.h
4482 @@ -0,0 +1,49 @@
4483 +/*
4484 + * linux/arch/arm/mach-bcm2708/bcm2708.h
4485 + *
4486 + * BCM2708 machine support header
4487 + *
4488 + * Copyright (C) 2010 Broadcom
4489 + *
4490 + * This program is free software; you can redistribute it and/or modify
4491 + * it under the terms of the GNU General Public License as published by
4492 + * the Free Software Foundation; either version 2 of the License, or
4493 + * (at your option) any later version.
4494 + *
4495 + * This program is distributed in the hope that it will be useful,
4496 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4497 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4498 + * GNU General Public License for more details.
4499 + *
4500 + * You should have received a copy of the GNU General Public License
4501 + * along with this program; if not, write to the Free Software
4502 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4503 + */
4504 +
4505 +#ifndef __BCM2708_BCM2708_H
4506 +#define __BCM2708_BCM2708_H
4507 +
4508 +#include <linux/amba/bus.h>
4509 +
4510 +extern void __init bcm2708_init(void);
4511 +extern void __init bcm2708_init_irq(void);
4512 +extern void __init bcm2708_map_io(void);
4513 +extern struct sys_timer bcm2708_timer;
4514 +extern unsigned int mmc_status(struct device *dev);
4515 +
4516 +#define AMBA_DEVICE(name, busid, base, plat) \
4517 +static struct amba_device name##_device = { \
4518 + .dev = { \
4519 + .coherent_dma_mask = ~0, \
4520 + .init_name = busid, \
4521 + .platform_data = plat, \
4522 + }, \
4523 + .res = { \
4524 + .start = base##_BASE, \
4525 + .end = (base##_BASE) + SZ_4K - 1,\
4526 + .flags = IORESOURCE_MEM, \
4527 + }, \
4528 + .irq = base##_IRQ, \
4529 +}
4530 +
4531 +#endif
4532 diff --git a/arch/arm/mach-bcm2709/clock.c b/arch/arm/mach-bcm2709/clock.c
4533 new file mode 100644
4534 index 0000000..4fc556e
4535 --- /dev/null
4536 +++ b/arch/arm/mach-bcm2709/clock.c
4537 @@ -0,0 +1,61 @@
4538 +/*
4539 + * linux/arch/arm/mach-bcm2708/clock.c
4540 + *
4541 + * Copyright (C) 2010 Broadcom
4542 + *
4543 + * This program is free software; you can redistribute it and/or modify
4544 + * it under the terms of the GNU General Public License as published by
4545 + * the Free Software Foundation; either version 2 of the License, or
4546 + * (at your option) any later version.
4547 + *
4548 + * This program is distributed in the hope that it will be useful,
4549 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4550 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4551 + * GNU General Public License for more details.
4552 + *
4553 + * You should have received a copy of the GNU General Public License
4554 + * along with this program; if not, write to the Free Software
4555 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4556 + */
4557 +#include <linux/module.h>
4558 +#include <linux/kernel.h>
4559 +#include <linux/device.h>
4560 +#include <linux/list.h>
4561 +#include <linux/errno.h>
4562 +#include <linux/err.h>
4563 +#include <linux/string.h>
4564 +#include <linux/clk.h>
4565 +#include <linux/mutex.h>
4566 +
4567 +#include <asm/clkdev.h>
4568 +
4569 +#include "clock.h"
4570 +
4571 +int clk_enable(struct clk *clk)
4572 +{
4573 + return 0;
4574 +}
4575 +EXPORT_SYMBOL(clk_enable);
4576 +
4577 +void clk_disable(struct clk *clk)
4578 +{
4579 +}
4580 +EXPORT_SYMBOL(clk_disable);
4581 +
4582 +unsigned long clk_get_rate(struct clk *clk)
4583 +{
4584 + return clk->rate;
4585 +}
4586 +EXPORT_SYMBOL(clk_get_rate);
4587 +
4588 +long clk_round_rate(struct clk *clk, unsigned long rate)
4589 +{
4590 + return clk->rate;
4591 +}
4592 +EXPORT_SYMBOL(clk_round_rate);
4593 +
4594 +int clk_set_rate(struct clk *clk, unsigned long rate)
4595 +{
4596 + return -EIO;
4597 +}
4598 +EXPORT_SYMBOL(clk_set_rate);
4599 diff --git a/arch/arm/mach-bcm2709/clock.h b/arch/arm/mach-bcm2709/clock.h
4600 new file mode 100644
4601 index 0000000..5f9d725
4602 --- /dev/null
4603 +++ b/arch/arm/mach-bcm2709/clock.h
4604 @@ -0,0 +1,24 @@
4605 +/*
4606 + * linux/arch/arm/mach-bcm2708/clock.h
4607 + *
4608 + * Copyright (C) 2010 Broadcom
4609 + *
4610 + * This program is free software; you can redistribute it and/or modify
4611 + * it under the terms of the GNU General Public License as published by
4612 + * the Free Software Foundation; either version 2 of the License, or
4613 + * (at your option) any later version.
4614 + *
4615 + * This program is distributed in the hope that it will be useful,
4616 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4617 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4618 + * GNU General Public License for more details.
4619 + *
4620 + * You should have received a copy of the GNU General Public License
4621 + * along with this program; if not, write to the Free Software
4622 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4623 + */
4624 +struct module;
4625 +
4626 +struct clk {
4627 + unsigned long rate;
4628 +};
4629 diff --git a/arch/arm/mach-bcm2709/delay.S b/arch/arm/mach-bcm2709/delay.S
4630 new file mode 100644
4631 index 0000000..06f4780
4632 --- /dev/null
4633 +++ b/arch/arm/mach-bcm2709/delay.S
4634 @@ -0,0 +1,21 @@
4635 +/*
4636 + * linux/arch/arm/lib/delay.S
4637 + *
4638 + * Copyright (C) 1995, 1996 Russell King
4639 + *
4640 + * This program is free software; you can redistribute it and/or modify
4641 + * it under the terms of the GNU General Public License version 2 as
4642 + * published by the Free Software Foundation.
4643 + */
4644 +#include <linux/linkage.h>
4645 +#include <asm/assembler.h>
4646 +#include <asm/param.h>
4647 +
4648 + .text
4649 +.align 3 @ 8 byte alignment seems to be needed to avoid fetching stalls
4650 +@ Delay routine
4651 +ENTRY(bcm2708_delay)
4652 + subs r0, r0, #1
4653 + bhi bcm2708_delay
4654 + mov pc, lr
4655 +ENDPROC(bcm2708_delay)
4656 diff --git a/arch/arm/mach-bcm2709/dma.c b/arch/arm/mach-bcm2709/dma.c
4657 new file mode 100644
4658 index 0000000..a5e58d1
4659 --- /dev/null
4660 +++ b/arch/arm/mach-bcm2709/dma.c
4661 @@ -0,0 +1,409 @@
4662 +/*
4663 + * linux/arch/arm/mach-bcm2708/dma.c
4664 + *
4665 + * Copyright (C) 2010 Broadcom
4666 + *
4667 + * This program is free software; you can redistribute it and/or modify
4668 + * it under the terms of the GNU General Public License version 2 as
4669 + * published by the Free Software Foundation.
4670 + */
4671 +
4672 +#include <linux/slab.h>
4673 +#include <linux/device.h>
4674 +#include <linux/platform_device.h>
4675 +#include <linux/module.h>
4676 +#include <linux/scatterlist.h>
4677 +
4678 +#include <mach/dma.h>
4679 +#include <mach/irqs.h>
4680 +
4681 +/*****************************************************************************\
4682 + * *
4683 + * Configuration *
4684 + * *
4685 +\*****************************************************************************/
4686 +
4687 +#define CACHE_LINE_MASK 31
4688 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
4689 +#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
4690 +
4691 +/* valid only for channels 0 - 14, 15 has its own base address */
4692 +#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
4693 +#define BCM2708_DMA_CHANIO(dma_base, n) \
4694 + ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
4695 +
4696 +
4697 +/*****************************************************************************\
4698 + * *
4699 + * DMA Auxilliary Functions *
4700 + * *
4701 +\*****************************************************************************/
4702 +
4703 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
4704 + section inside the DMA buffer and another section outside it.
4705 + Even if we flush DMA buffers from the cache there is always the chance that
4706 + during a DMA someone will access the part of a cache line that is outside
4707 + the DMA buffer - which will then bring in unwelcome data.
4708 + Without being able to dictate our own buffer pools we must insist that
4709 + DMA buffers consist of a whole number of cache lines.
4710 +*/
4711 +
4712 +extern int
4713 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
4714 +{
4715 + int i;
4716 +
4717 + for (i = 0; i < sg_len; i++) {
4718 + if (sg_ptr[i].offset & CACHE_LINE_MASK ||
4719 + sg_ptr[i].length & CACHE_LINE_MASK)
4720 + return 0;
4721 + }
4722 +
4723 + return 1;
4724 +}
4725 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
4726 +
4727 +extern void
4728 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
4729 +{
4730 + dsb(); /* ARM data synchronization (push) operation */
4731 +
4732 + writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
4733 + writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
4734 +}
4735 +
4736 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
4737 +{
4738 + dsb();
4739 +
4740 + /* ugly busy wait only option for now */
4741 + while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
4742 + cpu_relax();
4743 +}
4744 +
4745 +EXPORT_SYMBOL_GPL(bcm_dma_start);
4746 +
4747 +extern bool bcm_dma_is_busy(void __iomem *dma_chan_base)
4748 +{
4749 + dsb();
4750 +
4751 + return readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE;
4752 +}
4753 +EXPORT_SYMBOL_GPL(bcm_dma_is_busy);
4754 +
4755 +/* Complete an ongoing DMA (assuming its results are to be ignored)
4756 + Does nothing if there is no DMA in progress.
4757 + This routine waits for the current AXI transfer to complete before
4758 + terminating the current DMA. If the current transfer is hung on a DREQ used
4759 + by an uncooperative peripheral the AXI transfer may never complete. In this
4760 + case the routine times out and return a non-zero error code.
4761 + Use of this routine doesn't guarantee that the ongoing or aborted DMA
4762 + does not produce an interrupt.
4763 +*/
4764 +extern int
4765 +bcm_dma_abort(void __iomem *dma_chan_base)
4766 +{
4767 + unsigned long int cs;
4768 + int rc = 0;
4769 +
4770 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
4771 +
4772 + if (BCM2708_DMA_ACTIVE & cs) {
4773 + long int timeout = 10000;
4774 +
4775 + /* write 0 to the active bit - pause the DMA */
4776 + writel(0, dma_chan_base + BCM2708_DMA_CS);
4777 +
4778 + /* wait for any current AXI transfer to complete */
4779 + while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
4780 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
4781 +
4782 + if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
4783 + /* we'll un-pause when we set of our next DMA */
4784 + rc = -ETIMEDOUT;
4785 +
4786 + } else if (BCM2708_DMA_ACTIVE & cs) {
4787 + /* terminate the control block chain */
4788 + writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
4789 +
4790 + /* abort the whole DMA */
4791 + writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
4792 + dma_chan_base + BCM2708_DMA_CS);
4793 + }
4794 + }
4795 +
4796 + return rc;
4797 +}
4798 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
4799 +
4800 +
4801 +/***************************************************************************** \
4802 + * *
4803 + * DMA Manager Device Methods *
4804 + * *
4805 +\*****************************************************************************/
4806 +
4807 +struct vc_dmaman {
4808 + void __iomem *dma_base;
4809 + u32 chan_available; /* bitmap of available channels */
4810 + u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
4811 +};
4812 +
4813 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
4814 + u32 chans_available)
4815 +{
4816 + dmaman->dma_base = dma_base;
4817 + dmaman->chan_available = chans_available;
4818 + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
4819 + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
4820 + dmaman->has_feature[BCM_DMA_FEATURE_NORMAL_ORD] = 0xfe; /* chans 1 to 7 */
4821 + dmaman->has_feature[BCM_DMA_FEATURE_LITE_ORD] = 0x7f00; /* chans 8 to 14 */
4822 +}
4823 +
4824 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
4825 + unsigned preferred_feature_set)
4826 +{
4827 + u32 chans;
4828 + int feature;
4829 +
4830 + chans = dmaman->chan_available;
4831 + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
4832 + /* select the subset of available channels with the desired
4833 + feature so long as some of the candidate channels have that
4834 + feature */
4835 + if ((preferred_feature_set & (1 << feature)) &&
4836 + (chans & dmaman->has_feature[feature]))
4837 + chans &= dmaman->has_feature[feature];
4838 +
4839 + if (chans) {
4840 + int chan = 0;
4841 + /* return the ordinal of the first channel in the bitmap */
4842 + while (chans != 0 && (chans & 1) == 0) {
4843 + chans >>= 1;
4844 + chan++;
4845 + }
4846 + /* claim the channel */
4847 + dmaman->chan_available &= ~(1 << chan);
4848 + return chan;
4849 + } else
4850 + return -ENOMEM;
4851 +}
4852 +
4853 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
4854 +{
4855 + if (chan < 0)
4856 + return -EINVAL;
4857 + else if ((1 << chan) & dmaman->chan_available)
4858 + return -EIDRM;
4859 + else {
4860 + dmaman->chan_available |= (1 << chan);
4861 + return 0;
4862 + }
4863 +}
4864 +
4865 +/*****************************************************************************\
4866 + * *
4867 + * DMA IRQs *
4868 + * *
4869 +\*****************************************************************************/
4870 +
4871 +static unsigned char bcm_dma_irqs[] = {
4872 + IRQ_DMA0,
4873 + IRQ_DMA1,
4874 + IRQ_DMA2,
4875 + IRQ_DMA3,
4876 + IRQ_DMA4,
4877 + IRQ_DMA5,
4878 + IRQ_DMA6,
4879 + IRQ_DMA7,
4880 + IRQ_DMA8,
4881 + IRQ_DMA9,
4882 + IRQ_DMA10,
4883 + IRQ_DMA11,
4884 + IRQ_DMA12
4885 +};
4886 +
4887 +
4888 +/***************************************************************************** \
4889 + * *
4890 + * DMA Manager Monitor *
4891 + * *
4892 +\*****************************************************************************/
4893 +
4894 +static struct device *dmaman_dev; /* we assume there's only one! */
4895 +
4896 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
4897 + void __iomem **out_dma_base, int *out_dma_irq)
4898 +{
4899 + if (!dmaman_dev)
4900 + return -ENODEV;
4901 + else {
4902 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
4903 + int rc;
4904 +
4905 + device_lock(dmaman_dev);
4906 + rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
4907 + if (rc >= 0) {
4908 + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
4909 + rc);
4910 + *out_dma_irq = bcm_dma_irqs[rc];
4911 + }
4912 + device_unlock(dmaman_dev);
4913 +
4914 + return rc;
4915 + }
4916 +}
4917 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
4918 +
4919 +extern int bcm_dma_chan_free(int channel)
4920 +{
4921 + if (dmaman_dev) {
4922 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
4923 + int rc;
4924 +
4925 + device_lock(dmaman_dev);
4926 + rc = vc_dmaman_chan_free(dmaman, channel);
4927 + device_unlock(dmaman_dev);
4928 +
4929 + return rc;
4930 + } else
4931 + return -ENODEV;
4932 +}
4933 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
4934 +
4935 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
4936 +{
4937 + int rc = dmaman_dev ? -EINVAL : 0;
4938 + dmaman_dev = dev;
4939 + return rc;
4940 +}
4941 +
4942 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
4943 +{
4944 + dmaman_dev = NULL;
4945 +}
4946 +
4947 +/*****************************************************************************\
4948 + * *
4949 + * DMA Device *
4950 + * *
4951 +\*****************************************************************************/
4952 +
4953 +static int dmachans = -1; /* module parameter */
4954 +
4955 +static int bcm_dmaman_probe(struct platform_device *pdev)
4956 +{
4957 + int ret = 0;
4958 + struct vc_dmaman *dmaman;
4959 + struct resource *dma_res = NULL;
4960 + void __iomem *dma_base = NULL;
4961 + int have_dma_region = 0;
4962 +
4963 + dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
4964 + if (NULL == dmaman) {
4965 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
4966 + "DMA management memory\n");
4967 + ret = -ENOMEM;
4968 + } else {
4969 +
4970 + dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4971 + if (dma_res == NULL) {
4972 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
4973 + "resource\n");
4974 + ret = -ENODEV;
4975 + } else if (!request_mem_region(dma_res->start,
4976 + resource_size(dma_res),
4977 + DRIVER_NAME)) {
4978 + dev_err(&pdev->dev, "cannot obtain DMA region\n");
4979 + ret = -EBUSY;
4980 + } else {
4981 + have_dma_region = 1;
4982 + dma_base = ioremap(dma_res->start,
4983 + resource_size(dma_res));
4984 + if (!dma_base) {
4985 + dev_err(&pdev->dev, "cannot map DMA region\n");
4986 + ret = -ENOMEM;
4987 + } else {
4988 + /* use module parameter if one was provided */
4989 + if (dmachans > 0)
4990 + vc_dmaman_init(dmaman, dma_base,
4991 + dmachans);
4992 + else
4993 + vc_dmaman_init(dmaman, dma_base,
4994 + DEFAULT_DMACHAN_BITMAP);
4995 +
4996 + platform_set_drvdata(pdev, dmaman);
4997 + dev_dmaman_register(DRIVER_NAME, &pdev->dev);
4998 +
4999 + printk(KERN_INFO DRIVER_NAME ": DMA manager "
5000 + "at %p\n", dma_base);
5001 + }
5002 + }
5003 + }
5004 + if (ret != 0) {
5005 + if (dma_base)
5006 + iounmap(dma_base);
5007 + if (dma_res && have_dma_region)
5008 + release_mem_region(dma_res->start,
5009 + resource_size(dma_res));
5010 + if (dmaman)
5011 + kfree(dmaman);
5012 + }
5013 + return ret;
5014 +}
5015 +
5016 +static int bcm_dmaman_remove(struct platform_device *pdev)
5017 +{
5018 + struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
5019 +
5020 + platform_set_drvdata(pdev, NULL);
5021 + dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
5022 + kfree(dmaman);
5023 +
5024 + return 0;
5025 +}
5026 +
5027 +static struct platform_driver bcm_dmaman_driver = {
5028 + .probe = bcm_dmaman_probe,
5029 + .remove = bcm_dmaman_remove,
5030 +
5031 + .driver = {
5032 + .name = DRIVER_NAME,
5033 + .owner = THIS_MODULE,
5034 + },
5035 +};
5036 +
5037 +/*****************************************************************************\
5038 + * *
5039 + * Driver init/exit *
5040 + * *
5041 +\*****************************************************************************/
5042 +
5043 +static int __init bcm_dmaman_drv_init(void)
5044 +{
5045 + int ret;
5046 +
5047 + ret = platform_driver_register(&bcm_dmaman_driver);
5048 + if (ret != 0) {
5049 + printk(KERN_ERR DRIVER_NAME ": failed to register "
5050 + "on platform\n");
5051 + }
5052 +
5053 + return ret;
5054 +}
5055 +
5056 +static void __exit bcm_dmaman_drv_exit(void)
5057 +{
5058 + platform_driver_unregister(&bcm_dmaman_driver);
5059 +}
5060 +
5061 +module_init(bcm_dmaman_drv_init);
5062 +module_exit(bcm_dmaman_drv_exit);
5063 +
5064 +module_param(dmachans, int, 0644);
5065 +
5066 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
5067 +MODULE_DESCRIPTION("DMA channel manager driver");
5068 +MODULE_LICENSE("GPL");
5069 +
5070 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
5071 diff --git a/arch/arm/mach-bcm2709/dmaer.c b/arch/arm/mach-bcm2709/dmaer.c
5072 new file mode 100755
5073 index 0000000..5b0f0ff
5074 --- /dev/null
5075 +++ b/arch/arm/mach-bcm2709/dmaer.c
5076 @@ -0,0 +1,886 @@
5077 +#include <linux/init.h>
5078 +#include <linux/sched.h>
5079 +#include <linux/module.h>
5080 +#include <linux/types.h>
5081 +#include <linux/kdev_t.h>
5082 +#include <linux/fs.h>
5083 +#include <linux/cdev.h>
5084 +#include <linux/mm.h>
5085 +#include <linux/slab.h>
5086 +#include <linux/pagemap.h>
5087 +#include <linux/device.h>
5088 +#include <linux/jiffies.h>
5089 +#include <linux/timex.h>
5090 +#include <linux/dma-mapping.h>
5091 +
5092 +#include <asm/uaccess.h>
5093 +#include <asm/atomic.h>
5094 +#include <asm/cacheflush.h>
5095 +#include <asm/io.h>
5096 +
5097 +#include <mach/dma.h>
5098 +#include <mach/vc_support.h>
5099 +
5100 +#ifdef ECLIPSE_IGNORE
5101 +
5102 +#define __user
5103 +#define __init
5104 +#define __exit
5105 +#define __iomem
5106 +#define KERN_DEBUG
5107 +#define KERN_ERR
5108 +#define KERN_WARNING
5109 +#define KERN_INFO
5110 +#define _IOWR(a, b, c) b
5111 +#define _IOW(a, b, c) b
5112 +#define _IO(a, b) b
5113 +
5114 +#endif
5115 +
5116 +//#define inline
5117 +
5118 +#define PRINTK(args...) printk(args)
5119 +//#define PRINTK_VERBOSE(args...) printk(args)
5120 +//#define PRINTK(args...)
5121 +#define PRINTK_VERBOSE(args...)
5122 +
5123 +/***** TYPES ****/
5124 +#define PAGES_PER_LIST 500
5125 +struct PageList
5126 +{
5127 + struct page *m_pPages[PAGES_PER_LIST];
5128 + unsigned int m_used;
5129 + struct PageList *m_pNext;
5130 +};
5131 +
5132 +struct VmaPageList
5133 +{
5134 + //each vma has a linked list of pages associated with it
5135 + struct PageList *m_pPageHead;
5136 + struct PageList *m_pPageTail;
5137 + unsigned int m_refCount;
5138 +};
5139 +
5140 +struct DmaControlBlock
5141 +{
5142 + unsigned int m_transferInfo;
5143 + void __user *m_pSourceAddr;
5144 + void __user *m_pDestAddr;
5145 + unsigned int m_xferLen;
5146 + unsigned int m_tdStride;
5147 + struct DmaControlBlock *m_pNext;
5148 + unsigned int m_blank1, m_blank2;
5149 +};
5150 +
5151 +/***** DEFINES ******/
5152 +//magic number defining the module
5153 +#define DMA_MAGIC 0xdd
5154 +
5155 +//do user virtual to physical translation of the CB chain
5156 +#define DMA_PREPARE _IOWR(DMA_MAGIC, 0, struct DmaControlBlock *)
5157 +
5158 +//kick the pre-prepared CB chain
5159 +#define DMA_KICK _IOW(DMA_MAGIC, 1, struct DmaControlBlock *)
5160 +
5161 +//prepare it, kick it, wait for it
5162 +#define DMA_PREPARE_KICK_WAIT _IOWR(DMA_MAGIC, 2, struct DmaControlBlock *)
5163 +
5164 +//prepare it, kick it, don't wait for it
5165 +#define DMA_PREPARE_KICK _IOWR(DMA_MAGIC, 3, struct DmaControlBlock *)
5166 +
5167 +//not currently implemented
5168 +#define DMA_WAIT_ONE _IO(DMA_MAGIC, 4, struct DmaControlBlock *)
5169 +
5170 +//wait on all kicked CB chains
5171 +#define DMA_WAIT_ALL _IO(DMA_MAGIC, 5)
5172 +
5173 +//in order to discover the largest AXI burst that should be programmed into the transfer params
5174 +#define DMA_MAX_BURST _IO(DMA_MAGIC, 6)
5175 +
5176 +//set the address range through which the user address is assumed to already by a physical address
5177 +#define DMA_SET_MIN_PHYS _IOW(DMA_MAGIC, 7, unsigned long)
5178 +#define DMA_SET_MAX_PHYS _IOW(DMA_MAGIC, 8, unsigned long)
5179 +#define DMA_SET_PHYS_OFFSET _IOW(DMA_MAGIC, 9, unsigned long)
5180 +
5181 +//used to define the size for the CMA-based allocation *in pages*, can only be done once once the file is opened
5182 +#define DMA_CMA_SET_SIZE _IOW(DMA_MAGIC, 10, unsigned long)
5183 +
5184 +//used to get the version of the module, to test for a capability
5185 +#define DMA_GET_VERSION _IO(DMA_MAGIC, 99)
5186 +
5187 +#define VERSION_NUMBER 1
5188 +
5189 +#define VIRT_TO_BUS_CACHE_SIZE 8
5190 +
5191 +/***** FILE OPS *****/
5192 +static int Open(struct inode *pInode, struct file *pFile);
5193 +static int Release(struct inode *pInode, struct file *pFile);
5194 +static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg);
5195 +static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp);
5196 +static int Mmap(struct file *pFile, struct vm_area_struct *pVma);
5197 +
5198 +/***** VMA OPS ****/
5199 +static void VmaOpen4k(struct vm_area_struct *pVma);
5200 +static void VmaClose4k(struct vm_area_struct *pVma);
5201 +static int VmaFault4k(struct vm_area_struct *pVma, struct vm_fault *pVmf);
5202 +
5203 +/**** DMA PROTOTYPES */
5204 +static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError);
5205 +static int DmaKick(struct DmaControlBlock __user *pUserCB);
5206 +static void DmaWaitAll(void);
5207 +
5208 +/**** GENERIC ****/
5209 +static int __init dmaer_init(void);
5210 +static void __exit dmaer_exit(void);
5211 +
5212 +/*** OPS ***/
5213 +static struct vm_operations_struct g_vmOps4k = {
5214 + .open = VmaOpen4k,
5215 + .close = VmaClose4k,
5216 + .fault = VmaFault4k,
5217 +};
5218 +
5219 +static struct file_operations g_fOps = {
5220 + .owner = THIS_MODULE,
5221 + .llseek = 0,
5222 + .read = Read,
5223 + .write = 0,
5224 + .unlocked_ioctl = Ioctl,
5225 + .open = Open,
5226 + .release = Release,
5227 + .mmap = Mmap,
5228 +};
5229 +
5230 +/***** GLOBALS ******/
5231 +static dev_t g_majorMinor;
5232 +
5233 +//tracking usage of the two files
5234 +static atomic_t g_oneLock4k = ATOMIC_INIT(1);
5235 +
5236 +//device operations
5237 +static struct cdev g_cDev;
5238 +static int g_trackedPages = 0;
5239 +
5240 +//dma control
5241 +static unsigned int *g_pDmaChanBase;
5242 +static int g_dmaIrq;
5243 +static int g_dmaChan;
5244 +
5245 +//cma allocation
5246 +static int g_cmaHandle;
5247 +
5248 +//user virtual to bus address translation acceleration
5249 +static unsigned long g_virtAddr[VIRT_TO_BUS_CACHE_SIZE];
5250 +static unsigned long g_busAddr[VIRT_TO_BUS_CACHE_SIZE];
5251 +static unsigned long g_cbVirtAddr;
5252 +static unsigned long g_cbBusAddr;
5253 +static int g_cacheInsertAt;
5254 +static int g_cacheHit, g_cacheMiss;
5255 +
5256 +//off by default
5257 +static void __user *g_pMinPhys;
5258 +static void __user *g_pMaxPhys;
5259 +static unsigned long g_physOffset;
5260 +
5261 +/****** CACHE OPERATIONS ********/
5262 +static inline void FlushAddrCache(void)
5263 +{
5264 + int count = 0;
5265 + for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++)
5266 + g_virtAddr[count] = 0xffffffff; //never going to match as we always chop the bottom bits anyway
5267 +
5268 + g_cbVirtAddr = 0xffffffff;
5269 +
5270 + g_cacheInsertAt = 0;
5271 +}
5272 +
5273 +//translate from a user virtual address to a bus address by mapping the page
5274 +//NB this won't lock a page in memory, so to avoid potential paging issues using kernel logical addresses
5275 +static inline void __iomem *UserVirtualToBus(void __user *pUser)
5276 +{
5277 + int mapped;
5278 + struct page *pPage;
5279 + void *phys;
5280 +
5281 + //map it (requiring that the pointer points to something that does not hang off the page boundary)
5282 + mapped = get_user_pages(current, current->mm,
5283 + (unsigned long)pUser, 1,
5284 + 1, 0,
5285 + &pPage,
5286 + 0);
5287 +
5288 + if (mapped <= 0) //error
5289 + return 0;
5290 +
5291 + PRINTK_VERBOSE(KERN_DEBUG "user virtual %p arm phys %p bus %p\n",
5292 + pUser, page_address(pPage), (void __iomem *)__virt_to_bus(page_address(pPage)));
5293 +
5294 + //get the arm physical address
5295 + phys = page_address(pPage) + offset_in_page(pUser);
5296 + page_cache_release(pPage);
5297 +
5298 + //and now the bus address
5299 + return (void __iomem *)__virt_to_bus(phys);
5300 +}
5301 +
5302 +static inline void __iomem *UserVirtualToBusViaCbCache(void __user *pUser)
5303 +{
5304 + unsigned long virtual_page = (unsigned long)pUser & ~4095;
5305 + unsigned long page_offset = (unsigned long)pUser & 4095;
5306 + unsigned long bus_addr;
5307 +
5308 + if (g_cbVirtAddr == virtual_page)
5309 + {
5310 + bus_addr = g_cbBusAddr + page_offset;
5311 + g_cacheHit++;
5312 + return (void __iomem *)bus_addr;
5313 + }
5314 + else
5315 + {
5316 + bus_addr = (unsigned long)UserVirtualToBus(pUser);
5317 +
5318 + if (!bus_addr)
5319 + return 0;
5320 +
5321 + g_cbVirtAddr = virtual_page;
5322 + g_cbBusAddr = bus_addr & ~4095;
5323 + g_cacheMiss++;
5324 +
5325 + return (void __iomem *)bus_addr;
5326 + }
5327 +}
5328 +
5329 +//do the same as above, by query our virt->bus cache
5330 +static inline void __iomem *UserVirtualToBusViaCache(void __user *pUser)
5331 +{
5332 + int count;
5333 + //get the page and its offset
5334 + unsigned long virtual_page = (unsigned long)pUser & ~4095;
5335 + unsigned long page_offset = (unsigned long)pUser & 4095;
5336 + unsigned long bus_addr;
5337 +
5338 + if (pUser >= g_pMinPhys && pUser < g_pMaxPhys)
5339 + {
5340 + PRINTK_VERBOSE(KERN_DEBUG "user->phys passthrough on %p\n", pUser);
5341 + return (void __iomem *)((unsigned long)pUser + g_physOffset);
5342 + }
5343 +
5344 + //check the cache for our entry
5345 + for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++)
5346 + if (g_virtAddr[count] == virtual_page)
5347 + {
5348 + bus_addr = g_busAddr[count] + page_offset;
5349 + g_cacheHit++;
5350 + return (void __iomem *)bus_addr;
5351 + }
5352 +
5353 + //not found, look up manually and then insert its page address
5354 + bus_addr = (unsigned long)UserVirtualToBus(pUser);
5355 +
5356 + if (!bus_addr)
5357 + return 0;
5358 +
5359 + g_virtAddr[g_cacheInsertAt] = virtual_page;
5360 + g_busAddr[g_cacheInsertAt] = bus_addr & ~4095;
5361 +
5362 + //round robin
5363 + g_cacheInsertAt++;
5364 + if (g_cacheInsertAt == VIRT_TO_BUS_CACHE_SIZE)
5365 + g_cacheInsertAt = 0;
5366 +
5367 + g_cacheMiss++;
5368 +
5369 + return (void __iomem *)bus_addr;
5370 +}
5371 +
5372 +/***** FILE OPERATIONS ****/
5373 +static int Open(struct inode *pInode, struct file *pFile)
5374 +{
5375 + PRINTK(KERN_DEBUG "file opening: %d/%d\n", imajor(pInode), iminor(pInode));
5376 +
5377 + //check which device we are
5378 + if (iminor(pInode) == 0) //4k
5379 + {
5380 + //only one at a time
5381 + if (!atomic_dec_and_test(&g_oneLock4k))
5382 + {
5383 + atomic_inc(&g_oneLock4k);
5384 + return -EBUSY;
5385 + }
5386 + }
5387 + else
5388 + return -EINVAL;
5389 +
5390 + //todo there will be trouble if two different processes open the files
5391 +
5392 + //reset after any file is opened
5393 + g_pMinPhys = (void __user *)-1;
5394 + g_pMaxPhys = (void __user *)0;
5395 + g_physOffset = 0;
5396 + g_cmaHandle = 0;
5397 +
5398 + return 0;
5399 +}
5400 +
5401 +static int Release(struct inode *pInode, struct file *pFile)
5402 +{
5403 + PRINTK(KERN_DEBUG "file closing, %d pages tracked\n", g_trackedPages);
5404 + if (g_trackedPages)
5405 + PRINTK(KERN_ERR "we\'re leaking memory!\n");
5406 +
5407 + //wait for any dmas to finish
5408 + DmaWaitAll();
5409 +
5410 + //free this memory on the application closing the file or it crashing (implicitly closing the file)
5411 + if (g_cmaHandle)
5412 + {
5413 + PRINTK(KERN_DEBUG "unlocking vc memory\n");
5414 + if (UnlockVcMemory(g_cmaHandle))
5415 + PRINTK(KERN_ERR "uh-oh, unable to unlock vc memory!\n");
5416 + PRINTK(KERN_DEBUG "releasing vc memory\n");
5417 + if (ReleaseVcMemory(g_cmaHandle))
5418 + PRINTK(KERN_ERR "uh-oh, unable to release vc memory!\n");
5419 + }
5420 +
5421 + if (iminor(pInode) == 0)
5422 + atomic_inc(&g_oneLock4k);
5423 + else
5424 + return -EINVAL;
5425 +
5426 + return 0;
5427 +}
5428 +
5429 +static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError)
5430 +{
5431 + struct DmaControlBlock kernCB;
5432 + struct DmaControlBlock __user *pUNext;
5433 + void __iomem *pSourceBus, __iomem *pDestBus;
5434 +
5435 + //get the control block into kernel memory so we can work on it
5436 + if (copy_from_user(&kernCB, pUserCB, sizeof(struct DmaControlBlock)) != 0)
5437 + {
5438 + PRINTK(KERN_ERR "copy_from_user failed for user cb %p\n", pUserCB);
5439 + *pError = 1;
5440 + return 0;
5441 + }
5442 +
5443 + if (kernCB.m_pSourceAddr == 0 || kernCB.m_pDestAddr == 0)
5444 + {
5445 + PRINTK(KERN_ERR "faulty source (%p) dest (%p) addresses for user cb %p\n",
5446 + kernCB.m_pSourceAddr, kernCB.m_pDestAddr, pUserCB);
5447 + *pError = 1;
5448 + return 0;
5449 + }
5450 +
5451 + pSourceBus = UserVirtualToBusViaCache(kernCB.m_pSourceAddr);
5452 + pDestBus = UserVirtualToBusViaCache(kernCB.m_pDestAddr);
5453 +
5454 + if (!pSourceBus || !pDestBus)
5455 + {
5456 + PRINTK(KERN_ERR "virtual to bus translation failure for source/dest %p/%p->%p/%p\n",
5457 + kernCB.m_pSourceAddr, kernCB.m_pDestAddr,
5458 + pSourceBus, pDestBus);
5459 + *pError = 1;
5460 + return 0;
5461 + }
5462 +
5463 + //update the user structure with the new bus addresses
5464 + kernCB.m_pSourceAddr = pSourceBus;
5465 + kernCB.m_pDestAddr = pDestBus;
5466 +
5467 + PRINTK_VERBOSE(KERN_DEBUG "final source %p dest %p\n", kernCB.m_pSourceAddr, kernCB.m_pDestAddr);
5468 +
5469 + //sort out the bus address for the next block
5470 + pUNext = kernCB.m_pNext;
5471 +
5472 + if (kernCB.m_pNext)
5473 + {
5474 + void __iomem *pNextBus;
5475 + pNextBus = UserVirtualToBusViaCbCache(kernCB.m_pNext);
5476 +
5477 + if (!pNextBus)
5478 + {
5479 + PRINTK(KERN_ERR "virtual to bus translation failure for m_pNext\n");
5480 + *pError = 1;
5481 + return 0;
5482 + }
5483 +
5484 + //update the pointer with the bus address
5485 + kernCB.m_pNext = pNextBus;
5486 + }
5487 +
5488 + //write it back to user space
5489 + if (copy_to_user(pUserCB, &kernCB, sizeof(struct DmaControlBlock)) != 0)
5490 + {
5491 + PRINTK(KERN_ERR "copy_to_user failed for cb %p\n", pUserCB);
5492 + *pError = 1;
5493 + return 0;
5494 + }
5495 +
5496 + __cpuc_flush_dcache_area(pUserCB, 32);
5497 +
5498 + *pError = 0;
5499 + return pUNext;
5500 +}
5501 +
5502 +static int DmaKick(struct DmaControlBlock __user *pUserCB)
5503 +{
5504 + void __iomem *pBusCB;
5505 +
5506 + pBusCB = UserVirtualToBusViaCbCache(pUserCB);
5507 + if (!pBusCB)
5508 + {
5509 + PRINTK(KERN_ERR "virtual to bus translation failure for cb\n");
5510 + return 1;
5511 + }
5512 +
5513 + //flush_cache_all();
5514 +
5515 + bcm_dma_start(g_pDmaChanBase, (dma_addr_t)pBusCB);
5516 +
5517 + return 0;
5518 +}
5519 +
5520 +static void DmaWaitAll(void)
5521 +{
5522 + int counter = 0;
5523 + volatile int inner_count;
5524 + volatile unsigned int cs;
5525 + unsigned long time_before, time_after;
5526 +
5527 + time_before = jiffies;
5528 + //bcm_dma_wait_idle(g_pDmaChanBase);
5529 + dsb();
5530 +
5531 + cs = readl(g_pDmaChanBase);
5532 +
5533 + while ((cs & 1) == 1)
5534 + {
5535 + cs = readl(g_pDmaChanBase);
5536 + counter++;
5537 +
5538 + for (inner_count = 0; inner_count < 32; inner_count++);
5539 +
5540 + asm volatile ("MCR p15,0,r0,c7,c0,4 \n");
5541 + //cpu_do_idle();
5542 + if (counter >= 1000000)
5543 + {
5544 + PRINTK(KERN_WARNING "DMA failed to finish in a timely fashion\n");
5545 + break;
5546 + }
5547 + }
5548 + time_after = jiffies;
5549 + PRINTK_VERBOSE(KERN_DEBUG "done, counter %d, cs %08x", counter, cs);
5550 + PRINTK_VERBOSE(KERN_DEBUG "took %ld jiffies, %d HZ\n", time_after - time_before, HZ);
5551 +}
5552 +
5553 +static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg)
5554 +{
5555 + int error = 0;
5556 + PRINTK_VERBOSE(KERN_DEBUG "ioctl cmd %x arg %lx\n", cmd, arg);
5557 +
5558 + switch (cmd)
5559 + {
5560 + case DMA_PREPARE:
5561 + case DMA_PREPARE_KICK:
5562 + case DMA_PREPARE_KICK_WAIT:
5563 + {
5564 + struct DmaControlBlock __user *pUCB = (struct DmaControlBlock *)arg;
5565 + int steps = 0;
5566 + unsigned long start_time = jiffies;
5567 + (void)start_time;
5568 +
5569 + //flush our address cache
5570 + FlushAddrCache();
5571 +
5572 + PRINTK_VERBOSE(KERN_DEBUG "dma prepare\n");
5573 +
5574 + //do virtual to bus translation for each entry
5575 + do
5576 + {
5577 + pUCB = DmaPrepare(pUCB, &error);
5578 + } while (error == 0 && ++steps && pUCB);
5579 + PRINTK_VERBOSE(KERN_DEBUG "prepare done in %d steps, %ld\n", steps, jiffies - start_time);
5580 +
5581 + //carry straight on if we want to kick too
5582 + if (cmd == DMA_PREPARE || error)
5583 + {
5584 + PRINTK_VERBOSE(KERN_DEBUG "falling out\n");
5585 + return error ? -EINVAL : 0;
5586 + }
5587 + }
5588 + case DMA_KICK:
5589 + PRINTK_VERBOSE(KERN_DEBUG "dma begin\n");
5590 +
5591 + if (cmd == DMA_KICK)
5592 + FlushAddrCache();
5593 +
5594 + DmaKick((struct DmaControlBlock __user *)arg);
5595 +
5596 + if (cmd != DMA_PREPARE_KICK_WAIT)
5597 + break;
5598 +/* case DMA_WAIT_ONE:
5599 + //PRINTK(KERN_DEBUG "dma wait one\n");
5600 + break;*/
5601 + case DMA_WAIT_ALL:
5602 + //PRINTK(KERN_DEBUG "dma wait all\n");
5603 + DmaWaitAll();
5604 + break;
5605 + case DMA_MAX_BURST:
5606 + if (g_dmaChan == 0)
5607 + return 10;
5608 + else
5609 + return 5;
5610 + case DMA_SET_MIN_PHYS:
5611 + g_pMinPhys = (void __user *)arg;
5612 + PRINTK(KERN_DEBUG "min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys);
5613 + break;
5614 + case DMA_SET_MAX_PHYS:
5615 + g_pMaxPhys = (void __user *)arg;
5616 + PRINTK(KERN_DEBUG "min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys);
5617 + break;
5618 + case DMA_SET_PHYS_OFFSET:
5619 + g_physOffset = arg;
5620 + PRINTK(KERN_DEBUG "user/phys bypass offset set to %ld\n", g_physOffset);
5621 + break;
5622 + case DMA_CMA_SET_SIZE:
5623 + {
5624 + unsigned int pBusAddr;
5625 +
5626 + if (g_cmaHandle)
5627 + {
5628 + PRINTK(KERN_ERR "memory has already been allocated (handle %d)\n", g_cmaHandle);
5629 + return -EINVAL;
5630 + }
5631 +
5632 + PRINTK(KERN_INFO "allocating %ld bytes of VC memory\n", arg * 4096);
5633 +
5634 + //get the memory
5635 + if (AllocateVcMemory(&g_cmaHandle, arg * 4096, 4096, MEM_FLAG_L1_NONALLOCATING | MEM_FLAG_NO_INIT | MEM_FLAG_HINT_PERMALOCK))
5636 + {
5637 + PRINTK(KERN_ERR "failed to allocate %ld bytes of VC memory\n", arg * 4096);
5638 + g_cmaHandle = 0;
5639 + return -EINVAL;
5640 + }
5641 +
5642 + //get an address for it
5643 + PRINTK(KERN_INFO "trying to map VC memory\n");
5644 +
5645 + if (LockVcMemory(&pBusAddr, g_cmaHandle))
5646 + {
5647 + PRINTK(KERN_ERR "failed to map CMA handle %d, releasing memory\n", g_cmaHandle);
5648 + ReleaseVcMemory(g_cmaHandle);
5649 + g_cmaHandle = 0;
5650 + }
5651 +
5652 + PRINTK(KERN_INFO "bus address for CMA memory is %x\n", pBusAddr);
5653 + return pBusAddr;
5654 + }
5655 + case DMA_GET_VERSION:
5656 + PRINTK(KERN_DEBUG "returning version number, %d\n", VERSION_NUMBER);
5657 + return VERSION_NUMBER;
5658 + default:
5659 + PRINTK(KERN_DEBUG "unknown ioctl: %d\n", cmd);
5660 + return -EINVAL;
5661 + }
5662 +
5663 + return 0;
5664 +}
5665 +
5666 +static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp)
5667 +{
5668 + return -EIO;
5669 +}
5670 +
5671 +static int Mmap(struct file *pFile, struct vm_area_struct *pVma)
5672 +{
5673 + struct PageList *pPages;
5674 + struct VmaPageList *pVmaList;
5675 +
5676 + PRINTK_VERBOSE(KERN_DEBUG "MMAP vma %p, length %ld (%s %d)\n",
5677 + pVma, pVma->vm_end - pVma->vm_start,
5678 + current->comm, current->pid);
5679 + PRINTK_VERBOSE(KERN_DEBUG "MMAP %p %d (tracked %d)\n", pVma, current->pid, g_trackedPages);
5680 +
5681 + //make a new page list
5682 + pPages = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL);
5683 + if (!pPages)
5684 + {
5685 + PRINTK(KERN_ERR "couldn\'t allocate a new page list (%s %d)\n",
5686 + current->comm, current->pid);
5687 + return -ENOMEM;
5688 + }
5689 +
5690 + //clear the page list
5691 + pPages->m_used = 0;
5692 + pPages->m_pNext = 0;
5693 +
5694 + //insert our vma and new page list somewhere
5695 + if (!pVma->vm_private_data)
5696 + {
5697 + struct VmaPageList *pList;
5698 +
5699 + PRINTK_VERBOSE(KERN_DEBUG "new vma list, making new one (%s %d)\n",
5700 + current->comm, current->pid);
5701 +
5702 + //make a new vma list
5703 + pList = (struct VmaPageList *)kmalloc(sizeof(struct VmaPageList), GFP_KERNEL);
5704 + if (!pList)
5705 + {
5706 + PRINTK(KERN_ERR "couldn\'t allocate vma page list (%s %d)\n",
5707 + current->comm, current->pid);
5708 + kfree(pPages);
5709 + return -ENOMEM;
5710 + }
5711 +
5712 + //clear this list
5713 + pVma->vm_private_data = (void *)pList;
5714 + pList->m_refCount = 0;
5715 + }
5716 +
5717 + pVmaList = (struct VmaPageList *)pVma->vm_private_data;
5718 +
5719 + //add it to the vma list
5720 + pVmaList->m_pPageHead = pPages;
5721 + pVmaList->m_pPageTail = pPages;
5722 +
5723 + pVma->vm_ops = &g_vmOps4k;
5724 + pVma->vm_flags |= VM_IO;
5725 +
5726 + VmaOpen4k(pVma);
5727 +
5728 + return 0;
5729 +}
5730 +
5731 +/****** VMA OPERATIONS ******/
5732 +
5733 +static void VmaOpen4k(struct vm_area_struct *pVma)
5734 +{
5735 + struct VmaPageList *pVmaList;
5736 +
5737 + PRINTK_VERBOSE(KERN_DEBUG "vma open %p private %p (%s %d), %d live pages\n", pVma, pVma->vm_private_data, current->comm, current->pid, g_trackedPages);
5738 + PRINTK_VERBOSE(KERN_DEBUG "OPEN %p %d %ld pages (tracked pages %d)\n",
5739 + pVma, current->pid, (pVma->vm_end - pVma->vm_start) >> 12,
5740 + g_trackedPages);
5741 +
5742 + pVmaList = (struct VmaPageList *)pVma->vm_private_data;
5743 +
5744 + if (pVmaList)
5745 + {
5746 + pVmaList->m_refCount++;
5747 + PRINTK_VERBOSE(KERN_DEBUG "ref count is now %d\n", pVmaList->m_refCount);
5748 + }
5749 + else
5750 + {
5751 + PRINTK_VERBOSE(KERN_DEBUG "err, open but no vma page list\n");
5752 + }
5753 +}
5754 +
5755 +static void VmaClose4k(struct vm_area_struct *pVma)
5756 +{
5757 + struct VmaPageList *pVmaList;
5758 + int freed = 0;
5759 +
5760 + PRINTK_VERBOSE(KERN_DEBUG "vma close %p private %p (%s %d)\n", pVma, pVma->vm_private_data, current->comm, current->pid);
5761 +
5762 + //wait for any dmas to finish
5763 + DmaWaitAll();
5764 +
5765 + //find our vma in the list
5766 + pVmaList = (struct VmaPageList *)pVma->vm_private_data;
5767 +
5768 + //may be a fork
5769 + if (pVmaList)
5770 + {
5771 + struct PageList *pPages;
5772 +
5773 + pVmaList->m_refCount--;
5774 +
5775 + if (pVmaList->m_refCount == 0)
5776 + {
5777 + PRINTK_VERBOSE(KERN_DEBUG "found vma, freeing pages (%s %d)\n",
5778 + current->comm, current->pid);
5779 +
5780 + pPages = pVmaList->m_pPageHead;
5781 +
5782 + if (!pPages)
5783 + {
5784 + PRINTK(KERN_ERR "no page list (%s %d)!\n",
5785 + current->comm, current->pid);
5786 + return;
5787 + }
5788 +
5789 + while (pPages)
5790 + {
5791 + struct PageList *next;
5792 + int count;
5793 +
5794 + PRINTK_VERBOSE(KERN_DEBUG "page list (%s %d)\n",
5795 + current->comm, current->pid);
5796 +
5797 + next = pPages->m_pNext;
5798 + for (count = 0; count < pPages->m_used; count++)
5799 + {
5800 + PRINTK_VERBOSE(KERN_DEBUG "freeing page %p (%s %d)\n",
5801 + pPages->m_pPages[count],
5802 + current->comm, current->pid);
5803 + __free_pages(pPages->m_pPages[count], 0);
5804 + g_trackedPages--;
5805 + freed++;
5806 + }
5807 +
5808 + PRINTK_VERBOSE(KERN_DEBUG "freeing page list (%s %d)\n",
5809 + current->comm, current->pid);
5810 + kfree(pPages);
5811 + pPages = next;
5812 + }
5813 +
5814 + //remove our vma from the list
5815 + kfree(pVmaList);
5816 + pVma->vm_private_data = 0;
5817 + }
5818 + else
5819 + {
5820 + PRINTK_VERBOSE(KERN_DEBUG "ref count is %d, not closing\n", pVmaList->m_refCount);
5821 + }
5822 + }
5823 + else
5824 + {
5825 + PRINTK_VERBOSE(KERN_ERR "uh-oh, vma %p not found (%s %d)!\n", pVma, current->comm, current->pid);
5826 + PRINTK_VERBOSE(KERN_ERR "CLOSE ERR\n");
5827 + }
5828 +
5829 + PRINTK_VERBOSE(KERN_DEBUG "CLOSE %p %d %d pages (tracked pages %d)",
5830 + pVma, current->pid, freed, g_trackedPages);
5831 +
5832 + PRINTK_VERBOSE(KERN_DEBUG "%d pages open\n", g_trackedPages);
5833 +}
5834 +
5835 +static int VmaFault4k(struct vm_area_struct *pVma, struct vm_fault *pVmf)
5836 +{
5837 + PRINTK_VERBOSE(KERN_DEBUG "vma fault for vma %p private %p at offset %ld (%s %d)\n", pVma, pVma->vm_private_data, pVmf->pgoff,
5838 + current->comm, current->pid);
5839 + PRINTK_VERBOSE(KERN_DEBUG "FAULT\n");
5840 + pVmf->page = alloc_page(GFP_KERNEL);
5841 +
5842 + if (pVmf->page)
5843 + {
5844 + PRINTK_VERBOSE(KERN_DEBUG "alloc page virtual %p\n", page_address(pVmf->page));
5845 + }
5846 +
5847 + if (!pVmf->page)
5848 + {
5849 + PRINTK(KERN_ERR "vma fault oom (%s %d)\n", current->comm, current->pid);
5850 + return VM_FAULT_OOM;
5851 + }
5852 + else
5853 + {
5854 + struct VmaPageList *pVmaList;
5855 +
5856 + get_page(pVmf->page);
5857 + g_trackedPages++;
5858 +
5859 + //find our vma in the list
5860 + pVmaList = (struct VmaPageList *)pVma->vm_private_data;
5861 +
5862 + if (pVmaList)
5863 + {
5864 + PRINTK_VERBOSE(KERN_DEBUG "vma found (%s %d)\n", current->comm, current->pid);
5865 +
5866 + if (pVmaList->m_pPageTail->m_used == PAGES_PER_LIST)
5867 + {
5868 + PRINTK_VERBOSE(KERN_DEBUG "making new page list (%s %d)\n", current->comm, current->pid);
5869 + //making a new page list
5870 + pVmaList->m_pPageTail->m_pNext = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL);
5871 + if (!pVmaList->m_pPageTail->m_pNext)
5872 + return -ENOMEM;
5873 +
5874 + //update the tail pointer
5875 + pVmaList->m_pPageTail = pVmaList->m_pPageTail->m_pNext;
5876 + pVmaList->m_pPageTail->m_used = 0;
5877 + pVmaList->m_pPageTail->m_pNext = 0;
5878 + }
5879 +
5880 + PRINTK_VERBOSE(KERN_DEBUG "adding page to list (%s %d)\n", current->comm, current->pid);
5881 +
5882 + pVmaList->m_pPageTail->m_pPages[pVmaList->m_pPageTail->m_used] = pVmf->page;
5883 + pVmaList->m_pPageTail->m_used++;
5884 + }
5885 + else
5886 + PRINTK(KERN_ERR "returned page for vma we don\'t know %p (%s %d)\n", pVma, current->comm, current->pid);
5887 +
5888 + return 0;
5889 + }
5890 +}
5891 +
5892 +/****** GENERIC FUNCTIONS ******/
5893 +static int __init dmaer_init(void)
5894 +{
5895 + int result = alloc_chrdev_region(&g_majorMinor, 0, 1, "dmaer");
5896 + if (result < 0)
5897 + {
5898 + PRINTK(KERN_ERR "unable to get major device number\n");
5899 + return result;
5900 + }
5901 + else
5902 + PRINTK(KERN_DEBUG "major device number %d\n", MAJOR(g_majorMinor));
5903 +
5904 + PRINTK(KERN_DEBUG "vma list size %d, page list size %d, page size %ld\n",
5905 + sizeof(struct VmaPageList), sizeof(struct PageList), PAGE_SIZE);
5906 +
5907 + //get a dma channel to work with
5908 + result = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, (void **)&g_pDmaChanBase, &g_dmaIrq);
5909 +
5910 + //uncomment to force to channel 0
5911 + //result = 0;
5912 + //g_pDmaChanBase = 0xce808000;
5913 +
5914 + if (result < 0)
5915 + {
5916 + PRINTK(KERN_ERR "failed to allocate dma channel\n");
5917 + cdev_del(&g_cDev);
5918 + unregister_chrdev_region(g_majorMinor, 1);
5919 + }
5920 +
5921 + //reset the channel
5922 + PRINTK(KERN_DEBUG "allocated dma channel %d (%p), initial state %08x\n", result, g_pDmaChanBase, *g_pDmaChanBase);
5923 + *g_pDmaChanBase = 1 << 31;
5924 + PRINTK(KERN_DEBUG "post-reset %08x\n", *g_pDmaChanBase);
5925 +
5926 + g_dmaChan = result;
5927 +
5928 + //clear the cache stats
5929 + g_cacheHit = 0;
5930 + g_cacheMiss = 0;
5931 +
5932 + //register our device - after this we are go go go
5933 + cdev_init(&g_cDev, &g_fOps);
5934 + g_cDev.owner = THIS_MODULE;
5935 + g_cDev.ops = &g_fOps;
5936 +
5937 + result = cdev_add(&g_cDev, g_majorMinor, 1);
5938 + if (result < 0)
5939 + {
5940 + PRINTK(KERN_ERR "failed to add character device\n");
5941 + unregister_chrdev_region(g_majorMinor, 1);
5942 + bcm_dma_chan_free(g_dmaChan);
5943 + return result;
5944 + }
5945 +
5946 + return 0;
5947 +}
5948 +
5949 +static void __exit dmaer_exit(void)
5950 +{
5951 + PRINTK(KERN_INFO "closing dmaer device, cache stats: %d hits %d misses\n", g_cacheHit, g_cacheMiss);
5952 + //unregister the device
5953 + cdev_del(&g_cDev);
5954 + unregister_chrdev_region(g_majorMinor, 1);
5955 + //free the dma channel
5956 + bcm_dma_chan_free(g_dmaChan);
5957 +}
5958 +
5959 +MODULE_LICENSE("Dual BSD/GPL");
5960 +MODULE_AUTHOR("Simon Hall");
5961 +module_init(dmaer_init);
5962 +module_exit(dmaer_exit);
5963 diff --git a/arch/arm/mach-bcm2709/include/mach/arm_control.h b/arch/arm/mach-bcm2709/include/mach/arm_control.h
5964 new file mode 100644
5965 index 0000000..e346caf
5966 --- /dev/null
5967 +++ b/arch/arm/mach-bcm2709/include/mach/arm_control.h
5968 @@ -0,0 +1,493 @@
5969 +/*
5970 + * linux/arch/arm/mach-bcm2708/arm_control.h
5971 + *
5972 + * Copyright (C) 2010 Broadcom
5973 + *
5974 + * This program is free software; you can redistribute it and/or modify
5975 + * it under the terms of the GNU General Public License as published by
5976 + * the Free Software Foundation; either version 2 of the License, or
5977 + * (at your option) any later version.
5978 + *
5979 + * This program is distributed in the hope that it will be useful,
5980 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5981 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5982 + * GNU General Public License for more details.
5983 + *
5984 + * You should have received a copy of the GNU General Public License
5985 + * along with this program; if not, write to the Free Software
5986 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5987 + */
5988 +
5989 +#ifndef __BCM2708_ARM_CONTROL_H
5990 +#define __BCM2708_ARM_CONTROL_H
5991 +
5992 +/*
5993 + * Definitions and addresses for the ARM CONTROL logic
5994 + * This file is manually generated.
5995 + */
5996 +
5997 +#define ARM_BASE 0x7E00B000
5998 +
5999 +/* Basic configuration */
6000 +#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
6001 +#define ARM_C0_SIZ128M 0x00000000
6002 +#define ARM_C0_SIZ256M 0x00000001
6003 +#define ARM_C0_SIZ512M 0x00000002
6004 +#define ARM_C0_SIZ1G 0x00000003
6005 +#define ARM_C0_BRESP0 0x00000000
6006 +#define ARM_C0_BRESP1 0x00000004
6007 +#define ARM_C0_BRESP2 0x00000008
6008 +#define ARM_C0_BOOTHI 0x00000010
6009 +#define ARM_C0_UNUSED05 0x00000020 /* free */
6010 +#define ARM_C0_FULLPERI 0x00000040
6011 +#define ARM_C0_UNUSED78 0x00000180 /* free */
6012 +#define ARM_C0_JTAGMASK 0x00000E00
6013 +#define ARM_C0_JTAGOFF 0x00000000
6014 +#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
6015 +#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
6016 +#define ARM_C0_APROTMSK 0x0000F000
6017 +#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
6018 +#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
6019 +#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
6020 +#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
6021 +#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
6022 +#define ARM_C0_PRIO_L2 0x0F000000
6023 +#define ARM_C0_PRIO_UC 0xF0000000
6024 +
6025 +#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
6026 +#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
6027 +#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
6028 +
6029 +
6030 +#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
6031 +#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
6032 +#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
6033 +#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
6034 +#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
6035 +#define ARM_C1_PERSON 0x00000100 /* peripherals on */
6036 +#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
6037 +
6038 +#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
6039 +#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
6040 +#define ARM_S_READPEND 0x000003FF /* pending reads counter */
6041 +#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
6042 +
6043 +#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
6044 +#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
6045 +#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
6046 +#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
6047 +#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
6048 +#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
6049 +#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
6050 +
6051 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
6052 +#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
6053 +#define ARM_IDVAL 0x364D5241
6054 +
6055 +/* Translation memory */
6056 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
6057 +/* 32 locations: 0x100.. 0x17F */
6058 +/* 32 spare means we CAN go to 64 pages.... */
6059 +
6060 +
6061 +/* Interrupts */
6062 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
6063 +#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
6064 +#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
6065 +#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
6066 +#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
6067 +#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
6068 +#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
6069 +
6070 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
6071 +/* todo: all I1_interrupt sources */
6072 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
6073 +/* todo: all I2_interrupt sources */
6074 +
6075 +#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
6076 +#define ARM_IF_INDEX 0x0000007F /* FIQ select */
6077 +#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
6078 +#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
6079 +#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
6080 +#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
6081 +#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
6082 +#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
6083 +#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
6084 +#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
6085 +#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
6086 +
6087 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
6088 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
6089 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
6090 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
6091 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
6092 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
6093 +#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
6094 +#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
6095 +#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
6096 +#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
6097 +#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
6098 +#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
6099 +#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
6100 +
6101 +/* Timer */
6102 +/* For reg. fields see sp804 spec. */
6103 +#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
6104 +#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
6105 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
6106 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
6107 +#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
6108 +#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
6109 +#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
6110 +#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
6111 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
6112 +
6113 +#define TIMER_CTRL_ONESHOT (1 << 0)
6114 +#define TIMER_CTRL_32BIT (1 << 1)
6115 +#define TIMER_CTRL_DIV1 (0 << 2)
6116 +#define TIMER_CTRL_DIV16 (1 << 2)
6117 +#define TIMER_CTRL_DIV256 (2 << 2)
6118 +#define TIMER_CTRL_IE (1 << 5)
6119 +#define TIMER_CTRL_PERIODIC (1 << 6)
6120 +#define TIMER_CTRL_ENABLE (1 << 7)
6121 +#define TIMER_CTRL_DBGHALT (1 << 8)
6122 +#define TIMER_CTRL_ENAFREE (1 << 9)
6123 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
6124 +#define TIMER_CTRL_FREEDIV_MASK 0xff
6125 +
6126 +/* Semaphores, Doorbells, Mailboxes */
6127 +#define ARM_SBM_OWN0 (ARM_BASE+0x800)
6128 +#define ARM_SBM_OWN1 (ARM_BASE+0x900)
6129 +#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
6130 +#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
6131 +
6132 +/* MAILBOXES
6133 + * Register flags are common across all
6134 + * owner registers. See end of this section
6135 + *
6136 + * Semaphores, Doorbells, Mailboxes Owner 0
6137 + *
6138 + */
6139 +
6140 +#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
6141 +#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
6142 +#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
6143 +#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
6144 +#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
6145 +#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
6146 +#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
6147 +#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
6148 +#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
6149 +#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
6150 +#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
6151 +#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
6152 +#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
6153 +/* MAILBOX 0 access in Owner 0 area */
6154 +/* Some addresses should ONLY be used by owner 0 */
6155 +#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
6156 +#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
6157 +#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
6158 +#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
6159 +#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
6160 +#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
6161 +/* MAILBOX 1 access in Owner 0 area */
6162 +/* Owner 0 should only WRITE to this mailbox */
6163 +#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
6164 +/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
6165 +/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
6166 +/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
6167 +#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
6168 +/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
6169 +/* General SEM, BELL, MAIL config/status */
6170 +#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
6171 +#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
6172 +#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
6173 +#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
6174 +
6175 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
6176 +#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
6177 +#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
6178 +#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
6179 +#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
6180 +#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
6181 +#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
6182 +#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
6183 +#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
6184 +#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
6185 +#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
6186 +#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
6187 +#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
6188 +#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
6189 +/* MAILBOX 0 access in Owner 0 area */
6190 +/* Owner 1 should only WRITE to this mailbox */
6191 +#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
6192 +/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
6193 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
6194 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
6195 +#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
6196 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
6197 +/* MAILBOX 1 access in Owner 0 area */
6198 +#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
6199 +#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
6200 +#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
6201 +#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
6202 +#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
6203 +#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
6204 +/* General SEM, BELL, MAIL config/status */
6205 +#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
6206 +#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
6207 +#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
6208 +#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
6209 +
6210 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
6211 +#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
6212 +#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
6213 +#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
6214 +#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
6215 +#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
6216 +#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
6217 +#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
6218 +#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
6219 +#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
6220 +#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
6221 +#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
6222 +#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
6223 +#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
6224 +/* MAILBOX 0 access in Owner 2 area */
6225 +/* Owner 2 should only WRITE to this mailbox */
6226 +#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
6227 +/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
6228 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
6229 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
6230 +#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
6231 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
6232 +/* MAILBOX 1 access in Owner 2 area */
6233 +/* Owner 2 should only WRITE to this mailbox */
6234 +#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
6235 +/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
6236 +/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
6237 +/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
6238 +#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
6239 +/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
6240 +/* General SEM, BELL, MAIL config/status */
6241 +#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
6242 +#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
6243 +#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
6244 +#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
6245 +
6246 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
6247 +#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
6248 +#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
6249 +#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
6250 +#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
6251 +#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
6252 +#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
6253 +#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
6254 +#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
6255 +#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
6256 +#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
6257 +#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
6258 +#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
6259 +#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
6260 +/* MAILBOX 0 access in Owner 3 area */
6261 +/* Owner 3 should only WRITE to this mailbox */
6262 +#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
6263 +/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
6264 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
6265 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
6266 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
6267 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
6268 +/* MAILBOX 1 access in Owner 3 area */
6269 +/* Owner 3 should only WRITE to this mailbox */
6270 +#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
6271 +/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
6272 +/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
6273 +/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
6274 +#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
6275 +/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
6276 +/* General SEM, BELL, MAIL config/status */
6277 +#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
6278 +#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
6279 +#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
6280 +#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
6281 +
6282 +
6283 +
6284 +/* Mailbox flags. Valid for all owners */
6285 +
6286 +/* Mailbox status register (...0x98) */
6287 +#define ARM_MS_FULL 0x80000000
6288 +#define ARM_MS_EMPTY 0x40000000
6289 +#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
6290 +
6291 +/* MAILBOX config/status register (...0x9C) */
6292 +/* ANY write to this register clears the error bits! */
6293 +#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
6294 +#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
6295 +#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
6296 +#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
6297 +#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
6298 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
6299 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
6300 +/* Bit 7 is unused */
6301 +#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
6302 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
6303 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
6304 +
6305 +/* Semaphore clear/debug register (...0xE0) */
6306 +#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
6307 +#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
6308 +#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
6309 +#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
6310 +#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
6311 +#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
6312 +#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
6313 +#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
6314 +#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
6315 +#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
6316 +#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
6317 +#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
6318 +#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
6319 +#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
6320 +#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
6321 +#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
6322 +
6323 +/* Doorbells clear/debug register (...0xE4) */
6324 +#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
6325 +#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
6326 +#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
6327 +#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
6328 +#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
6329 +#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
6330 +#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
6331 +#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
6332 +
6333 +/* MY IRQS register (...0xF8) */
6334 +#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
6335 +#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
6336 +
6337 +/* ALL IRQS register (...0xF8) */
6338 +#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
6339 +#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
6340 +#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
6341 +#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
6342 +#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
6343 +#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
6344 +#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
6345 +#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
6346 +#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
6347 +#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
6348 +/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
6349 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
6350 +/* */
6351 +/* ARM JTAG BASH */
6352 +/* */
6353 +#define AJB_BASE 0x7e2000c0
6354 +
6355 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
6356 +#define AJB_BITS0 0x000000
6357 +#define AJB_BITS4 0x000004
6358 +#define AJB_BITS8 0x000008
6359 +#define AJB_BITS12 0x00000C
6360 +#define AJB_BITS16 0x000010
6361 +#define AJB_BITS20 0x000014
6362 +#define AJB_BITS24 0x000018
6363 +#define AJB_BITS28 0x00001C
6364 +#define AJB_BITS32 0x000020
6365 +#define AJB_BITS34 0x000022
6366 +#define AJB_OUT_MS 0x000040
6367 +#define AJB_OUT_LS 0x000000
6368 +#define AJB_INV_CLK 0x000080
6369 +#define AJB_D0_RISE 0x000100
6370 +#define AJB_D0_FALL 0x000000
6371 +#define AJB_D1_RISE 0x000200
6372 +#define AJB_D1_FALL 0x000000
6373 +#define AJB_IN_RISE 0x000400
6374 +#define AJB_IN_FALL 0x000000
6375 +#define AJB_ENABLE 0x000800
6376 +#define AJB_HOLD0 0x000000
6377 +#define AJB_HOLD1 0x001000
6378 +#define AJB_HOLD2 0x002000
6379 +#define AJB_HOLD3 0x003000
6380 +#define AJB_RESETN 0x004000
6381 +#define AJB_CLKSHFT 16
6382 +#define AJB_BUSY 0x80000000
6383 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
6384 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
6385 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
6386 +
6387 +#define ARM_LOCAL_BASE 0x40000000
6388 +#define ARM_LOCAL_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x000)
6389 +#define ARM_LOCAL_PRESCALER HW_REGISTER_RW(ARM_LOCAL_BASE+0x008)
6390 +#define ARM_LOCAL_GPU_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x00C)
6391 +#define ARM_LOCAL_PM_ROUTING_SET HW_REGISTER_RW(ARM_LOCAL_BASE+0x010)
6392 +#define ARM_LOCAL_PM_ROUTING_CLR HW_REGISTER_RW(ARM_LOCAL_BASE+0x014)
6393 +#define ARM_LOCAL_TIMER_LS HW_REGISTER_RW(ARM_LOCAL_BASE+0x01C)
6394 +#define ARM_LOCAL_TIMER_MS HW_REGISTER_RW(ARM_LOCAL_BASE+0x020)
6395 +#define ARM_LOCAL_INT_ROUTING HW_REGISTER_RW(ARM_LOCAL_BASE+0x024)
6396 +#define ARM_LOCAL_AXI_COUNT HW_REGISTER_RW(ARM_LOCAL_BASE+0x02C)
6397 +#define ARM_LOCAL_AXI_IRQ HW_REGISTER_RW(ARM_LOCAL_BASE+0x030)
6398 +#define ARM_LOCAL_TIMER_CONTROL HW_REGISTER_RW(ARM_LOCAL_BASE+0x034)
6399 +#define ARM_LOCAL_TIMER_WRITE HW_REGISTER_RW(ARM_LOCAL_BASE+0x038)
6400 +
6401 +#define ARM_LOCAL_TIMER_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x040)
6402 +#define ARM_LOCAL_TIMER_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x044)
6403 +#define ARM_LOCAL_TIMER_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x048)
6404 +#define ARM_LOCAL_TIMER_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x04C)
6405 +
6406 +#define ARM_LOCAL_MAILBOX_INT_CONTROL0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x050)
6407 +#define ARM_LOCAL_MAILBOX_INT_CONTROL1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x054)
6408 +#define ARM_LOCAL_MAILBOX_INT_CONTROL2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x058)
6409 +#define ARM_LOCAL_MAILBOX_INT_CONTROL3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x05C)
6410 +
6411 +#define ARM_LOCAL_IRQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x060)
6412 +#define ARM_LOCAL_IRQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x064)
6413 +#define ARM_LOCAL_IRQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x068)
6414 +#define ARM_LOCAL_IRQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x06C)
6415 +
6416 +#define ARM_LOCAL_FIQ_PENDING0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x070)
6417 +#define ARM_LOCAL_FIQ_PENDING1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x074)
6418 +#define ARM_LOCAL_FIQ_PENDING2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x078)
6419 +#define ARM_LOCAL_FIQ_PENDING3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x07C)
6420 +
6421 +#define ARM_LOCAL_MAILBOX0_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x080)
6422 +#define ARM_LOCAL_MAILBOX1_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x084)
6423 +#define ARM_LOCAL_MAILBOX2_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x088)
6424 +#define ARM_LOCAL_MAILBOX3_SET0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x08C)
6425 +
6426 +#define ARM_LOCAL_MAILBOX0_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x090)
6427 +#define ARM_LOCAL_MAILBOX1_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x094)
6428 +#define ARM_LOCAL_MAILBOX2_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x098)
6429 +#define ARM_LOCAL_MAILBOX3_SET1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x09C)
6430 +
6431 +#define ARM_LOCAL_MAILBOX0_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A0)
6432 +#define ARM_LOCAL_MAILBOX1_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A4)
6433 +#define ARM_LOCAL_MAILBOX2_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0A8)
6434 +#define ARM_LOCAL_MAILBOX3_SET2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0AC)
6435 +
6436 +#define ARM_LOCAL_MAILBOX0_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B0)
6437 +#define ARM_LOCAL_MAILBOX1_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B4)
6438 +#define ARM_LOCAL_MAILBOX2_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0B8)
6439 +#define ARM_LOCAL_MAILBOX3_SET3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0BC)
6440 +
6441 +#define ARM_LOCAL_MAILBOX0_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C0)
6442 +#define ARM_LOCAL_MAILBOX1_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C4)
6443 +#define ARM_LOCAL_MAILBOX2_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0C8)
6444 +#define ARM_LOCAL_MAILBOX3_CLR0 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0CC)
6445 +
6446 +#define ARM_LOCAL_MAILBOX0_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D0)
6447 +#define ARM_LOCAL_MAILBOX1_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D4)
6448 +#define ARM_LOCAL_MAILBOX2_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0D8)
6449 +#define ARM_LOCAL_MAILBOX3_CLR1 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0DC)
6450 +
6451 +#define ARM_LOCAL_MAILBOX0_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E0)
6452 +#define ARM_LOCAL_MAILBOX1_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E4)
6453 +#define ARM_LOCAL_MAILBOX2_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0E8)
6454 +#define ARM_LOCAL_MAILBOX3_CLR2 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0EC)
6455 +
6456 +#define ARM_LOCAL_MAILBOX0_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F0)
6457 +#define ARM_LOCAL_MAILBOX1_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F4)
6458 +#define ARM_LOCAL_MAILBOX2_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0F8)
6459 +#define ARM_LOCAL_MAILBOX3_CLR3 HW_REGISTER_RW(ARM_LOCAL_BASE+0x0FC)
6460 +
6461 +#endif
6462 diff --git a/arch/arm/mach-bcm2709/include/mach/arm_power.h b/arch/arm/mach-bcm2709/include/mach/arm_power.h
6463 new file mode 100644
6464 index 0000000..d3bf245
6465 --- /dev/null
6466 +++ b/arch/arm/mach-bcm2709/include/mach/arm_power.h
6467 @@ -0,0 +1,62 @@
6468 +/*
6469 + * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
6470 + *
6471 + * Copyright (C) 2010 Broadcom
6472 + *
6473 + * This program is free software; you can redistribute it and/or modify
6474 + * it under the terms of the GNU General Public License as published by
6475 + * the Free Software Foundation; either version 2 of the License, or
6476 + * (at your option) any later version.
6477 + *
6478 + * This program is distributed in the hope that it will be useful,
6479 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6480 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6481 + * GNU General Public License for more details.
6482 + *
6483 + * You should have received a copy of the GNU General Public License
6484 + * along with this program; if not, write to the Free Software
6485 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6486 + */
6487 +
6488 +#ifndef _ARM_POWER_H
6489 +#define _ARM_POWER_H
6490 +
6491 +/* Use meaningful names on each side */
6492 +#ifdef __VIDEOCORE__
6493 +#define PREFIX(x) ARM_##x
6494 +#else
6495 +#define PREFIX(x) BCM_##x
6496 +#endif
6497 +
6498 +enum {
6499 + PREFIX(POWER_SDCARD_BIT),
6500 + PREFIX(POWER_UART_BIT),
6501 + PREFIX(POWER_MINIUART_BIT),
6502 + PREFIX(POWER_USB_BIT),
6503 + PREFIX(POWER_I2C0_BIT),
6504 + PREFIX(POWER_I2C1_BIT),
6505 + PREFIX(POWER_I2C2_BIT),
6506 + PREFIX(POWER_SPI_BIT),
6507 + PREFIX(POWER_CCP2TX_BIT),
6508 + PREFIX(POWER_DSI_BIT),
6509 +
6510 + PREFIX(POWER_MAX)
6511 +};
6512 +
6513 +enum {
6514 + PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
6515 + PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
6516 + PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
6517 + PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
6518 + PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
6519 + PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
6520 + PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
6521 + PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
6522 + PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
6523 + PREFIX(POWER_DSI) = (1 << PREFIX(POWER_DSI_BIT)),
6524 +
6525 + PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
6526 + PREFIX(POWER_NONE) = 0
6527 +};
6528 +
6529 +#endif
6530 diff --git a/arch/arm/mach-bcm2709/include/mach/barriers.h b/arch/arm/mach-bcm2709/include/mach/barriers.h
6531 new file mode 100644
6532 index 0000000..723cdad
6533 --- /dev/null
6534 +++ b/arch/arm/mach-bcm2709/include/mach/barriers.h
6535 @@ -0,0 +1,3 @@
6536 +#define mb() dsb()
6537 +#define rmb() dsb()
6538 +#define wmb() mb()
6539 diff --git a/arch/arm/mach-bcm2709/include/mach/clkdev.h b/arch/arm/mach-bcm2709/include/mach/clkdev.h
6540 new file mode 100644
6541 index 0000000..04b37a8
6542 --- /dev/null
6543 +++ b/arch/arm/mach-bcm2709/include/mach/clkdev.h
6544 @@ -0,0 +1,7 @@
6545 +#ifndef __ASM_MACH_CLKDEV_H
6546 +#define __ASM_MACH_CLKDEV_H
6547 +
6548 +#define __clk_get(clk) ({ 1; })
6549 +#define __clk_put(clk) do { } while (0)
6550 +
6551 +#endif
6552 diff --git a/arch/arm/mach-bcm2709/include/mach/debug-macro.S b/arch/arm/mach-bcm2709/include/mach/debug-macro.S
6553 new file mode 100644
6554 index 0000000..b24304a
6555 --- /dev/null
6556 +++ b/arch/arm/mach-bcm2709/include/mach/debug-macro.S
6557 @@ -0,0 +1,22 @@
6558 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
6559 + *
6560 + * Debugging macro include header
6561 + *
6562 + * Copyright (C) 2010 Broadcom
6563 + * Copyright (C) 1994-1999 Russell King
6564 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
6565 + *
6566 + * This program is free software; you can redistribute it and/or modify
6567 + * it under the terms of the GNU General Public License version 2 as
6568 + * published by the Free Software Foundation.
6569 + *
6570 +*/
6571 +
6572 +#include <mach/platform.h>
6573 +
6574 + .macro addruart, rp, rv, tmp
6575 + ldr \rp, =UART0_BASE
6576 + ldr \rv, =IO_ADDRESS(UART0_BASE)
6577 + .endm
6578 +
6579 +#include <debug/pl01x.S>
6580 diff --git a/arch/arm/mach-bcm2709/include/mach/dma.h b/arch/arm/mach-bcm2709/include/mach/dma.h
6581 new file mode 100644
6582 index 0000000..d03e7b5
6583 --- /dev/null
6584 +++ b/arch/arm/mach-bcm2709/include/mach/dma.h
6585 @@ -0,0 +1,94 @@
6586 +/*
6587 + * linux/arch/arm/mach-bcm2708/include/mach/dma.h
6588 + *
6589 + * Copyright (C) 2010 Broadcom
6590 + *
6591 + * This program is free software; you can redistribute it and/or modify
6592 + * it under the terms of the GNU General Public License version 2 as
6593 + * published by the Free Software Foundation.
6594 + */
6595 +
6596 +
6597 +#ifndef _MACH_BCM2708_DMA_H
6598 +#define _MACH_BCM2708_DMA_H
6599 +
6600 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
6601 +
6602 +/* DMA CS Control and Status bits */
6603 +#define BCM2708_DMA_ACTIVE (1 << 0)
6604 +#define BCM2708_DMA_INT (1 << 2)
6605 +#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
6606 +#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
6607 +#define BCM2708_DMA_ERR (1 << 8)
6608 +#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
6609 +#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
6610 +
6611 +/* DMA control block "info" field bits */
6612 +#define BCM2708_DMA_INT_EN (1 << 0)
6613 +#define BCM2708_DMA_TDMODE (1 << 1)
6614 +#define BCM2708_DMA_WAIT_RESP (1 << 3)
6615 +#define BCM2708_DMA_D_INC (1 << 4)
6616 +#define BCM2708_DMA_D_WIDTH (1 << 5)
6617 +#define BCM2708_DMA_D_DREQ (1 << 6)
6618 +#define BCM2708_DMA_S_INC (1 << 8)
6619 +#define BCM2708_DMA_S_WIDTH (1 << 9)
6620 +#define BCM2708_DMA_S_DREQ (1 << 10)
6621 +
6622 +#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12)
6623 +#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
6624 +#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21)
6625 +
6626 +#define BCM2708_DMA_DREQ_EMMC 11
6627 +#define BCM2708_DMA_DREQ_SDHOST 13
6628 +
6629 +#define BCM2708_DMA_CS 0x00 /* Control and Status */
6630 +#define BCM2708_DMA_ADDR 0x04
6631 +/* the current control block appears in the following registers - read only */
6632 +#define BCM2708_DMA_INFO 0x08
6633 +#define BCM2708_DMA_SOURCE_AD 0x0c
6634 +#define BCM2708_DMA_DEST_AD 0x10
6635 +#define BCM2708_DMA_NEXTCB 0x1C
6636 +#define BCM2708_DMA_DEBUG 0x20
6637 +
6638 +#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
6639 +#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
6640 +
6641 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
6642 +
6643 +struct bcm2708_dma_cb {
6644 + unsigned long info;
6645 + unsigned long src;
6646 + unsigned long dst;
6647 + unsigned long length;
6648 + unsigned long stride;
6649 + unsigned long next;
6650 + unsigned long pad[2];
6651 +};
6652 +struct scatterlist;
6653 +
6654 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
6655 +extern void bcm_dma_start(void __iomem *dma_chan_base,
6656 + dma_addr_t control_block);
6657 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
6658 +extern bool bcm_dma_is_busy(void __iomem *dma_chan_base);
6659 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
6660 +
6661 +/* When listing features we can ask for when allocating DMA channels give
6662 + those with higher priority smaller ordinal numbers */
6663 +#define BCM_DMA_FEATURE_FAST_ORD 0
6664 +#define BCM_DMA_FEATURE_BULK_ORD 1
6665 +#define BCM_DMA_FEATURE_NORMAL_ORD 2
6666 +#define BCM_DMA_FEATURE_LITE_ORD 3
6667 +#define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
6668 +#define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
6669 +#define BCM_DMA_FEATURE_NORMAL (1<<BCM_DMA_FEATURE_NORMAL_ORD)
6670 +#define BCM_DMA_FEATURE_LITE (1<<BCM_DMA_FEATURE_LITE_ORD)
6671 +#define BCM_DMA_FEATURE_COUNT 4
6672 +
6673 +/* return channel no or -ve error */
6674 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
6675 + void __iomem **out_dma_base, int *out_dma_irq);
6676 +extern int bcm_dma_chan_free(int channel);
6677 +
6678 +
6679 +#endif /* _MACH_BCM2708_DMA_H */
6680 diff --git a/arch/arm/mach-bcm2709/include/mach/entry-macro.S b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
6681 new file mode 100644
6682 index 0000000..d08591b
6683 --- /dev/null
6684 +++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
6685 @@ -0,0 +1,123 @@
6686 +/*
6687 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
6688 + *
6689 + * Low-level IRQ helper macros for BCM2708 platforms
6690 + *
6691 + * Copyright (C) 2010 Broadcom
6692 + *
6693 + * This program is free software; you can redistribute it and/or modify
6694 + * it under the terms of the GNU General Public License as published by
6695 + * the Free Software Foundation; either version 2 of the License, or
6696 + * (at your option) any later version.
6697 + *
6698 + * This program is distributed in the hope that it will be useful,
6699 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6700 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6701 + * GNU General Public License for more details.
6702 + *
6703 + * You should have received a copy of the GNU General Public License
6704 + * along with this program; if not, write to the Free Software
6705 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6706 + */
6707 +#include <mach/hardware.h>
6708 +#include <mach/irqs.h>
6709 +
6710 + .macro disable_fiq
6711 + .endm
6712 +
6713 + .macro get_irqnr_preamble, base, tmp
6714 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
6715 + .endm
6716 +
6717 + .macro arch_ret_to_user, tmp1, tmp2
6718 + .endm
6719 +
6720 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
6721 + /* get core number */
6722 + mrc p15, 0, \tmp, c0, c0, 5
6723 + ubfx \tmp, \tmp, #0, #2
6724 +
6725 + /* get core's local interrupt controller */
6726 + ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
6727 + add \irqstat, \irqstat, \tmp, lsl #2
6728 + ldr \tmp, [\irqstat]
6729 + /* ignore gpu interrupt */
6730 + bic \tmp, #0x100
6731 + /* ignore mailbox interrupts */
6732 + bics \tmp, #0xf0
6733 + beq 1005f
6734 +
6735 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
6736 + @ N.B. CLZ is an ARM5 instruction.
6737 + mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
6738 + sub \irqstat, \tmp, #1
6739 + eor \irqstat, \irqstat, \tmp
6740 + clz \tmp, \irqstat
6741 + sub \irqnr, \tmp
6742 + b 1020f
6743 +1005:
6744 + /* get core number */
6745 + mrc p15, 0, \tmp, c0, c0, 5
6746 + ubfx \tmp, \tmp, #0, #2
6747 +
6748 + cmp \tmp, #1
6749 + beq 1020f
6750 + cmp \tmp, #2
6751 + beq 1020f
6752 + cmp \tmp, #3
6753 + beq 1020f
6754 +
6755 + /* get masked status */
6756 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
6757 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
6758 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
6759 + /* clear bits 8 and 9, and test */
6760 + bics \irqstat, \irqstat, #0x300
6761 + bne 1010f
6762 +
6763 + tst \tmp, #0x100
6764 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
6765 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
6766 + @ Mask out the interrupts also present in PEND0 - see SW-5809
6767 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
6768 + bicne \irqstat, #((1<<18) | (1<<19))
6769 + bne 1010f
6770 +
6771 + tst \tmp, #0x200
6772 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
6773 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
6774 + @ Mask out the interrupts also present in PEND0 - see SW-5809
6775 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
6776 + bicne \irqstat, #((1<<30))
6777 + beq 1020f
6778 +
6779 +1010:
6780 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
6781 + @ N.B. CLZ is an ARM5 instruction.
6782 + sub \tmp, \irqstat, #1
6783 + eor \irqstat, \irqstat, \tmp
6784 + clz \tmp, \irqstat
6785 + sub \irqnr, \tmp
6786 +
6787 +1020: @ EQ will be set if no irqs pending
6788 +
6789 + .endm
6790 +
6791 + .macro test_for_ipi, irqnr, irqstat, base, tmp
6792 + /* get core number */
6793 + mrc p15, 0, \tmp, c0, c0, 5
6794 + ubfx \tmp, \tmp, #0, #2
6795 + /* get core's mailbox interrupt control */
6796 + ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
6797 + add \irqstat, \irqstat, \tmp, lsl #4
6798 + ldr \tmp, [\irqstat]
6799 + cmp \tmp, #0
6800 + beq 1030f
6801 + clz \tmp, \tmp
6802 + rsb \irqnr, \tmp, #31
6803 + mov \tmp, #1
6804 + lsl \tmp, \irqnr
6805 + str \tmp, [\irqstat] @ clear interrupt source
6806 + dsb
6807 +1030: @ EQ will be set if no irqs pending
6808 + .endm
6809 diff --git a/arch/arm/mach-bcm2709/include/mach/frc.h b/arch/arm/mach-bcm2709/include/mach/frc.h
6810 new file mode 100644
6811 index 0000000..dd51e07
6812 --- /dev/null
6813 +++ b/arch/arm/mach-bcm2709/include/mach/frc.h
6814 @@ -0,0 +1,38 @@
6815 +/*
6816 + * arch/arm/mach-bcm2708/include/mach/timex.h
6817 + *
6818 + * BCM2708 free running counter (timer)
6819 + *
6820 + * Copyright (C) 2010 Broadcom
6821 + *
6822 + * This program is free software; you can redistribute it and/or modify
6823 + * it under the terms of the GNU General Public License as published by
6824 + * the Free Software Foundation; either version 2 of the License, or
6825 + * (at your option) any later version.
6826 + *
6827 + * This program is distributed in the hope that it will be useful,
6828 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6829 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6830 + * GNU General Public License for more details.
6831 + *
6832 + * You should have received a copy of the GNU General Public License
6833 + * along with this program; if not, write to the Free Software
6834 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6835 + */
6836 +
6837 +#ifndef _MACH_FRC_H
6838 +#define _MACH_FRC_H
6839 +
6840 +#define FRC_TICK_RATE (1000000)
6841 +
6842 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
6843 + (slightly faster than frc_clock_ticks63()
6844 + */
6845 +extern unsigned long frc_clock_ticks32(void);
6846 +
6847 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
6848 + * Note - top bit should be ignored (see cnt32_to_63)
6849 + */
6850 +extern unsigned long long frc_clock_ticks63(void);
6851 +
6852 +#endif
6853 diff --git a/arch/arm/mach-bcm2709/include/mach/gpio.h b/arch/arm/mach-bcm2709/include/mach/gpio.h
6854 new file mode 100644
6855 index 0000000..7965a97
6856 --- /dev/null
6857 +++ b/arch/arm/mach-bcm2709/include/mach/gpio.h
6858 @@ -0,0 +1,17 @@
6859 +/*
6860 + * arch/arm/mach-bcm2708/include/mach/gpio.h
6861 + *
6862 + * This file is licensed under the terms of the GNU General Public
6863 + * License version 2. This program is licensed "as is" without any
6864 + * warranty of any kind, whether express or implied.
6865 + */
6866 +
6867 +#ifndef __ASM_ARCH_GPIO_H
6868 +#define __ASM_ARCH_GPIO_H
6869 +
6870 +#define BCM2708_NR_GPIOS 54 // number of gpio lines
6871 +
6872 +#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
6873 +#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
6874 +
6875 +#endif
6876 diff --git a/arch/arm/mach-bcm2709/include/mach/hardware.h b/arch/arm/mach-bcm2709/include/mach/hardware.h
6877 new file mode 100644
6878 index 0000000..c2954e8
6879 --- /dev/null
6880 +++ b/arch/arm/mach-bcm2709/include/mach/hardware.h
6881 @@ -0,0 +1,28 @@
6882 +/*
6883 + * arch/arm/mach-bcm2708/include/mach/hardware.h
6884 + *
6885 + * This file contains the hardware definitions of the BCM2708 devices.
6886 + *
6887 + * Copyright (C) 2010 Broadcom
6888 + *
6889 + * This program is free software; you can redistribute it and/or modify
6890 + * it under the terms of the GNU General Public License as published by
6891 + * the Free Software Foundation; either version 2 of the License, or
6892 + * (at your option) any later version.
6893 + *
6894 + * This program is distributed in the hope that it will be useful,
6895 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6896 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6897 + * GNU General Public License for more details.
6898 + *
6899 + * You should have received a copy of the GNU General Public License
6900 + * along with this program; if not, write to the Free Software
6901 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6902 + */
6903 +#ifndef __ASM_ARCH_HARDWARE_H
6904 +#define __ASM_ARCH_HARDWARE_H
6905 +
6906 +#include <asm/sizes.h>
6907 +#include <mach/platform.h>
6908 +
6909 +#endif
6910 diff --git a/arch/arm/mach-bcm2709/include/mach/io.h b/arch/arm/mach-bcm2709/include/mach/io.h
6911 new file mode 100644
6912 index 0000000..e6eb84d
6913 --- /dev/null
6914 +++ b/arch/arm/mach-bcm2709/include/mach/io.h
6915 @@ -0,0 +1,27 @@
6916 +/*
6917 + * arch/arm/mach-bcm2708/include/mach/io.h
6918 + *
6919 + * Copyright (C) 2003 ARM Limited
6920 + *
6921 + * This program is free software; you can redistribute it and/or modify
6922 + * it under the terms of the GNU General Public License as published by
6923 + * the Free Software Foundation; either version 2 of the License, or
6924 + * (at your option) any later version.
6925 + *
6926 + * This program is distributed in the hope that it will be useful,
6927 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6928 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6929 + * GNU General Public License for more details.
6930 + *
6931 + * You should have received a copy of the GNU General Public License
6932 + * along with this program; if not, write to the Free Software
6933 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6934 + */
6935 +#ifndef __ASM_ARM_ARCH_IO_H
6936 +#define __ASM_ARM_ARCH_IO_H
6937 +
6938 +#define IO_SPACE_LIMIT 0xffffffff
6939 +
6940 +#define __io(a) __typesafe_io(a)
6941 +
6942 +#endif
6943 diff --git a/arch/arm/mach-bcm2709/include/mach/irqs.h b/arch/arm/mach-bcm2709/include/mach/irqs.h
6944 new file mode 100644
6945 index 0000000..3a883d2
6946 --- /dev/null
6947 +++ b/arch/arm/mach-bcm2709/include/mach/irqs.h
6948 @@ -0,0 +1,225 @@
6949 +/*
6950 + * arch/arm/mach-bcm2708/include/mach/irqs.h
6951 + *
6952 + * Copyright (C) 2010 Broadcom
6953 + * Copyright (C) 2003 ARM Limited
6954 + * Copyright (C) 2000 Deep Blue Solutions Ltd.
6955 + *
6956 + * This program is free software; you can redistribute it and/or modify
6957 + * it under the terms of the GNU General Public License as published by
6958 + * the Free Software Foundation; either version 2 of the License, or
6959 + * (at your option) any later version.
6960 + *
6961 + * This program is distributed in the hope that it will be useful,
6962 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6963 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6964 + * GNU General Public License for more details.
6965 + *
6966 + * You should have received a copy of the GNU General Public License
6967 + * along with this program; if not, write to the Free Software
6968 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
6969 + */
6970 +
6971 +#ifndef _BCM2708_IRQS_H_
6972 +#define _BCM2708_IRQS_H_
6973 +
6974 +#include <mach/platform.h>
6975 +
6976 +/*
6977 + * IRQ interrupts definitions are the same as the INT definitions
6978 + * held within platform.h
6979 + */
6980 +#define IRQ_ARMCTRL_START 0
6981 +#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
6982 +#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
6983 +#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
6984 +#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
6985 +#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
6986 +#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
6987 +#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
6988 +#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
6989 +#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
6990 +#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
6991 +#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
6992 +#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
6993 +#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
6994 +#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
6995 +#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
6996 +#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
6997 +#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
6998 +#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
6999 +#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
7000 +#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
7001 +#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
7002 +#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
7003 +#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
7004 +#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
7005 +#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
7006 +#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
7007 +#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
7008 +#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
7009 +#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
7010 +#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
7011 +#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
7012 +#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
7013 +#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
7014 +#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
7015 +#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
7016 +#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
7017 +#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
7018 +#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
7019 +#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
7020 +#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
7021 +#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
7022 +#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
7023 +#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
7024 +#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
7025 +#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
7026 +#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
7027 +#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
7028 +#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
7029 +#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
7030 +#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
7031 +#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
7032 +#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
7033 +#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
7034 +#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
7035 +#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
7036 +#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
7037 +#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
7038 +#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
7039 +#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
7040 +#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
7041 +#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
7042 +#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
7043 +#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
7044 +#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
7045 +
7046 +#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
7047 +#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
7048 +#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
7049 +#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
7050 +#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
7051 +#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
7052 +#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
7053 +#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
7054 +#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
7055 +#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
7056 +
7057 +#define IRQ_ARM_LOCAL_CNTPSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
7058 +#define IRQ_ARM_LOCAL_CNTPNSIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
7059 +#define IRQ_ARM_LOCAL_CNTHPIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
7060 +#define IRQ_ARM_LOCAL_CNTVIRQ (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
7061 +#define IRQ_ARM_LOCAL_MAILBOX0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
7062 +#define IRQ_ARM_LOCAL_MAILBOX1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
7063 +#define IRQ_ARM_LOCAL_MAILBOX2 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
7064 +#define IRQ_ARM_LOCAL_MAILBOX3 (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
7065 +#define IRQ_ARM_LOCAL_GPU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
7066 +#define IRQ_ARM_LOCAL_PMU_FAST (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
7067 +#define IRQ_ARM_LOCAL_ZERO (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
7068 +#define IRQ_ARM_LOCAL_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
7069 +
7070 +#define FIQ_START HARD_IRQS
7071 +
7072 +/*
7073 + * FIQ interrupts definitions are the same as the INT definitions.
7074 + */
7075 +#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0)
7076 +#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1)
7077 +#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2)
7078 +#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3)
7079 +#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0)
7080 +#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1)
7081 +#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2)
7082 +#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG)
7083 +#define FIQ_ISP (FIQ_START+INTERRUPT_ISP)
7084 +#define FIQ_USB (FIQ_START+INTERRUPT_USB)
7085 +#define FIQ_3D (FIQ_START+INTERRUPT_3D)
7086 +#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER)
7087 +#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0)
7088 +#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1)
7089 +#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2)
7090 +#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3)
7091 +#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0)
7092 +#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1)
7093 +#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2)
7094 +#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3)
7095 +#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4)
7096 +#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5)
7097 +#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6)
7098 +#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7)
7099 +#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8)
7100 +#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9)
7101 +#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10)
7102 +#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11)
7103 +#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12)
7104 +#define FIQ_AUX (FIQ_START+INTERRUPT_AUX)
7105 +#define FIQ_ARM (FIQ_START+INTERRUPT_ARM)
7106 +#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA)
7107 +#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT)
7108 +#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER)
7109 +#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX)
7110 +#define FIQ_SDC (FIQ_START+INTERRUPT_SDC)
7111 +#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0)
7112 +#define FIQ_AVE (FIQ_START+INTERRUPT_AVE)
7113 +#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0)
7114 +#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1)
7115 +#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0)
7116 +#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1)
7117 +#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1)
7118 +#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV)
7119 +#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1)
7120 +#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0)
7121 +#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1)
7122 +#define FIQ_CPR (FIQ_START+INTERRUPT_CPR)
7123 +#define FIQ_SMI (FIQ_START+INTERRUPT_SMI)
7124 +#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0)
7125 +#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1)
7126 +#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2)
7127 +#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3)
7128 +#define FIQ_I2C (FIQ_START+INTERRUPT_I2C)
7129 +#define FIQ_SPI (FIQ_START+INTERRUPT_SPI)
7130 +#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM)
7131 +#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO)
7132 +#define FIQ_UART (FIQ_START+INTERRUPT_UART)
7133 +#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS)
7134 +#define FIQ_VEC (FIQ_START+INTERRUPT_VEC)
7135 +#define FIQ_CPG (FIQ_START+INTERRUPT_CPG)
7136 +#define FIQ_RNG (FIQ_START+INTERRUPT_RNG)
7137 +#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO)
7138 +#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON)
7139 +
7140 +#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER)
7141 +#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX)
7142 +#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0)
7143 +#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1)
7144 +#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED)
7145 +#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED)
7146 +#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0)
7147 +#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1)
7148 +#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1)
7149 +#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2)
7150 +
7151 +#define FIQ_ARM_LOCAL_CNTPSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPSIRQ)
7152 +#define FIQ_ARM_LOCAL_CNTPNSIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTPNSIRQ)
7153 +#define FIQ_ARM_LOCAL_CNTHPIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTHPIRQ)
7154 +#define FIQ_ARM_LOCAL_CNTVIRQ (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_CNTVIRQ)
7155 +#define FIQ_ARM_LOCAL_MAILBOX0 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX0)
7156 +#define FIQ_ARM_LOCAL_MAILBOX1 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX1)
7157 +#define FIQ_ARM_LOCAL_MAILBOX2 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX2)
7158 +#define FIQ_ARM_LOCAL_MAILBOX3 (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_MAILBOX3)
7159 +#define FIQ_ARM_LOCAL_GPU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_GPU_FAST)
7160 +#define FIQ_ARM_LOCAL_PMU_FAST (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_PMU_FAST)
7161 +#define FIQ_ARM_LOCAL_ZERO (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_ZERO)
7162 +#define FIQ_ARM_LOCAL_TIMER (FIQ_ARMCTRL_START + INTERRUPT_ARM_LOCAL_TIMER)
7163 +
7164 +#define HARD_IRQS (128)
7165 +#define FIQ_IRQS (128)
7166 +#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS)
7167 +#define GPIO_IRQS (32*5)
7168 +#define SPARE_ALLOC_IRQS 32
7169 +#define BCM2708_ALLOC_IRQS (HARD_IRQS+FIQ_IRQS+GPIO_IRQS+SPARE_ALLOC_IRQS)
7170 +#define FREE_IRQS 32
7171 +#define NR_IRQS (BCM2708_ALLOC_IRQS+FREE_IRQS)
7172 +
7173 +#endif /* _BCM2708_IRQS_H_ */
7174 diff --git a/arch/arm/mach-bcm2709/include/mach/memory.h b/arch/arm/mach-bcm2709/include/mach/memory.h
7175 new file mode 100644
7176 index 0000000..7548a52
7177 --- /dev/null
7178 +++ b/arch/arm/mach-bcm2709/include/mach/memory.h
7179 @@ -0,0 +1,57 @@
7180 +/*
7181 + * arch/arm/mach-bcm2708/include/mach/memory.h
7182 + *
7183 + * Copyright (C) 2010 Broadcom
7184 + *
7185 + * This program is free software; you can redistribute it and/or modify
7186 + * it under the terms of the GNU General Public License as published by
7187 + * the Free Software Foundation; either version 2 of the License, or
7188 + * (at your option) any later version.
7189 + *
7190 + * This program is distributed in the hope that it will be useful,
7191 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7192 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7193 + * GNU General Public License for more details.
7194 + *
7195 + * You should have received a copy of the GNU General Public License
7196 + * along with this program; if not, write to the Free Software
7197 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7198 + */
7199 +#ifndef __ASM_ARCH_MEMORY_H
7200 +#define __ASM_ARCH_MEMORY_H
7201 +
7202 +/* Memory overview:
7203 +
7204 + [ARMcore] <--virtual addr-->
7205 + [ARMmmu] <--physical addr-->
7206 + [GERTmap] <--bus add-->
7207 + [VCperiph]
7208 +
7209 +*/
7210 +
7211 +/*
7212 + * Physical DRAM offset.
7213 + */
7214 +#define BCM_PLAT_PHYS_OFFSET UL(0x00000000)
7215 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
7216 +
7217 +#ifdef CONFIG_BCM2708_NOL2CACHE
7218 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
7219 +#else
7220 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
7221 +#endif
7222 +
7223 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
7224 + * will provide the offset into this area as well as setting the bits that
7225 + * stop the L1 and L2 cache from being used
7226 + *
7227 + * WARNING: this only works because the ARM is given memory at a fixed location
7228 + * (ARMMEM_OFFSET)
7229 + */
7230 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
7231 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
7232 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
7233 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
7234 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - BCM_PLAT_PHYS_OFFSET))
7235 +
7236 +#endif
7237 diff --git a/arch/arm/mach-bcm2709/include/mach/platform.h b/arch/arm/mach-bcm2709/include/mach/platform.h
7238 new file mode 100644
7239 index 0000000..7157f38
7240 --- /dev/null
7241 +++ b/arch/arm/mach-bcm2709/include/mach/platform.h
7242 @@ -0,0 +1,225 @@
7243 +/*
7244 + * arch/arm/mach-bcm2708/include/mach/platform.h
7245 + *
7246 + * Copyright (C) 2010 Broadcom
7247 + *
7248 + * This program is free software; you can redistribute it and/or modify
7249 + * it under the terms of the GNU General Public License as published by
7250 + * the Free Software Foundation; either version 2 of the License, or
7251 + * (at your option) any later version.
7252 + *
7253 + * This program is distributed in the hope that it will be useful,
7254 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7255 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7256 + * GNU General Public License for more details.
7257 + *
7258 + * You should have received a copy of the GNU General Public License
7259 + * along with this program; if not, write to the Free Software
7260 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7261 + */
7262 +
7263 +#ifndef _BCM2708_PLATFORM_H
7264 +#define _BCM2708_PLATFORM_H
7265 +
7266 +
7267 +/* macros to get at IO space when running virtually */
7268 +#define IO_ADDRESS(x) (((x) & 0x00ffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
7269 +
7270 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
7271 +
7272 +
7273 +/*
7274 + * SDRAM
7275 + */
7276 +#define BCM2708_SDRAM_BASE 0x00000000
7277 +
7278 +/*
7279 + * Logic expansion modules
7280 + *
7281 + */
7282 +
7283 +
7284 +/* ------------------------------------------------------------------------
7285 + * BCM2708 ARMCTRL Registers
7286 + * ------------------------------------------------------------------------
7287 + */
7288 +
7289 +#define HW_REGISTER_RW(addr) (addr)
7290 +#define HW_REGISTER_RO(addr) (addr)
7291 +
7292 +#include "arm_control.h"
7293 +#undef ARM_BASE
7294 +
7295 +/*
7296 + * Definitions and addresses for the ARM CONTROL logic
7297 + * This file is manually generated.
7298 + */
7299 +
7300 +#define BCM2708_PERI_BASE 0x3F000000
7301 +#define IC0_BASE (BCM2708_PERI_BASE + 0x2000)
7302 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
7303 +#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */
7304 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
7305 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
7306 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
7307 +#define PCM_CLOCK_BASE (BCM2708_PERI_BASE + 0x101098) /* PCM Clock */
7308 +#define RNG_BASE (BCM2708_PERI_BASE + 0x104000) /* Hardware RNG */
7309 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
7310 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
7311 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
7312 +#define I2S_BASE (BCM2708_PERI_BASE + 0x203000) /* I2S */
7313 +#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */
7314 +#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */
7315 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
7316 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
7317 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
7318 +#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */
7319 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
7320 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
7321 +
7322 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
7323 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
7324 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
7325 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
7326 +
7327 +
7328 +/*
7329 + * Interrupt assignments
7330 + */
7331 +
7332 +#define ARM_IRQ1_BASE 0
7333 +#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
7334 +#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
7335 +#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
7336 +#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
7337 +#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
7338 +#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
7339 +#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
7340 +#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
7341 +#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
7342 +#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
7343 +#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
7344 +#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
7345 +#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
7346 +#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
7347 +#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
7348 +#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
7349 +#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
7350 +#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
7351 +#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
7352 +#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
7353 +#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
7354 +#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
7355 +#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
7356 +#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
7357 +#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
7358 +#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
7359 +#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
7360 +#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
7361 +#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
7362 +#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
7363 +#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
7364 +#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
7365 +
7366 +#define ARM_IRQ2_BASE 32
7367 +#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
7368 +#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
7369 +#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
7370 +#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
7371 +#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
7372 +#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
7373 +#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
7374 +#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
7375 +#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
7376 +#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
7377 +#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
7378 +#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
7379 +#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
7380 +#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
7381 +#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
7382 +#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
7383 +#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
7384 +#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
7385 +#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
7386 +#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
7387 +#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
7388 +#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
7389 +#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
7390 +#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
7391 +#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
7392 +#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
7393 +#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
7394 +#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
7395 +#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
7396 +#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
7397 +#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
7398 +#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
7399 +
7400 +#define ARM_IRQ0_BASE 64
7401 +#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
7402 +#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
7403 +#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
7404 +#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
7405 +#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
7406 +#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
7407 +#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
7408 +#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
7409 +#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
7410 +#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
7411 +#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
7412 +#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
7413 +#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
7414 +#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
7415 +#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
7416 +#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
7417 +#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
7418 +#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
7419 +#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
7420 +#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
7421 +#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
7422 +
7423 +#define ARM_IRQ_LOCAL_BASE 96
7424 +#define INTERRUPT_ARM_LOCAL_CNTPSIRQ (ARM_IRQ_LOCAL_BASE + 0)
7425 +#define INTERRUPT_ARM_LOCAL_CNTPNSIRQ (ARM_IRQ_LOCAL_BASE + 1)
7426 +#define INTERRUPT_ARM_LOCAL_CNTHPIRQ (ARM_IRQ_LOCAL_BASE + 2)
7427 +#define INTERRUPT_ARM_LOCAL_CNTVIRQ (ARM_IRQ_LOCAL_BASE + 3)
7428 +#define INTERRUPT_ARM_LOCAL_MAILBOX0 (ARM_IRQ_LOCAL_BASE + 4)
7429 +#define INTERRUPT_ARM_LOCAL_MAILBOX1 (ARM_IRQ_LOCAL_BASE + 5)
7430 +#define INTERRUPT_ARM_LOCAL_MAILBOX2 (ARM_IRQ_LOCAL_BASE + 6)
7431 +#define INTERRUPT_ARM_LOCAL_MAILBOX3 (ARM_IRQ_LOCAL_BASE + 7)
7432 +#define INTERRUPT_ARM_LOCAL_GPU_FAST (ARM_IRQ_LOCAL_BASE + 8)
7433 +#define INTERRUPT_ARM_LOCAL_PMU_FAST (ARM_IRQ_LOCAL_BASE + 9)
7434 +#define INTERRUPT_ARM_LOCAL_ZERO (ARM_IRQ_LOCAL_BASE + 10)
7435 +#define INTERRUPT_ARM_LOCAL_TIMER (ARM_IRQ_LOCAL_BASE + 11)
7436 +
7437 +/*
7438 + * Watchdog
7439 + */
7440 +#define PM_RSTC (PM_BASE+0x1c)
7441 +#define PM_RSTS (PM_BASE+0x20)
7442 +#define PM_WDOG (PM_BASE+0x24)
7443 +
7444 +#define PM_WDOG_RESET 0000000000
7445 +#define PM_PASSWORD 0x5a000000
7446 +#define PM_WDOG_TIME_SET 0x000fffff
7447 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
7448 +#define PM_RSTC_WRCFG_SET 0x00000030
7449 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
7450 +#define PM_RSTC_RESET 0x00000102
7451 +
7452 +#define PM_RSTS_HADPOR_SET 0x00001000
7453 +#define PM_RSTS_HADSRH_SET 0x00000400
7454 +#define PM_RSTS_HADSRF_SET 0x00000200
7455 +#define PM_RSTS_HADSRQ_SET 0x00000100
7456 +#define PM_RSTS_HADWRH_SET 0x00000040
7457 +#define PM_RSTS_HADWRF_SET 0x00000020
7458 +#define PM_RSTS_HADWRQ_SET 0x00000010
7459 +#define PM_RSTS_HADDRH_SET 0x00000004
7460 +#define PM_RSTS_HADDRF_SET 0x00000002
7461 +#define PM_RSTS_HADDRQ_SET 0x00000001
7462 +
7463 +#define UART0_CLOCK 3000000
7464 +
7465 +#endif
7466 +
7467 +/* END */
7468 diff --git a/arch/arm/mach-bcm2709/include/mach/power.h b/arch/arm/mach-bcm2709/include/mach/power.h
7469 new file mode 100644
7470 index 0000000..52b3b02
7471 --- /dev/null
7472 +++ b/arch/arm/mach-bcm2709/include/mach/power.h
7473 @@ -0,0 +1,26 @@
7474 +/*
7475 + * linux/arch/arm/mach-bcm2708/power.h
7476 + *
7477 + * Copyright (C) 2010 Broadcom
7478 + *
7479 + * This program is free software; you can redistribute it and/or modify
7480 + * it under the terms of the GNU General Public License version 2 as
7481 + * published by the Free Software Foundation.
7482 + *
7483 + * This device provides a shared mechanism for controlling the power to
7484 + * VideoCore subsystems.
7485 + */
7486 +
7487 +#ifndef _MACH_BCM2708_POWER_H
7488 +#define _MACH_BCM2708_POWER_H
7489 +
7490 +#include <linux/types.h>
7491 +#include <mach/arm_power.h>
7492 +
7493 +typedef unsigned int BCM_POWER_HANDLE_T;
7494 +
7495 +extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
7496 +extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
7497 +extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
7498 +
7499 +#endif
7500 diff --git a/arch/arm/mach-bcm2709/include/mach/system.h b/arch/arm/mach-bcm2709/include/mach/system.h
7501 new file mode 100644
7502 index 0000000..2d0b821
7503 --- /dev/null
7504 +++ b/arch/arm/mach-bcm2709/include/mach/system.h
7505 @@ -0,0 +1,38 @@
7506 +/*
7507 + * arch/arm/mach-bcm2708/include/mach/system.h
7508 + *
7509 + * Copyright (C) 2010 Broadcom
7510 + * Copyright (C) 2003 ARM Limited
7511 + * Copyright (C) 2000 Deep Blue Solutions Ltd
7512 + *
7513 + * This program is free software; you can redistribute it and/or modify
7514 + * it under the terms of the GNU General Public License as published by
7515 + * the Free Software Foundation; either version 2 of the License, or
7516 + * (at your option) any later version.
7517 + *
7518 + * This program is distributed in the hope that it will be useful,
7519 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7520 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7521 + * GNU General Public License for more details.
7522 + *
7523 + * You should have received a copy of the GNU General Public License
7524 + * along with this program; if not, write to the Free Software
7525 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7526 + */
7527 +#ifndef __ASM_ARCH_SYSTEM_H
7528 +#define __ASM_ARCH_SYSTEM_H
7529 +
7530 +#include <linux/io.h>
7531 +#include <mach/hardware.h>
7532 +#include <mach/platform.h>
7533 +
7534 +static inline void arch_idle(void)
7535 +{
7536 + /*
7537 + * This should do all the clock switching
7538 + * and wait for interrupt tricks
7539 + */
7540 + cpu_do_idle();
7541 +}
7542 +
7543 +#endif
7544 diff --git a/arch/arm/mach-bcm2709/include/mach/timex.h b/arch/arm/mach-bcm2709/include/mach/timex.h
7545 new file mode 100644
7546 index 0000000..64a660c
7547 --- /dev/null
7548 +++ b/arch/arm/mach-bcm2709/include/mach/timex.h
7549 @@ -0,0 +1,23 @@
7550 +/*
7551 + * arch/arm/mach-bcm2708/include/mach/timex.h
7552 + *
7553 + * BCM2708 sysem clock frequency
7554 + *
7555 + * Copyright (C) 2010 Broadcom
7556 + *
7557 + * This program is free software; you can redistribute it and/or modify
7558 + * it under the terms of the GNU General Public License as published by
7559 + * the Free Software Foundation; either version 2 of the License, or
7560 + * (at your option) any later version.
7561 + *
7562 + * This program is distributed in the hope that it will be useful,
7563 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7564 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7565 + * GNU General Public License for more details.
7566 + *
7567 + * You should have received a copy of the GNU General Public License
7568 + * along with this program; if not, write to the Free Software
7569 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7570 + */
7571 +
7572 +#define CLOCK_TICK_RATE (1000000)
7573 diff --git a/arch/arm/mach-bcm2709/include/mach/uncompress.h b/arch/arm/mach-bcm2709/include/mach/uncompress.h
7574 new file mode 100644
7575 index 0000000..d634813
7576 --- /dev/null
7577 +++ b/arch/arm/mach-bcm2709/include/mach/uncompress.h
7578 @@ -0,0 +1,84 @@
7579 +/*
7580 + * arch/arm/mach-bcn2708/include/mach/uncompress.h
7581 + *
7582 + * Copyright (C) 2010 Broadcom
7583 + * Copyright (C) 2003 ARM Limited
7584 + *
7585 + * This program is free software; you can redistribute it and/or modify
7586 + * it under the terms of the GNU General Public License as published by
7587 + * the Free Software Foundation; either version 2 of the License, or
7588 + * (at your option) any later version.
7589 + *
7590 + * This program is distributed in the hope that it will be useful,
7591 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7592 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7593 + * GNU General Public License for more details.
7594 + *
7595 + * You should have received a copy of the GNU General Public License
7596 + * along with this program; if not, write to the Free Software
7597 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7598 + */
7599 +
7600 +#include <linux/io.h>
7601 +#include <linux/amba/serial.h>
7602 +#include <mach/hardware.h>
7603 +
7604 +#define UART_BAUD 115200
7605 +
7606 +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
7607 +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
7608 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
7609 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
7610 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
7611 +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
7612 +
7613 +/*
7614 + * This does not append a newline
7615 + */
7616 +static inline void putc(int c)
7617 +{
7618 + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
7619 + barrier();
7620 +
7621 + __raw_writel(c, BCM2708_UART_DR);
7622 +}
7623 +
7624 +static inline void flush(void)
7625 +{
7626 + int fr;
7627 +
7628 + do {
7629 + fr = __raw_readl(BCM2708_UART_FR);
7630 + barrier();
7631 + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
7632 +}
7633 +
7634 +static inline void arch_decomp_setup(void)
7635 +{
7636 + int temp, div, rem, frac;
7637 +
7638 + temp = 16 * UART_BAUD;
7639 + div = UART0_CLOCK / temp;
7640 + rem = UART0_CLOCK % temp;
7641 + temp = (8 * rem) / UART_BAUD;
7642 + frac = (temp >> 1) + (temp & 1);
7643 +
7644 + /* Make sure the UART is disabled before we start */
7645 + __raw_writel(0, BCM2708_UART_CR);
7646 +
7647 + /* Set the baud rate */
7648 + __raw_writel(div, BCM2708_UART_IBRD);
7649 + __raw_writel(frac, BCM2708_UART_FBRD);
7650 +
7651 + /* Set the UART to 8n1, FIFO enabled */
7652 + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
7653 +
7654 + /* Enable the UART */
7655 + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
7656 + BCM2708_UART_CR);
7657 +}
7658 +
7659 +/*
7660 + * nothing to do
7661 + */
7662 +#define arch_decomp_wdog()
7663 diff --git a/arch/arm/mach-bcm2709/include/mach/vc_mem.h b/arch/arm/mach-bcm2709/include/mach/vc_mem.h
7664 new file mode 100644
7665 index 0000000..4a4a338
7666 --- /dev/null
7667 +++ b/arch/arm/mach-bcm2709/include/mach/vc_mem.h
7668 @@ -0,0 +1,35 @@
7669 +/*****************************************************************************
7670 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
7671 +*
7672 +* Unless you and Broadcom execute a separate written software license
7673 +* agreement governing use of this software, this software is licensed to you
7674 +* under the terms of the GNU General Public License version 2, available at
7675 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
7676 +*
7677 +* Notwithstanding the above, under no circumstances may you combine this
7678 +* software in any way with any other Broadcom software provided under a
7679 +* license other than the GPL, without Broadcom's express prior written
7680 +* consent.
7681 +*****************************************************************************/
7682 +
7683 +#if !defined( VC_MEM_H )
7684 +#define VC_MEM_H
7685 +
7686 +#include <linux/ioctl.h>
7687 +
7688 +#define VC_MEM_IOC_MAGIC 'v'
7689 +
7690 +#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
7691 +#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
7692 +#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
7693 +#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
7694 +
7695 +#if defined( __KERNEL__ )
7696 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
7697 +
7698 +extern unsigned long mm_vc_mem_phys_addr;
7699 +extern unsigned int mm_vc_mem_size;
7700 +extern int vc_mem_get_current_size( void );
7701 +#endif
7702 +
7703 +#endif /* VC_MEM_H */
7704 diff --git a/arch/arm/mach-bcm2709/include/mach/vc_support.h b/arch/arm/mach-bcm2709/include/mach/vc_support.h
7705 new file mode 100755
7706 index 0000000..70e809f
7707 --- /dev/null
7708 +++ b/arch/arm/mach-bcm2709/include/mach/vc_support.h
7709 @@ -0,0 +1,69 @@
7710 +#ifndef _VC_SUPPORT_H_
7711 +#define _VC_SUPPORT_H_
7712 +
7713 +/*
7714 + * vc_support.h
7715 + *
7716 + * Created on: 25 Nov 2012
7717 + * Author: Simon
7718 + */
7719 +
7720 +enum {
7721 +/*
7722 + If a MEM_HANDLE_T is discardable, the memory manager may resize it to size
7723 + 0 at any time when it is not locked or retained.
7724 + */
7725 + MEM_FLAG_DISCARDABLE = 1 << 0,
7726 +
7727 + /*
7728 + If a MEM_HANDLE_T is allocating (or normal), its block of memory will be
7729 + accessed in an allocating fashion through the cache.
7730 + */
7731 + MEM_FLAG_NORMAL = 0 << 2,
7732 + MEM_FLAG_ALLOCATING = MEM_FLAG_NORMAL,
7733 +
7734 + /*
7735 + If a MEM_HANDLE_T is direct, its block of memory will be accessed
7736 + directly, bypassing the cache.
7737 + */
7738 + MEM_FLAG_DIRECT = 1 << 2,
7739 +
7740 + /*
7741 + If a MEM_HANDLE_T is coherent, its block of memory will be accessed in a
7742 + non-allocating fashion through the cache.
7743 + */
7744 + MEM_FLAG_COHERENT = 2 << 2,
7745 +
7746 + /*
7747 + If a MEM_HANDLE_T is L1-nonallocating, its block of memory will be accessed by
7748 + the VPU in a fashion which is allocating in L2, but only coherent in L1.
7749 + */
7750 + MEM_FLAG_L1_NONALLOCATING = (MEM_FLAG_DIRECT | MEM_FLAG_COHERENT),
7751 +
7752 + /*
7753 + If a MEM_HANDLE_T is zero'd, its contents are set to 0 rather than
7754 + MEM_HANDLE_INVALID on allocation and resize up.
7755 + */
7756 + MEM_FLAG_ZERO = 1 << 4,
7757 +
7758 + /*
7759 + If a MEM_HANDLE_T is uninitialised, it will not be reset to a defined value
7760 + (either zero, or all 1's) on allocation.
7761 + */
7762 + MEM_FLAG_NO_INIT = 1 << 5,
7763 +
7764 + /*
7765 + Hints.
7766 + */
7767 + MEM_FLAG_HINT_PERMALOCK = 1 << 6, /* Likely to be locked for long periods of time. */
7768 +};
7769 +
7770 +unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags);
7771 +unsigned int ReleaseVcMemory(unsigned int handle);
7772 +unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle);
7773 +unsigned int UnlockVcMemory(unsigned int handle);
7774 +
7775 +unsigned int ExecuteVcCode(unsigned int code,
7776 + unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5);
7777 +
7778 +#endif
7779 diff --git a/arch/arm/mach-bcm2709/include/mach/vcio.h b/arch/arm/mach-bcm2709/include/mach/vcio.h
7780 new file mode 100644
7781 index 0000000..8e11d67
7782 --- /dev/null
7783 +++ b/arch/arm/mach-bcm2709/include/mach/vcio.h
7784 @@ -0,0 +1,165 @@
7785 +/*
7786 + * arch/arm/mach-bcm2708/include/mach/vcio.h
7787 + *
7788 + * Copyright (C) 2010 Broadcom
7789 + *
7790 + * This program is free software; you can redistribute it and/or modify
7791 + * it under the terms of the GNU General Public License as published by
7792 + * the Free Software Foundation; either version 2 of the License, or
7793 + * (at your option) any later version.
7794 + *
7795 + * This program is distributed in the hope that it will be useful,
7796 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7797 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7798 + * GNU General Public License for more details.
7799 + *
7800 + * You should have received a copy of the GNU General Public License
7801 + * along with this program; if not, write to the Free Software
7802 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7803 + */
7804 +#ifndef _MACH_BCM2708_VCIO_H
7805 +#define _MACH_BCM2708_VCIO_H
7806 +
7807 +/* Routines to handle I/O via the VideoCore "ARM control" registers
7808 + * (semaphores, doorbells, mailboxes)
7809 + */
7810 +
7811 +#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
7812 +
7813 +/* Constants shared with the ARM identifying separate mailbox channels */
7814 +#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
7815 +#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
7816 +#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
7817 +#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
7818 +#define MBOX_CHAN_COUNT 9
7819 +
7820 +enum {
7821 + VCMSG_PROCESS_REQUEST = 0x00000000
7822 +};
7823 +enum {
7824 + VCMSG_REQUEST_SUCCESSFUL = 0x80000000,
7825 + VCMSG_REQUEST_FAILED = 0x80000001
7826 +};
7827 +/* Mailbox property tags */
7828 +enum {
7829 + VCMSG_PROPERTY_END = 0x00000000,
7830 + VCMSG_GET_FIRMWARE_REVISION = 0x00000001,
7831 + VCMSG_GET_BOARD_MODEL = 0x00010001,
7832 + VCMSG_GET_BOARD_REVISION = 0x00010002,
7833 + VCMSG_GET_BOARD_MAC_ADDRESS = 0x00010003,
7834 + VCMSG_GET_BOARD_SERIAL = 0x00010004,
7835 + VCMSG_GET_ARM_MEMORY = 0x00010005,
7836 + VCMSG_GET_VC_MEMORY = 0x00010006,
7837 + VCMSG_GET_CLOCKS = 0x00010007,
7838 + VCMSG_GET_COMMAND_LINE = 0x00050001,
7839 + VCMSG_GET_DMA_CHANNELS = 0x00060001,
7840 + VCMSG_GET_POWER_STATE = 0x00020001,
7841 + VCMSG_GET_TIMING = 0x00020002,
7842 + VCMSG_SET_POWER_STATE = 0x00028001,
7843 + VCMSG_GET_CLOCK_STATE = 0x00030001,
7844 + VCMSG_SET_CLOCK_STATE = 0x00038001,
7845 + VCMSG_GET_CLOCK_RATE = 0x00030002,
7846 + VCMSG_SET_CLOCK_RATE = 0x00038002,
7847 + VCMSG_GET_VOLTAGE = 0x00030003,
7848 + VCMSG_SET_VOLTAGE = 0x00038003,
7849 + VCMSG_GET_MAX_CLOCK = 0x00030004,
7850 + VCMSG_GET_MAX_VOLTAGE = 0x00030005,
7851 + VCMSG_GET_TEMPERATURE = 0x00030006,
7852 + VCMSG_GET_MIN_CLOCK = 0x00030007,
7853 + VCMSG_GET_MIN_VOLTAGE = 0x00030008,
7854 + VCMSG_GET_TURBO = 0x00030009,
7855 + VCMSG_GET_MAX_TEMPERATURE = 0x0003000a,
7856 + VCMSG_GET_STC = 0x0003000b,
7857 + VCMSG_SET_TURBO = 0x00038009,
7858 + VCMSG_SET_ALLOCATE_MEM = 0x0003000c,
7859 + VCMSG_SET_LOCK_MEM = 0x0003000d,
7860 + VCMSG_SET_UNLOCK_MEM = 0x0003000e,
7861 + VCMSG_SET_RELEASE_MEM = 0x0003000f,
7862 + VCMSG_SET_EXECUTE_CODE = 0x00030010,
7863 + VCMSG_SET_EXECUTE_QPU = 0x00030011,
7864 + VCMSG_SET_ENABLE_QPU = 0x00030012,
7865 + VCMSG_GET_RESOURCE_HANDLE = 0x00030014,
7866 + VCMSG_GET_EDID_BLOCK = 0x00030020,
7867 + VCMSG_GET_CUSTOMER_OTP = 0x00030021,
7868 + VCMSG_SET_CUSTOMER_OTP = 0x00038021,
7869 + VCMSG_SET_ALLOCATE_BUFFER = 0x00040001,
7870 + VCMSG_SET_RELEASE_BUFFER = 0x00048001,
7871 + VCMSG_SET_BLANK_SCREEN = 0x00040002,
7872 + VCMSG_TST_BLANK_SCREEN = 0x00044002,
7873 + VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
7874 + VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
7875 + VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
7876 + VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
7877 + VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
7878 + VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
7879 + VCMSG_GET_DEPTH = 0x00040005,
7880 + VCMSG_TST_DEPTH = 0x00044005,
7881 + VCMSG_SET_DEPTH = 0x00048005,
7882 + VCMSG_GET_PIXEL_ORDER = 0x00040006,
7883 + VCMSG_TST_PIXEL_ORDER = 0x00044006,
7884 + VCMSG_SET_PIXEL_ORDER = 0x00048006,
7885 + VCMSG_GET_ALPHA_MODE = 0x00040007,
7886 + VCMSG_TST_ALPHA_MODE = 0x00044007,
7887 + VCMSG_SET_ALPHA_MODE = 0x00048007,
7888 + VCMSG_GET_PITCH = 0x00040008,
7889 + VCMSG_TST_PITCH = 0x00044008,
7890 + VCMSG_SET_PITCH = 0x00048008,
7891 + VCMSG_GET_VIRTUAL_OFFSET = 0x00040009,
7892 + VCMSG_TST_VIRTUAL_OFFSET = 0x00044009,
7893 + VCMSG_SET_VIRTUAL_OFFSET = 0x00048009,
7894 + VCMSG_GET_OVERSCAN = 0x0004000a,
7895 + VCMSG_TST_OVERSCAN = 0x0004400a,
7896 + VCMSG_SET_OVERSCAN = 0x0004800a,
7897 + VCMSG_GET_PALETTE = 0x0004000b,
7898 + VCMSG_TST_PALETTE = 0x0004400b,
7899 + VCMSG_SET_PALETTE = 0x0004800b,
7900 + VCMSG_GET_LAYER = 0x0004000c,
7901 + VCMSG_TST_LAYER = 0x0004400c,
7902 + VCMSG_SET_LAYER = 0x0004800c,
7903 + VCMSG_GET_TRANSFORM = 0x0004000d,
7904 + VCMSG_TST_TRANSFORM = 0x0004400d,
7905 + VCMSG_SET_TRANSFORM = 0x0004800d,
7906 + VCMSG_TST_VSYNC = 0x0004400e,
7907 + VCMSG_SET_VSYNC = 0x0004800e,
7908 + VCMSG_SET_CURSOR_INFO = 0x00008010,
7909 + VCMSG_SET_CURSOR_STATE = 0x00008011,
7910 +};
7911 +
7912 +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
7913 +extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
7914 +extern int /*rc*/ bcm_mailbox_property(void *data, int size);
7915 +
7916 +#include <linux/ioctl.h>
7917 +
7918 +/*
7919 + * The major device number. We can't rely on dynamic
7920 + * registration any more, because ioctls need to know
7921 + * it.
7922 + */
7923 +#define MAJOR_NUM 100
7924 +
7925 +/*
7926 + * Set the message of the device driver
7927 + */
7928 +#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
7929 +/*
7930 + * _IOWR means that we're creating an ioctl command
7931 + * number for passing information from a user process
7932 + * to the kernel module and from the kernel module to user process
7933 + *
7934 + * The first arguments, MAJOR_NUM, is the major device
7935 + * number we're using.
7936 + *
7937 + * The second argument is the number of the command
7938 + * (there could be several with different meanings).
7939 + *
7940 + * The third argument is the type we want to get from
7941 + * the process to the kernel.
7942 + */
7943 +
7944 +/*
7945 + * The name of the device file
7946 + */
7947 +#define DEVICE_FILE_NAME "vcio"
7948 +
7949 +#endif
7950 diff --git a/arch/arm/mach-bcm2709/include/mach/vmalloc.h b/arch/arm/mach-bcm2709/include/mach/vmalloc.h
7951 new file mode 100644
7952 index 0000000..6aa6826
7953 --- /dev/null
7954 +++ b/arch/arm/mach-bcm2709/include/mach/vmalloc.h
7955 @@ -0,0 +1,20 @@
7956 +/*
7957 + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
7958 + *
7959 + * Copyright (C) 2010 Broadcom
7960 + *
7961 + * This program is free software; you can redistribute it and/or modify
7962 + * it under the terms of the GNU General Public License as published by
7963 + * the Free Software Foundation; either version 2 of the License, or
7964 + * (at your option) any later version.
7965 + *
7966 + * This program is distributed in the hope that it will be useful,
7967 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7968 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7969 + * GNU General Public License for more details.
7970 + *
7971 + * You should have received a copy of the GNU General Public License
7972 + * along with this program; if not, write to the Free Software
7973 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
7974 + */
7975 +#define VMALLOC_END (0xff000000)
7976 diff --git a/arch/arm/mach-bcm2709/power.c b/arch/arm/mach-bcm2709/power.c
7977 new file mode 100644
7978 index 0000000..3421057
7979 --- /dev/null
7980 +++ b/arch/arm/mach-bcm2709/power.c
7981 @@ -0,0 +1,195 @@
7982 +/*
7983 + * linux/arch/arm/mach-bcm2708/power.c
7984 + *
7985 + * Copyright (C) 2010 Broadcom
7986 + *
7987 + * This program is free software; you can redistribute it and/or modify
7988 + * it under the terms of the GNU General Public License version 2 as
7989 + * published by the Free Software Foundation.
7990 + *
7991 + * This device provides a shared mechanism for controlling the power to
7992 + * VideoCore subsystems.
7993 + */
7994 +
7995 +#include <linux/module.h>
7996 +#include <linux/semaphore.h>
7997 +#include <linux/bug.h>
7998 +#include <mach/power.h>
7999 +#include <mach/vcio.h>
8000 +#include <mach/arm_power.h>
8001 +
8002 +#define DRIVER_NAME "bcm2708_power"
8003 +
8004 +#define BCM_POWER_MAXCLIENTS 4
8005 +#define BCM_POWER_NOCLIENT (1<<31)
8006 +
8007 +/* Some drivers expect there devices to be permanently powered */
8008 +#ifdef CONFIG_USB
8009 +#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
8010 +#endif
8011 +
8012 +#if 1
8013 +#define DPRINTK printk
8014 +#else
8015 +#define DPRINTK if (0) printk
8016 +#endif
8017 +
8018 +struct state_struct {
8019 + uint32_t global_request;
8020 + uint32_t client_request[BCM_POWER_MAXCLIENTS];
8021 + struct semaphore client_mutex;
8022 + struct semaphore mutex;
8023 +} g_state;
8024 +
8025 +int bcm_power_open(BCM_POWER_HANDLE_T *handle)
8026 +{
8027 + BCM_POWER_HANDLE_T i;
8028 + int ret = -EBUSY;
8029 +
8030 + down(&g_state.client_mutex);
8031 +
8032 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
8033 + if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
8034 + g_state.client_request[i] = BCM_POWER_NONE;
8035 + *handle = i;
8036 + ret = 0;
8037 + break;
8038 + }
8039 + }
8040 +
8041 + up(&g_state.client_mutex);
8042 +
8043 + DPRINTK("bcm_power_open() -> %d\n", *handle);
8044 +
8045 + return ret;
8046 +}
8047 +EXPORT_SYMBOL_GPL(bcm_power_open);
8048 +
8049 +int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
8050 +{
8051 + int rc = 0;
8052 +
8053 + DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
8054 +
8055 + if ((handle < BCM_POWER_MAXCLIENTS) &&
8056 + (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
8057 + if (down_interruptible(&g_state.mutex) != 0) {
8058 + DPRINTK("bcm_power_request -> interrupted\n");
8059 + return -EINTR;
8060 + }
8061 +
8062 + if (request != g_state.client_request[handle]) {
8063 + uint32_t others_request = 0;
8064 + uint32_t global_request;
8065 + BCM_POWER_HANDLE_T i;
8066 +
8067 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
8068 + if (i != handle)
8069 + others_request |=
8070 + g_state.client_request[i];
8071 + }
8072 + others_request &= ~BCM_POWER_NOCLIENT;
8073 +
8074 + global_request = request | others_request;
8075 + if (global_request != g_state.global_request) {
8076 + uint32_t actual;
8077 +
8078 + /* Send a request to VideoCore */
8079 + bcm_mailbox_write(MBOX_CHAN_POWER,
8080 + global_request << 4);
8081 +
8082 + /* Wait for a response during power-up */
8083 + if (global_request & ~g_state.global_request) {
8084 + rc = bcm_mailbox_read(MBOX_CHAN_POWER,
8085 + &actual);
8086 + DPRINTK
8087 + ("bcm_mailbox_read -> %08x, %d\n",
8088 + actual, rc);
8089 + actual >>= 4;
8090 + } else {
8091 + rc = 0;
8092 + actual = global_request;
8093 + }
8094 +
8095 + if (rc == 0) {
8096 + if (actual != global_request) {
8097 + printk(KERN_ERR
8098 + "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
8099 + __func__,
8100 + g_state.global_request,
8101 + global_request, actual, request, others_request);
8102 + /* A failure */
8103 + BUG_ON((others_request & actual)
8104 + != others_request);
8105 + request &= actual;
8106 + rc = -EIO;
8107 + }
8108 +
8109 + g_state.global_request = actual;
8110 + g_state.client_request[handle] =
8111 + request;
8112 + }
8113 + }
8114 + }
8115 + up(&g_state.mutex);
8116 + } else {
8117 + rc = -EINVAL;
8118 + }
8119 + DPRINTK("bcm_power_request -> %d\n", rc);
8120 + return rc;
8121 +}
8122 +EXPORT_SYMBOL_GPL(bcm_power_request);
8123 +
8124 +int bcm_power_close(BCM_POWER_HANDLE_T handle)
8125 +{
8126 + int rc;
8127 +
8128 + DPRINTK("bcm_power_close(%d)\n", handle);
8129 +
8130 + rc = bcm_power_request(handle, BCM_POWER_NONE);
8131 + if (rc == 0)
8132 + g_state.client_request[handle] = BCM_POWER_NOCLIENT;
8133 +
8134 + return rc;
8135 +}
8136 +EXPORT_SYMBOL_GPL(bcm_power_close);
8137 +
8138 +static int __init bcm_power_init(void)
8139 +{
8140 +#if defined(BCM_POWER_ALWAYS_ON)
8141 + BCM_POWER_HANDLE_T always_on_handle;
8142 +#endif
8143 + int rc = 0;
8144 + int i;
8145 +
8146 + printk(KERN_INFO "bcm_power: Broadcom power driver\n");
8147 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
8148 +
8149 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
8150 + g_state.client_request[i] = BCM_POWER_NOCLIENT;
8151 +
8152 + sema_init(&g_state.client_mutex, 1);
8153 + sema_init(&g_state.mutex, 1);
8154 +
8155 + g_state.global_request = 0;
8156 +#if defined(BCM_POWER_ALWAYS_ON)
8157 + if (BCM_POWER_ALWAYS_ON) {
8158 + bcm_power_open(&always_on_handle);
8159 + bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
8160 + }
8161 +#endif
8162 +
8163 + return rc;
8164 +}
8165 +
8166 +static void __exit bcm_power_exit(void)
8167 +{
8168 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
8169 +}
8170 +
8171 +arch_initcall(bcm_power_init); /* Initialize early */
8172 +module_exit(bcm_power_exit);
8173 +
8174 +MODULE_AUTHOR("Phil Elwell");
8175 +MODULE_DESCRIPTION("Interface to BCM2708 power management");
8176 +MODULE_LICENSE("GPL");
8177 diff --git a/arch/arm/mach-bcm2709/vc_mem.c b/arch/arm/mach-bcm2709/vc_mem.c
8178 new file mode 100644
8179 index 0000000..ac578db
8180 --- /dev/null
8181 +++ b/arch/arm/mach-bcm2709/vc_mem.c
8182 @@ -0,0 +1,431 @@
8183 +/*****************************************************************************
8184 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
8185 +*
8186 +* Unless you and Broadcom execute a separate written software license
8187 +* agreement governing use of this software, this software is licensed to you
8188 +* under the terms of the GNU General Public License version 2, available at
8189 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8190 +*
8191 +* Notwithstanding the above, under no circumstances may you combine this
8192 +* software in any way with any other Broadcom software provided under a
8193 +* license other than the GPL, without Broadcom's express prior written
8194 +* consent.
8195 +*****************************************************************************/
8196 +
8197 +#include <linux/kernel.h>
8198 +#include <linux/module.h>
8199 +#include <linux/fs.h>
8200 +#include <linux/device.h>
8201 +#include <linux/cdev.h>
8202 +#include <linux/mm.h>
8203 +#include <linux/slab.h>
8204 +#include <linux/debugfs.h>
8205 +#include <asm/uaccess.h>
8206 +#include <linux/dma-mapping.h>
8207 +
8208 +#ifdef CONFIG_ARCH_KONA
8209 +#include <chal/chal_ipc.h>
8210 +#elif defined(CONFIG_ARCH_BCM2708) || defined(CONFIG_ARCH_BCM2709)
8211 +#else
8212 +#include <csp/chal_ipc.h>
8213 +#endif
8214 +
8215 +#include "mach/vc_mem.h"
8216 +#include <mach/vcio.h>
8217 +
8218 +#define DRIVER_NAME "vc-mem"
8219 +
8220 +// Device (/dev) related variables
8221 +static dev_t vc_mem_devnum = 0;
8222 +static struct class *vc_mem_class = NULL;
8223 +static struct cdev vc_mem_cdev;
8224 +static int vc_mem_inited = 0;
8225 +
8226 +#ifdef CONFIG_DEBUG_FS
8227 +static struct dentry *vc_mem_debugfs_entry;
8228 +#endif
8229 +
8230 +/*
8231 + * Videocore memory addresses and size
8232 + *
8233 + * Drivers that wish to know the videocore memory addresses and sizes should
8234 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
8235 + * headers. This allows the other drivers to not be tied down to a a certain
8236 + * address/size at compile time.
8237 + *
8238 + * In the future, the goal is to have the videocore memory virtual address and
8239 + * size be calculated at boot time rather than at compile time. The decision of
8240 + * where the videocore memory resides and its size would be in the hands of the
8241 + * bootloader (and/or kernel). When that happens, the values of these variables
8242 + * would be calculated and assigned in the init function.
8243 + */
8244 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
8245 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
8246 +unsigned int mm_vc_mem_size = 0;
8247 +unsigned int mm_vc_mem_base = 0;
8248 +
8249 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
8250 +EXPORT_SYMBOL(mm_vc_mem_size);
8251 +EXPORT_SYMBOL(mm_vc_mem_base);
8252 +
8253 +static uint phys_addr = 0;
8254 +static uint mem_size = 0;
8255 +static uint mem_base = 0;
8256 +
8257 +
8258 +/****************************************************************************
8259 +*
8260 +* vc_mem_open
8261 +*
8262 +***************************************************************************/
8263 +
8264 +static int
8265 +vc_mem_open(struct inode *inode, struct file *file)
8266 +{
8267 + (void) inode;
8268 + (void) file;
8269 +
8270 + pr_debug("%s: called file = 0x%p\n", __func__, file);
8271 +
8272 + return 0;
8273 +}
8274 +
8275 +/****************************************************************************
8276 +*
8277 +* vc_mem_release
8278 +*
8279 +***************************************************************************/
8280 +
8281 +static int
8282 +vc_mem_release(struct inode *inode, struct file *file)
8283 +{
8284 + (void) inode;
8285 + (void) file;
8286 +
8287 + pr_debug("%s: called file = 0x%p\n", __func__, file);
8288 +
8289 + return 0;
8290 +}
8291 +
8292 +/****************************************************************************
8293 +*
8294 +* vc_mem_get_size
8295 +*
8296 +***************************************************************************/
8297 +
8298 +static void
8299 +vc_mem_get_size(void)
8300 +{
8301 +}
8302 +
8303 +/****************************************************************************
8304 +*
8305 +* vc_mem_get_base
8306 +*
8307 +***************************************************************************/
8308 +
8309 +static void
8310 +vc_mem_get_base(void)
8311 +{
8312 +}
8313 +
8314 +/****************************************************************************
8315 +*
8316 +* vc_mem_get_current_size
8317 +*
8318 +***************************************************************************/
8319 +
8320 +int
8321 +vc_mem_get_current_size(void)
8322 +{
8323 + return mm_vc_mem_size;
8324 +}
8325 +
8326 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
8327 +
8328 +/****************************************************************************
8329 +*
8330 +* vc_mem_ioctl
8331 +*
8332 +***************************************************************************/
8333 +
8334 +static long
8335 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
8336 +{
8337 + int rc = 0;
8338 +
8339 + (void) cmd;
8340 + (void) arg;
8341 +
8342 + pr_debug("%s: called file = 0x%p\n", __func__, file);
8343 +
8344 + switch (cmd) {
8345 + case VC_MEM_IOC_MEM_PHYS_ADDR:
8346 + {
8347 + pr_debug("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p\n",
8348 + __func__, (void *) mm_vc_mem_phys_addr);
8349 +
8350 + if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
8351 + sizeof (mm_vc_mem_phys_addr)) != 0) {
8352 + rc = -EFAULT;
8353 + }
8354 + break;
8355 + }
8356 + case VC_MEM_IOC_MEM_SIZE:
8357 + {
8358 + // Get the videocore memory size first
8359 + vc_mem_get_size();
8360 +
8361 + pr_debug("%s: VC_MEM_IOC_MEM_SIZE=%u\n", __func__,
8362 + mm_vc_mem_size);
8363 +
8364 + if (copy_to_user((void *) arg, &mm_vc_mem_size,
8365 + sizeof (mm_vc_mem_size)) != 0) {
8366 + rc = -EFAULT;
8367 + }
8368 + break;
8369 + }
8370 + case VC_MEM_IOC_MEM_BASE:
8371 + {
8372 + // Get the videocore memory base
8373 + vc_mem_get_base();
8374 +
8375 + pr_debug("%s: VC_MEM_IOC_MEM_BASE=%u\n", __func__,
8376 + mm_vc_mem_base);
8377 +
8378 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
8379 + sizeof (mm_vc_mem_base)) != 0) {
8380 + rc = -EFAULT;
8381 + }
8382 + break;
8383 + }
8384 + case VC_MEM_IOC_MEM_LOAD:
8385 + {
8386 + // Get the videocore memory base
8387 + vc_mem_get_base();
8388 +
8389 + pr_debug("%s: VC_MEM_IOC_MEM_LOAD=%u\n", __func__,
8390 + mm_vc_mem_base);
8391 +
8392 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
8393 + sizeof (mm_vc_mem_base)) != 0) {
8394 + rc = -EFAULT;
8395 + }
8396 + break;
8397 + }
8398 + default:
8399 + {
8400 + return -ENOTTY;
8401 + }
8402 + }
8403 + pr_debug("%s: file = 0x%p returning %d\n", __func__, file, rc);
8404 +
8405 + return rc;
8406 +}
8407 +
8408 +/****************************************************************************
8409 +*
8410 +* vc_mem_mmap
8411 +*
8412 +***************************************************************************/
8413 +
8414 +static int
8415 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
8416 +{
8417 + int rc = 0;
8418 + unsigned long length = vma->vm_end - vma->vm_start;
8419 + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
8420 +
8421 + pr_debug("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx\n",
8422 + __func__, (long) vma->vm_start, (long) vma->vm_end,
8423 + (long) vma->vm_pgoff);
8424 +
8425 + if (offset + length > mm_vc_mem_size) {
8426 + pr_err("%s: length %ld is too big\n", __func__, length);
8427 + return -EINVAL;
8428 + }
8429 + // Do not cache the memory map
8430 + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
8431 +
8432 + rc = remap_pfn_range(vma, vma->vm_start,
8433 + (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
8434 + vma->vm_pgoff, length, vma->vm_page_prot);
8435 + if (rc != 0) {
8436 + pr_err("%s: remap_pfn_range failed (rc=%d)\n", __func__, rc);
8437 + }
8438 +
8439 + return rc;
8440 +}
8441 +
8442 +/****************************************************************************
8443 +*
8444 +* File Operations for the driver.
8445 +*
8446 +***************************************************************************/
8447 +
8448 +static const struct file_operations vc_mem_fops = {
8449 + .owner = THIS_MODULE,
8450 + .open = vc_mem_open,
8451 + .release = vc_mem_release,
8452 + .unlocked_ioctl = vc_mem_ioctl,
8453 + .mmap = vc_mem_mmap,
8454 +};
8455 +
8456 +#ifdef CONFIG_DEBUG_FS
8457 +static void vc_mem_debugfs_deinit(void)
8458 +{
8459 + debugfs_remove_recursive(vc_mem_debugfs_entry);
8460 + vc_mem_debugfs_entry = NULL;
8461 +}
8462 +
8463 +
8464 +static int vc_mem_debugfs_init(
8465 + struct device *dev)
8466 +{
8467 + vc_mem_debugfs_entry = debugfs_create_dir(DRIVER_NAME, NULL);
8468 + if (!vc_mem_debugfs_entry) {
8469 + dev_warn(dev, "could not create debugfs entry\n");
8470 + return -EFAULT;
8471 + }
8472 +
8473 + if (!debugfs_create_x32("vc_mem_phys_addr",
8474 + 0444,
8475 + vc_mem_debugfs_entry,
8476 + (u32 *)&mm_vc_mem_phys_addr)) {
8477 + dev_warn(dev, "%s:could not create vc_mem_phys entry\n",
8478 + __func__);
8479 + goto fail;
8480 + }
8481 +
8482 + if (!debugfs_create_x32("vc_mem_size",
8483 + 0444,
8484 + vc_mem_debugfs_entry,
8485 + (u32 *)&mm_vc_mem_size)) {
8486 + dev_warn(dev, "%s:could not create vc_mem_size entry\n",
8487 + __func__);
8488 + goto fail;
8489 + }
8490 +
8491 + if (!debugfs_create_x32("vc_mem_base",
8492 + 0444,
8493 + vc_mem_debugfs_entry,
8494 + (u32 *)&mm_vc_mem_base)) {
8495 + dev_warn(dev, "%s:could not create vc_mem_base entry\n",
8496 + __func__);
8497 + goto fail;
8498 + }
8499 +
8500 + return 0;
8501 +
8502 +fail:
8503 + vc_mem_debugfs_deinit();
8504 + return -EFAULT;
8505 +}
8506 +
8507 +#endif /* CONFIG_DEBUG_FS */
8508 +
8509 +
8510 +/****************************************************************************
8511 +*
8512 +* vc_mem_init
8513 +*
8514 +***************************************************************************/
8515 +
8516 +static int __init
8517 +vc_mem_init(void)
8518 +{
8519 + int rc = -EFAULT;
8520 + struct device *dev;
8521 +
8522 + pr_debug("%s: called\n", __func__);
8523 +
8524 + mm_vc_mem_phys_addr = phys_addr;
8525 + mm_vc_mem_size = mem_size;
8526 + mm_vc_mem_base = mem_base;
8527 +
8528 + vc_mem_get_size();
8529 +
8530 + pr_info("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
8531 + mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
8532 +
8533 + if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
8534 + pr_err("%s: alloc_chrdev_region failed (rc=%d)\n",
8535 + __func__, rc);
8536 + goto out_err;
8537 + }
8538 +
8539 + cdev_init(&vc_mem_cdev, &vc_mem_fops);
8540 + if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
8541 + pr_err("%s: cdev_add failed (rc=%d)\n", __func__, rc);
8542 + goto out_unregister;
8543 + }
8544 +
8545 + vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
8546 + if (IS_ERR(vc_mem_class)) {
8547 + rc = PTR_ERR(vc_mem_class);
8548 + pr_err("%s: class_create failed (rc=%d)\n", __func__, rc);
8549 + goto out_cdev_del;
8550 + }
8551 +
8552 + dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
8553 + DRIVER_NAME);
8554 + if (IS_ERR(dev)) {
8555 + rc = PTR_ERR(dev);
8556 + pr_err("%s: device_create failed (rc=%d)\n", __func__, rc);
8557 + goto out_class_destroy;
8558 + }
8559 +
8560 +#ifdef CONFIG_DEBUG_FS
8561 + /* don't fail if the debug entries cannot be created */
8562 + vc_mem_debugfs_init(dev);
8563 +#endif
8564 +
8565 + vc_mem_inited = 1;
8566 + return 0;
8567 +
8568 + device_destroy(vc_mem_class, vc_mem_devnum);
8569 +
8570 + out_class_destroy:
8571 + class_destroy(vc_mem_class);
8572 + vc_mem_class = NULL;
8573 +
8574 + out_cdev_del:
8575 + cdev_del(&vc_mem_cdev);
8576 +
8577 + out_unregister:
8578 + unregister_chrdev_region(vc_mem_devnum, 1);
8579 +
8580 + out_err:
8581 + return -1;
8582 +}
8583 +
8584 +/****************************************************************************
8585 +*
8586 +* vc_mem_exit
8587 +*
8588 +***************************************************************************/
8589 +
8590 +static void __exit
8591 +vc_mem_exit(void)
8592 +{
8593 + pr_debug("%s: called\n", __func__);
8594 +
8595 + if (vc_mem_inited) {
8596 +#if CONFIG_DEBUG_FS
8597 + vc_mem_debugfs_deinit();
8598 +#endif
8599 + device_destroy(vc_mem_class, vc_mem_devnum);
8600 + class_destroy(vc_mem_class);
8601 + cdev_del(&vc_mem_cdev);
8602 + unregister_chrdev_region(vc_mem_devnum, 1);
8603 + }
8604 +}
8605 +
8606 +module_init(vc_mem_init);
8607 +module_exit(vc_mem_exit);
8608 +MODULE_LICENSE("GPL");
8609 +MODULE_AUTHOR("Broadcom Corporation");
8610 +
8611 +module_param(phys_addr, uint, 0644);
8612 +module_param(mem_size, uint, 0644);
8613 +module_param(mem_base, uint, 0644);
8614 diff --git a/arch/arm/mach-bcm2709/vc_support.c b/arch/arm/mach-bcm2709/vc_support.c
8615 new file mode 100755
8616 index 0000000..0bc41c4
8617 --- /dev/null
8618 +++ b/arch/arm/mach-bcm2709/vc_support.c
8619 @@ -0,0 +1,318 @@
8620 +/*
8621 + * vc_support.c
8622 + *
8623 + * Created on: 25 Nov 2012
8624 + * Author: Simon
8625 + */
8626 +
8627 +#include <linux/module.h>
8628 +#include <mach/vcio.h>
8629 +
8630 +#ifdef ECLIPSE_IGNORE
8631 +
8632 +#define __user
8633 +#define __init
8634 +#define __exit
8635 +#define __iomem
8636 +#define KERN_DEBUG
8637 +#define KERN_ERR
8638 +#define KERN_WARNING
8639 +#define KERN_INFO
8640 +#define _IOWR(a, b, c) b
8641 +#define _IOW(a, b, c) b
8642 +#define _IO(a, b) b
8643 +
8644 +#endif
8645 +
8646 +/****** VC MAILBOX FUNCTIONALITY ******/
8647 +unsigned int AllocateVcMemory(unsigned int *pHandle, unsigned int size, unsigned int alignment, unsigned int flags)
8648 +{
8649 + struct vc_msg
8650 + {
8651 + unsigned int m_msgSize;
8652 + unsigned int m_response;
8653 +
8654 + struct vc_tag
8655 + {
8656 + unsigned int m_tagId;
8657 + unsigned int m_sendBufferSize;
8658 + union {
8659 + unsigned int m_sendDataSize;
8660 + unsigned int m_recvDataSize;
8661 + };
8662 +
8663 + struct args
8664 + {
8665 + union {
8666 + unsigned int m_size;
8667 + unsigned int m_handle;
8668 + };
8669 + unsigned int m_alignment;
8670 + unsigned int m_flags;
8671 + } m_args;
8672 + } m_tag;
8673 +
8674 + unsigned int m_endTag;
8675 + } msg;
8676 + int s;
8677 +
8678 + msg.m_msgSize = sizeof(msg);
8679 + msg.m_response = 0;
8680 + msg.m_endTag = 0;
8681 +
8682 + //fill in the tag for the allocation command
8683 + msg.m_tag.m_tagId = 0x3000c;
8684 + msg.m_tag.m_sendBufferSize = 12;
8685 + msg.m_tag.m_sendDataSize = 12;
8686 +
8687 + //fill in our args
8688 + msg.m_tag.m_args.m_size = size;
8689 + msg.m_tag.m_args.m_alignment = alignment;
8690 + msg.m_tag.m_args.m_flags = flags;
8691 +
8692 + //run the command
8693 + s = bcm_mailbox_property(&msg, sizeof(msg));
8694 +
8695 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8696 + {
8697 + *pHandle = msg.m_tag.m_args.m_handle;
8698 + return 0;
8699 + }
8700 + else
8701 + {
8702 + printk(KERN_ERR "failed to allocate vc memory: s=%d response=%08x recv data size=%08x\n",
8703 + s, msg.m_response, msg.m_tag.m_recvDataSize);
8704 + return 1;
8705 + }
8706 +}
8707 +
8708 +unsigned int ReleaseVcMemory(unsigned int handle)
8709 +{
8710 + struct vc_msg
8711 + {
8712 + unsigned int m_msgSize;
8713 + unsigned int m_response;
8714 +
8715 + struct vc_tag
8716 + {
8717 + unsigned int m_tagId;
8718 + unsigned int m_sendBufferSize;
8719 + union {
8720 + unsigned int m_sendDataSize;
8721 + unsigned int m_recvDataSize;
8722 + };
8723 +
8724 + struct args
8725 + {
8726 + union {
8727 + unsigned int m_handle;
8728 + unsigned int m_error;
8729 + };
8730 + } m_args;
8731 + } m_tag;
8732 +
8733 + unsigned int m_endTag;
8734 + } msg;
8735 + int s;
8736 +
8737 + msg.m_msgSize = sizeof(msg);
8738 + msg.m_response = 0;
8739 + msg.m_endTag = 0;
8740 +
8741 + //fill in the tag for the release command
8742 + msg.m_tag.m_tagId = 0x3000f;
8743 + msg.m_tag.m_sendBufferSize = 4;
8744 + msg.m_tag.m_sendDataSize = 4;
8745 +
8746 + //pass across the handle
8747 + msg.m_tag.m_args.m_handle = handle;
8748 +
8749 + s = bcm_mailbox_property(&msg, sizeof(msg));
8750 +
8751 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
8752 + return 0;
8753 + else
8754 + {
8755 + printk(KERN_ERR "failed to release vc memory: s=%d response=%08x recv data size=%08x error=%08x\n",
8756 + s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
8757 + return 1;
8758 + }
8759 +}
8760 +
8761 +unsigned int LockVcMemory(unsigned int *pBusAddress, unsigned int handle)
8762 +{
8763 + struct vc_msg
8764 + {
8765 + unsigned int m_msgSize;
8766 + unsigned int m_response;
8767 +
8768 + struct vc_tag
8769 + {
8770 + unsigned int m_tagId;
8771 + unsigned int m_sendBufferSize;
8772 + union {
8773 + unsigned int m_sendDataSize;
8774 + unsigned int m_recvDataSize;
8775 + };
8776 +
8777 + struct args
8778 + {
8779 + union {
8780 + unsigned int m_handle;
8781 + unsigned int m_busAddress;
8782 + };
8783 + } m_args;
8784 + } m_tag;
8785 +
8786 + unsigned int m_endTag;
8787 + } msg;
8788 + int s;
8789 +
8790 + msg.m_msgSize = sizeof(msg);
8791 + msg.m_response = 0;
8792 + msg.m_endTag = 0;
8793 +
8794 + //fill in the tag for the lock command
8795 + msg.m_tag.m_tagId = 0x3000d;
8796 + msg.m_tag.m_sendBufferSize = 4;
8797 + msg.m_tag.m_sendDataSize = 4;
8798 +
8799 + //pass across the handle
8800 + msg.m_tag.m_args.m_handle = handle;
8801 +
8802 + s = bcm_mailbox_property(&msg, sizeof(msg));
8803 +
8804 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8805 + {
8806 + //pick out the bus address
8807 + *pBusAddress = msg.m_tag.m_args.m_busAddress;
8808 + return 0;
8809 + }
8810 + else
8811 + {
8812 + printk(KERN_ERR "failed to lock vc memory: s=%d response=%08x recv data size=%08x\n",
8813 + s, msg.m_response, msg.m_tag.m_recvDataSize);
8814 + return 1;
8815 + }
8816 +}
8817 +
8818 +unsigned int UnlockVcMemory(unsigned int handle)
8819 +{
8820 + struct vc_msg
8821 + {
8822 + unsigned int m_msgSize;
8823 + unsigned int m_response;
8824 +
8825 + struct vc_tag
8826 + {
8827 + unsigned int m_tagId;
8828 + unsigned int m_sendBufferSize;
8829 + union {
8830 + unsigned int m_sendDataSize;
8831 + unsigned int m_recvDataSize;
8832 + };
8833 +
8834 + struct args
8835 + {
8836 + union {
8837 + unsigned int m_handle;
8838 + unsigned int m_error;
8839 + };
8840 + } m_args;
8841 + } m_tag;
8842 +
8843 + unsigned int m_endTag;
8844 + } msg;
8845 + int s;
8846 +
8847 + msg.m_msgSize = sizeof(msg);
8848 + msg.m_response = 0;
8849 + msg.m_endTag = 0;
8850 +
8851 + //fill in the tag for the unlock command
8852 + msg.m_tag.m_tagId = 0x3000e;
8853 + msg.m_tag.m_sendBufferSize = 4;
8854 + msg.m_tag.m_sendDataSize = 4;
8855 +
8856 + //pass across the handle
8857 + msg.m_tag.m_args.m_handle = handle;
8858 +
8859 + s = bcm_mailbox_property(&msg, sizeof(msg));
8860 +
8861 + //check the error code too
8862 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004 && msg.m_tag.m_args.m_error == 0)
8863 + return 0;
8864 + else
8865 + {
8866 + printk(KERN_ERR "failed to unlock vc memory: s=%d response=%08x recv data size=%08x error%08x\n",
8867 + s, msg.m_response, msg.m_tag.m_recvDataSize, msg.m_tag.m_args.m_error);
8868 + return 1;
8869 + }
8870 +}
8871 +
8872 +unsigned int ExecuteVcCode(unsigned int code,
8873 + unsigned int r0, unsigned int r1, unsigned int r2, unsigned int r3, unsigned int r4, unsigned int r5)
8874 +{
8875 + struct vc_msg
8876 + {
8877 + unsigned int m_msgSize;
8878 + unsigned int m_response;
8879 +
8880 + struct vc_tag
8881 + {
8882 + unsigned int m_tagId;
8883 + unsigned int m_sendBufferSize;
8884 + union {
8885 + unsigned int m_sendDataSize;
8886 + unsigned int m_recvDataSize;
8887 + };
8888 +
8889 + struct args
8890 + {
8891 + union {
8892 + unsigned int m_pCode;
8893 + unsigned int m_return;
8894 + };
8895 + unsigned int m_r0;
8896 + unsigned int m_r1;
8897 + unsigned int m_r2;
8898 + unsigned int m_r3;
8899 + unsigned int m_r4;
8900 + unsigned int m_r5;
8901 + } m_args;
8902 + } m_tag;
8903 +
8904 + unsigned int m_endTag;
8905 + } msg;
8906 + int s;
8907 +
8908 + msg.m_msgSize = sizeof(msg);
8909 + msg.m_response = 0;
8910 + msg.m_endTag = 0;
8911 +
8912 + //fill in the tag for the unlock command
8913 + msg.m_tag.m_tagId = 0x30010;
8914 + msg.m_tag.m_sendBufferSize = 28;
8915 + msg.m_tag.m_sendDataSize = 28;
8916 +
8917 + //pass across the handle
8918 + msg.m_tag.m_args.m_pCode = code;
8919 + msg.m_tag.m_args.m_r0 = r0;
8920 + msg.m_tag.m_args.m_r1 = r1;
8921 + msg.m_tag.m_args.m_r2 = r2;
8922 + msg.m_tag.m_args.m_r3 = r3;
8923 + msg.m_tag.m_args.m_r4 = r4;
8924 + msg.m_tag.m_args.m_r5 = r5;
8925 +
8926 + s = bcm_mailbox_property(&msg, sizeof(msg));
8927 +
8928 + //check the error code too
8929 + if (s == 0 && msg.m_response == 0x80000000 && msg.m_tag.m_recvDataSize == 0x80000004)
8930 + return msg.m_tag.m_args.m_return;
8931 + else
8932 + {
8933 + printk(KERN_ERR "failed to execute: s=%d response=%08x recv data size=%08x\n",
8934 + s, msg.m_response, msg.m_tag.m_recvDataSize);
8935 + return 1;
8936 + }
8937 +}
8938 diff --git a/arch/arm/mach-bcm2709/vcio.c b/arch/arm/mach-bcm2709/vcio.c
8939 new file mode 100644
8940 index 0000000..5e43e85
8941 --- /dev/null
8942 +++ b/arch/arm/mach-bcm2709/vcio.c
8943 @@ -0,0 +1,474 @@
8944 +/*
8945 + * linux/arch/arm/mach-bcm2708/vcio.c
8946 + *
8947 + * Copyright (C) 2010 Broadcom
8948 + *
8949 + * This program is free software; you can redistribute it and/or modify
8950 + * it under the terms of the GNU General Public License version 2 as
8951 + * published by the Free Software Foundation.
8952 + *
8953 + * This device provides a shared mechanism for writing to the mailboxes,
8954 + * semaphores, doorbells etc. that are shared between the ARM and the
8955 + * VideoCore processor
8956 + */
8957 +
8958 +#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
8959 +#define SUPPORT_SYSRQ
8960 +#endif
8961 +
8962 +#include <linux/module.h>
8963 +#include <linux/console.h>
8964 +#include <linux/serial_core.h>
8965 +#include <linux/serial.h>
8966 +#include <linux/errno.h>
8967 +#include <linux/device.h>
8968 +#include <linux/init.h>
8969 +#include <linux/mm.h>
8970 +#include <linux/dma-mapping.h>
8971 +#include <linux/platform_device.h>
8972 +#include <linux/sysrq.h>
8973 +#include <linux/delay.h>
8974 +#include <linux/slab.h>
8975 +#include <linux/interrupt.h>
8976 +#include <linux/irq.h>
8977 +
8978 +#include <linux/io.h>
8979 +
8980 +#include <mach/vcio.h>
8981 +#include <mach/platform.h>
8982 +
8983 +#include <asm/uaccess.h>
8984 +
8985 +
8986 +#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
8987 +
8988 +/* ----------------------------------------------------------------------
8989 + * Mailbox
8990 + * -------------------------------------------------------------------- */
8991 +
8992 +/* offsets from a mail box base address */
8993 +#define MAIL_WRT 0x00 /* write - and next 4 words */
8994 +#define MAIL_RD 0x00 /* read - and next 4 words */
8995 +#define MAIL_POL 0x10 /* read without popping the fifo */
8996 +#define MAIL_SND 0x14 /* sender ID (bottom two bits) */
8997 +#define MAIL_STA 0x18 /* status */
8998 +#define MAIL_CNF 0x1C /* configuration */
8999 +
9000 +#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf))
9001 +#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
9002 +#define MBOX_CHAN(msg) ((msg) & 0xf)
9003 +#define MBOX_DATA28(msg) ((msg) & ~0xf)
9004 +#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4)
9005 +
9006 +#define MBOX_MAGIC 0xd0d0c0de
9007 +
9008 +struct vc_mailbox {
9009 + struct device *dev; /* parent device */
9010 + void __iomem *status;
9011 + void __iomem *config;
9012 + void __iomem *read;
9013 + void __iomem *write;
9014 + uint32_t msg[MBOX_CHAN_COUNT];
9015 + struct semaphore sema[MBOX_CHAN_COUNT];
9016 + uint32_t magic;
9017 +};
9018 +
9019 +static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
9020 + uint32_t addr_mbox)
9021 +{
9022 + int i;
9023 +
9024 + mbox_out->dev = dev;
9025 + mbox_out->status = __io_address(addr_mbox + MAIL_STA);
9026 + mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
9027 + mbox_out->read = __io_address(addr_mbox + MAIL_RD);
9028 + /* Write to the other mailbox */
9029 + mbox_out->write =
9030 + __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
9031 + MAIL_WRT);
9032 +
9033 + for (i = 0; i < MBOX_CHAN_COUNT; i++) {
9034 + mbox_out->msg[i] = 0;
9035 + sema_init(&mbox_out->sema[i], 0);
9036 + }
9037 +
9038 + /* Enable the interrupt on data reception */
9039 + writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
9040 +
9041 + mbox_out->magic = MBOX_MAGIC;
9042 +}
9043 +
9044 +static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
9045 +{
9046 + int rc;
9047 +
9048 + if (mbox->magic != MBOX_MAGIC)
9049 + rc = -EINVAL;
9050 + else {
9051 + /* wait for the mailbox FIFO to have some space in it */
9052 + while (0 != (readl(mbox->status) & ARM_MS_FULL))
9053 + cpu_relax();
9054 +
9055 + writel(MBOX_MSG(chan, data28), mbox->write);
9056 + rc = 0;
9057 + }
9058 + return rc;
9059 +}
9060 +
9061 +static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
9062 +{
9063 + int rc;
9064 +
9065 + if (mbox->magic != MBOX_MAGIC)
9066 + rc = -EINVAL;
9067 + else {
9068 + down(&mbox->sema[chan]);
9069 + *data28 = MBOX_DATA28(mbox->msg[chan]);
9070 + mbox->msg[chan] = 0;
9071 + rc = 0;
9072 + }
9073 + return rc;
9074 +}
9075 +
9076 +static irqreturn_t mbox_irq(int irq, void *dev_id)
9077 +{
9078 + /* wait for the mailbox FIFO to have some data in it */
9079 + struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
9080 + int status = readl(mbox->status);
9081 + int ret = IRQ_NONE;
9082 +
9083 + while (!(status & ARM_MS_EMPTY)) {
9084 + uint32_t msg = readl(mbox->read);
9085 + int chan = MBOX_CHAN(msg);
9086 + if (chan < MBOX_CHAN_COUNT) {
9087 + if (mbox->msg[chan]) {
9088 + /* Overflow */
9089 + printk(KERN_ERR DRIVER_NAME
9090 + ": mbox chan %d overflow - drop %08x\n",
9091 + chan, msg);
9092 + } else {
9093 + mbox->msg[chan] = (msg | 0xf);
9094 + up(&mbox->sema[chan]);
9095 + }
9096 + } else {
9097 + printk(KERN_ERR DRIVER_NAME
9098 + ": invalid channel selector (msg %08x)\n", msg);
9099 + }
9100 + ret = IRQ_HANDLED;
9101 + status = readl(mbox->status);
9102 + }
9103 + return ret;
9104 +}
9105 +
9106 +static struct irqaction mbox_irqaction = {
9107 + .name = "ARM Mailbox IRQ",
9108 + .flags = IRQF_DISABLED | IRQF_IRQPOLL,
9109 + .handler = mbox_irq,
9110 +};
9111 +
9112 +/* ----------------------------------------------------------------------
9113 + * Mailbox Methods
9114 + * -------------------------------------------------------------------- */
9115 +
9116 +static struct device *mbox_dev; /* we assume there's only one! */
9117 +
9118 +static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
9119 +{
9120 + int rc;
9121 +
9122 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
9123 + device_lock(dev);
9124 + rc = mbox_write(mailbox, chan, data28);
9125 + device_unlock(dev);
9126 +
9127 + return rc;
9128 +}
9129 +
9130 +static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
9131 +{
9132 + int rc;
9133 +
9134 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
9135 + device_lock(dev);
9136 + rc = mbox_read(mailbox, chan, data28);
9137 + device_unlock(dev);
9138 +
9139 + return rc;
9140 +}
9141 +
9142 +extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
9143 +{
9144 + if (mbox_dev)
9145 + return dev_mbox_write(mbox_dev, chan, data28);
9146 + else
9147 + return -ENODEV;
9148 +}
9149 +EXPORT_SYMBOL_GPL(bcm_mailbox_write);
9150 +
9151 +extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
9152 +{
9153 + if (mbox_dev)
9154 + return dev_mbox_read(mbox_dev, chan, data28);
9155 + else
9156 + return -ENODEV;
9157 +}
9158 +EXPORT_SYMBOL_GPL(bcm_mailbox_read);
9159 +
9160 +static void dev_mbox_register(const char *dev_name, struct device *dev)
9161 +{
9162 + mbox_dev = dev;
9163 +}
9164 +
9165 +static int mbox_copy_from_user(void *dst, const void *src, int size)
9166 +{
9167 + if ( (uint32_t)src < TASK_SIZE)
9168 + {
9169 + return copy_from_user(dst, src, size);
9170 + }
9171 + else
9172 + {
9173 + memcpy( dst, src, size );
9174 + return 0;
9175 + }
9176 +}
9177 +
9178 +static int mbox_copy_to_user(void *dst, const void *src, int size)
9179 +{
9180 + if ( (uint32_t)dst < TASK_SIZE)
9181 + {
9182 + return copy_to_user(dst, src, size);
9183 + }
9184 + else
9185 + {
9186 + memcpy( dst, src, size );
9187 + return 0;
9188 + }
9189 +}
9190 +
9191 +static DEFINE_MUTEX(mailbox_lock);
9192 +extern int bcm_mailbox_property(void *data, int size)
9193 +{
9194 + uint32_t success;
9195 + dma_addr_t mem_bus; /* the memory address accessed from videocore */
9196 + void *mem_kern; /* the memory address accessed from driver */
9197 + int s = 0;
9198 +
9199 + mutex_lock(&mailbox_lock);
9200 + /* allocate some memory for the messages communicating with GPU */
9201 + mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
9202 + if (mem_kern) {
9203 + /* create the message */
9204 + mbox_copy_from_user(mem_kern, data, size);
9205 +
9206 + /* send the message */
9207 + wmb();
9208 + s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
9209 + if (s == 0) {
9210 + s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
9211 + }
9212 + if (s == 0) {
9213 + /* copy the response */
9214 + rmb();
9215 + mbox_copy_to_user(data, mem_kern, size);
9216 + }
9217 + dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
9218 + } else {
9219 + s = -ENOMEM;
9220 + }
9221 + if (s != 0)
9222 + printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
9223 +
9224 + mutex_unlock(&mailbox_lock);
9225 + return s;
9226 +}
9227 +EXPORT_SYMBOL_GPL(bcm_mailbox_property);
9228 +
9229 +/* ----------------------------------------------------------------------
9230 + * Platform Device for Mailbox
9231 + * -------------------------------------------------------------------- */
9232 +
9233 +/*
9234 + * Is the device open right now? Used to prevent
9235 + * concurent access into the same device
9236 + */
9237 +static int Device_Open = 0;
9238 +
9239 +/*
9240 + * This is called whenever a process attempts to open the device file
9241 + */
9242 +static int device_open(struct inode *inode, struct file *file)
9243 +{
9244 + /*
9245 + * We don't want to talk to two processes at the same time
9246 + */
9247 + if (Device_Open)
9248 + return -EBUSY;
9249 +
9250 + Device_Open++;
9251 + /*
9252 + * Initialize the message
9253 + */
9254 + try_module_get(THIS_MODULE);
9255 + return 0;
9256 +}
9257 +
9258 +static int device_release(struct inode *inode, struct file *file)
9259 +{
9260 + /*
9261 + * We're now ready for our next caller
9262 + */
9263 + Device_Open--;
9264 +
9265 + module_put(THIS_MODULE);
9266 + return 0;
9267 +}
9268 +
9269 +/*
9270 + * This function is called whenever a process tries to do an ioctl on our
9271 + * device file. We get two extra parameters (additional to the inode and file
9272 + * structures, which all device functions get): the number of the ioctl called
9273 + * and the parameter given to the ioctl function.
9274 + *
9275 + * If the ioctl is write or read/write (meaning output is returned to the
9276 + * calling process), the ioctl call returns the output of this function.
9277 + *
9278 + */
9279 +static long device_ioctl(struct file *file, /* see include/linux/fs.h */
9280 + unsigned int ioctl_num, /* number and param for ioctl */
9281 + unsigned long ioctl_param)
9282 +{
9283 + unsigned size;
9284 + /*
9285 + * Switch according to the ioctl called
9286 + */
9287 + switch (ioctl_num) {
9288 + case IOCTL_MBOX_PROPERTY:
9289 + /*
9290 + * Receive a pointer to a message (in user space) and set that
9291 + * to be the device's message. Get the parameter given to
9292 + * ioctl by the process.
9293 + */
9294 + mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
9295 + return bcm_mailbox_property((void *)ioctl_param, size);
9296 + break;
9297 + default:
9298 + printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
9299 + return -EINVAL;
9300 + }
9301 +
9302 + return 0;
9303 +}
9304 +
9305 +/* Module Declarations */
9306 +
9307 +/*
9308 + * This structure will hold the functions to be called
9309 + * when a process does something to the device we
9310 + * created. Since a pointer to this structure is kept in
9311 + * the devices table, it can't be local to
9312 + * init_module. NULL is for unimplemented functios.
9313 + */
9314 +struct file_operations fops = {
9315 + .unlocked_ioctl = device_ioctl,
9316 + .open = device_open,
9317 + .release = device_release, /* a.k.a. close */
9318 +};
9319 +
9320 +static int bcm_vcio_probe(struct platform_device *pdev)
9321 +{
9322 + int ret = 0;
9323 + struct vc_mailbox *mailbox;
9324 +
9325 + mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
9326 + if (NULL == mailbox) {
9327 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
9328 + "mailbox memory\n");
9329 + ret = -ENOMEM;
9330 + } else {
9331 + struct resource *res;
9332 +
9333 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
9334 + if (res == NULL) {
9335 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
9336 + "resource\n");
9337 + ret = -ENODEV;
9338 + kfree(mailbox);
9339 + } else {
9340 + /* should be based on the registers from res really */
9341 + mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
9342 +
9343 + platform_set_drvdata(pdev, mailbox);
9344 + dev_mbox_register(DRIVER_NAME, &pdev->dev);
9345 +
9346 + mbox_irqaction.dev_id = mailbox;
9347 + setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
9348 + printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
9349 + __io_address(ARM_0_MAIL0_RD));
9350 + }
9351 + }
9352 +
9353 + if (ret == 0) {
9354 + /*
9355 + * Register the character device
9356 + */
9357 + ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
9358 +
9359 + /*
9360 + * Negative values signify an error
9361 + */
9362 + if (ret < 0) {
9363 + printk(KERN_ERR DRIVER_NAME
9364 + "Failed registering the character device %d\n", ret);
9365 + return ret;
9366 + }
9367 + }
9368 + return ret;
9369 +}
9370 +
9371 +static int bcm_vcio_remove(struct platform_device *pdev)
9372 +{
9373 + struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
9374 +
9375 + platform_set_drvdata(pdev, NULL);
9376 + kfree(mailbox);
9377 +
9378 + return 0;
9379 +}
9380 +
9381 +static struct platform_driver bcm_mbox_driver = {
9382 + .probe = bcm_vcio_probe,
9383 + .remove = bcm_vcio_remove,
9384 +
9385 + .driver = {
9386 + .name = DRIVER_NAME,
9387 + .owner = THIS_MODULE,
9388 + },
9389 +};
9390 +
9391 +static int __init bcm_mbox_init(void)
9392 +{
9393 + int ret;
9394 +
9395 + printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
9396 +
9397 + ret = platform_driver_register(&bcm_mbox_driver);
9398 + if (ret != 0) {
9399 + printk(KERN_ERR DRIVER_NAME ": failed to register "
9400 + "on platform\n");
9401 + }
9402 +
9403 + return ret;
9404 +}
9405 +
9406 +static void __exit bcm_mbox_exit(void)
9407 +{
9408 + platform_driver_unregister(&bcm_mbox_driver);
9409 +}
9410 +
9411 +arch_initcall(bcm_mbox_init); /* Initialize early */
9412 +module_exit(bcm_mbox_exit);
9413 +
9414 +MODULE_AUTHOR("Gray Girling");
9415 +MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
9416 +MODULE_LICENSE("GPL");
9417 +MODULE_ALIAS("platform:bcm-mbox");
9418 diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
9419 index 22ac2a6..eec2825 100644
9420 --- a/arch/arm/mm/proc-v7.S
9421 +++ b/arch/arm/mm/proc-v7.S
9422 @@ -441,6 +441,7 @@ __v7_setup:
9423 orr r0, r0, r6 @ set them
9424 THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
9425 ret lr @ return to head.S:__ret
9426 + .space 256
9427 ENDPROC(__v7_setup)
9428
9429 .align 2
9430 diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
9431 index c9ddd87..bfc397c 100644
9432 --- a/arch/arm/tools/mach-types
9433 +++ b/arch/arm/tools/mach-types
9434 @@ -523,6 +523,7 @@ prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
9435 paz00 MACH_PAZ00 PAZ00 3128
9436 acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
9437 bcm2708 MACH_BCM2708 BCM2708 3138
9438 +bcm2709 MACH_BCM2709 BCM2709 3139
9439 ag5evm MACH_AG5EVM AG5EVM 3189
9440 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
9441 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
9442 diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
9443 index 0d2ca0d..77eb7a8 100644
9444 --- a/drivers/char/hw_random/Kconfig
9445 +++ b/drivers/char/hw_random/Kconfig
9446 @@ -322,7 +322,7 @@ config HW_RANDOM_TPM
9447
9448 config HW_RANDOM_BCM2708
9449 tristate "BCM2708 generic true random number generator support"
9450 - depends on HW_RANDOM && ARCH_BCM2708
9451 + depends on HW_RANDOM && (ARCH_BCM2708 || ARCH_BCM2709)
9452 ---help---
9453 This driver provides the kernel-side support for the BCM2708 hardware.
9454
9455 diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
9456 index 84b4c8b..8253434 100644
9457 --- a/drivers/clocksource/arm_arch_timer.c
9458 +++ b/drivers/clocksource/arm_arch_timer.c
9459 @@ -795,3 +795,39 @@ static void __init arch_timer_mem_init(struct device_node *np)
9460 }
9461 CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
9462 arch_timer_mem_init);
9463 +
9464 +int __init dc4_arch_timer_init(void)
9465 +{
9466 + if (arch_timers_present & ARCH_CP15_TIMER) {
9467 + pr_warn("arch_timer: multiple nodes in dt, skipping\n");
9468 + return -1;
9469 + }
9470 +
9471 + arch_timers_present |= ARCH_CP15_TIMER;
9472 +
9473 + /* Try to determine the frequency from the device tree or CNTFRQ */
9474 + arch_timer_rate = 19200000;
9475 +
9476 + arch_timer_ppi[PHYS_SECURE_PPI] = IRQ_ARM_LOCAL_CNTPSIRQ;
9477 + arch_timer_ppi[PHYS_NONSECURE_PPI] = IRQ_ARM_LOCAL_CNTPNSIRQ;
9478 + arch_timer_ppi[VIRT_PPI] = IRQ_ARM_LOCAL_CNTVIRQ;
9479 + arch_timer_ppi[HYP_PPI] = IRQ_ARM_LOCAL_CNTHPIRQ;
9480 +
9481 + /*
9482 + * If HYP mode is available, we know that the physical timer
9483 + * has been configured to be accessible from PL1. Use it, so
9484 + * that a guest can use the virtual timer instead.
9485 + *
9486 + * If no interrupt provided for virtual timer, we'll have to
9487 + * stick to the physical timer. It'd better be accessible...
9488 + */
9489 + if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
9490 + arch_timer_use_virtual = false;
9491 + }
9492 +
9493 + arch_timer_c3stop = 0;
9494 +
9495 + arch_timer_register();
9496 + arch_timer_common_init();
9497 + return 0;
9498 +}
9499 diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
9500 index c9b8eb5..5965795 100644
9501 --- a/drivers/dma/Kconfig
9502 +++ b/drivers/dma/Kconfig
9503 @@ -332,7 +332,7 @@ config DMA_BCM2835
9504
9505 config DMA_BCM2708
9506 tristate "BCM2708 DMA engine support"
9507 - depends on MACH_BCM2708
9508 + depends on MACH_BCM2708 || MACH_BCM2709
9509 select DMA_ENGINE
9510 select DMA_VIRTUAL_CHANNELS
9511
9512 diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
9513 index d30a986..d181d7f 100644
9514 --- a/drivers/i2c/busses/Kconfig
9515 +++ b/drivers/i2c/busses/Kconfig
9516 @@ -361,7 +361,7 @@ config I2C_AXXIA
9517
9518 config I2C_BCM2835
9519 tristate "Broadcom BCM2835 I2C controller"
9520 - depends on ARCH_BCM2835 || ARCH_BCM2708
9521 + depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709
9522 help
9523 If you say yes to this option, support will be included for the
9524 BCM2835 I2C controller.
9525 @@ -373,7 +373,7 @@ config I2C_BCM2835
9526
9527 config I2C_BCM2708
9528 tristate "BCM2708 BSC"
9529 - depends on MACH_BCM2708
9530 + depends on MACH_BCM2708 || MACH_BCM2709
9531 help
9532 Enabling this option will add BSC (Broadcom Serial Controller)
9533 support for the BCM2708. BSC is a Broadcom proprietary bus compatible
9534 diff --git a/drivers/media/platform/bcm2835/Kconfig b/drivers/media/platform/bcm2835/Kconfig
9535 index a8fd172..2cb1a68 100644
9536 --- a/drivers/media/platform/bcm2835/Kconfig
9537 +++ b/drivers/media/platform/bcm2835/Kconfig
9538 @@ -2,7 +2,7 @@
9539
9540 config VIDEO_BCM2835
9541 bool "Broadcom BCM2835 camera interface driver"
9542 - depends on VIDEO_V4L2 && ARCH_BCM2708
9543 + depends on VIDEO_V4L2 && (ARCH_BCM2708 || ARCH_BCM2709)
9544 ---help---
9545 Say Y here to enable camera host interface devices for
9546 Broadcom BCM2835 SoC. This operates over the VCHIQ interface
9547 diff --git a/drivers/misc/vc04_services/Kconfig b/drivers/misc/vc04_services/Kconfig
9548 index 2663933..b94e6cd 100644
9549 --- a/drivers/misc/vc04_services/Kconfig
9550 +++ b/drivers/misc/vc04_services/Kconfig
9551 @@ -1,6 +1,6 @@
9552 config BCM2708_VCHIQ
9553 tristate "Videocore VCHIQ"
9554 - depends on MACH_BCM2708
9555 + depends on MACH_BCM2708 || MACH_BCM2709
9556 default y
9557 help
9558 Kernel to VideoCore communication interface for the
9559 diff --git a/drivers/misc/vc04_services/Makefile b/drivers/misc/vc04_services/Makefile
9560 index 0c82520..8d038fe 100644
9561 --- a/drivers/misc/vc04_services/Makefile
9562 +++ b/drivers/misc/vc04_services/Makefile
9563 @@ -1,5 +1,3 @@
9564 -ifeq ($(CONFIG_MACH_BCM2708),y)
9565 -
9566 obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o
9567
9568 vchiq-objs := \
9569 @@ -14,4 +12,3 @@ vchiq-objs := \
9570
9571 ccflags-y += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000
9572
9573 -endif
9574 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
9575 index 977aeef..b049c15 100644
9576 --- a/drivers/mmc/host/Kconfig
9577 +++ b/drivers/mmc/host/Kconfig
9578 @@ -304,7 +304,7 @@ config MMC_SDHCI_ST
9579
9580 config MMC_BCM2835
9581 tristate "MMC support on BCM2835"
9582 - depends on MACH_BCM2708
9583 + depends on (MACH_BCM2708 || MACH_BCM2709)
9584 help
9585 This selects the MMC Interface on BCM2835.
9586
9587 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
9588 index a5238ab..ea70ef0 100644
9589 --- a/drivers/spi/Kconfig
9590 +++ b/drivers/spi/Kconfig
9591 @@ -77,7 +77,7 @@ config SPI_ATMEL
9592
9593 config SPI_BCM2835
9594 tristate "BCM2835 SPI controller"
9595 - depends on ARCH_BCM2835 || ARCH_BCM2708 || COMPILE_TEST
9596 + depends on ARCH_BCM2835 || ARCH_BCM2708 || ARCH_BCM2709 || COMPILE_TEST
9597 help
9598 This selects a driver for the Broadcom BCM2835 SPI master.
9599
9600 @@ -88,7 +88,7 @@ config SPI_BCM2835
9601
9602 config SPI_BCM2708
9603 tristate "BCM2708 SPI controller driver (SPI0)"
9604 - depends on MACH_BCM2708
9605 + depends on MACH_BCM2708 || MACH_BCM2709
9606 help
9607 This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This
9608 driver is not compatible with the "Universal SPI Master" or the SPI slave
9609 diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
9610 index ff56894..4bcc3b2 100644
9611 --- a/drivers/watchdog/Kconfig
9612 +++ b/drivers/watchdog/Kconfig
9613 @@ -454,7 +454,7 @@ config RETU_WATCHDOG
9614
9615 config BCM2708_WDT
9616 tristate "BCM2708 Watchdog"
9617 - depends on ARCH_BCM2708
9618 + depends on ARCH_BCM2708 || ARCH_BCM2709
9619 help
9620 Enables BCM2708 watchdog support.
9621
9622 diff --git a/sound/arm/Kconfig b/sound/arm/Kconfig
9623 index f7ceafd..ada7ba2 100644
9624 --- a/sound/arm/Kconfig
9625 +++ b/sound/arm/Kconfig
9626 @@ -41,7 +41,7 @@ config SND_PXA2XX_AC97
9627
9628 config SND_BCM2835
9629 tristate "BCM2835 ALSA driver"
9630 - depends on ARCH_BCM2708 && BCM2708_VCHIQ && SND
9631 + depends on (ARCH_BCM2708 || ARCH_BCM2709) && BCM2708_VCHIQ && SND
9632 select SND_PCM
9633 help
9634 Say Y or M if you want to support BCM2835 Alsa pcm card driver
9635 diff --git a/sound/soc/bcm/Kconfig b/sound/soc/bcm/Kconfig
9636 index a562ddf..40d27c1 100644
9637 --- a/sound/soc/bcm/Kconfig
9638 +++ b/sound/soc/bcm/Kconfig
9639 @@ -10,7 +10,7 @@ config SND_BCM2835_SOC_I2S
9640
9641 config SND_BCM2708_SOC_I2S
9642 tristate "SoC Audio support for the Broadcom BCM2708 I2S module"
9643 - depends on MACH_BCM2708
9644 + depends on MACH_BCM2708 || MACH_BCM2709
9645 select REGMAP_MMIO
9646 select SND_SOC_DMAENGINE_PCM
9647 select SND_SOC_GENERIC_DMAENGINE_PCM
9648 --
9649 1.8.3.2
9650
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