1 From 39a6ff9b1ecb74c734606429647a9d783c7504f1 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Fri, 20 Jun 2014 17:19:27 +0100
4 Subject: [PATCH 054/148] bcm2709: Simplify and strip down IRQ handler
7 arch/arm/include/asm/entry-macro-multi.S | 2 +
8 arch/arm/mach-bcm2709/include/mach/entry-macro.S | 173 +++++++++++------------
9 2 files changed, 87 insertions(+), 88 deletions(-)
11 --- a/arch/arm/include/asm/entry-macro-multi.S
12 +++ b/arch/arm/include/asm/entry-macro-multi.S
14 #include <asm/assembler.h>
16 +#ifndef CONFIG_ARCH_BCM2709
18 * Interrupt handling. Preserves r7, r8, r9
26 .macro arch_irq_handler, symbol_name
28 --- a/arch/arm/mach-bcm2709/include/mach/entry-macro.S
29 +++ b/arch/arm/mach-bcm2709/include/mach/entry-macro.S
31 #include <mach/hardware.h>
32 #include <mach/irqs.h>
36 + .macro arch_ret_to_user, tmp1, tmp2
39 - .macro get_irqnr_preamble, base, tmp
40 - ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
43 - .macro arch_ret_to_user, tmp1, tmp2
46 - .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
47 - /* get core number */
48 - mrc p15, 0, \tmp, c0, c0, 5
49 - ubfx \tmp, \tmp, #0, #2
51 - /* get core's local interrupt controller */
52 - ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
53 - add \irqstat, \irqstat, \tmp, lsl #2
54 - ldr \tmp, [\irqstat]
55 - /* ignore gpu interrupt */
57 - /* ignore mailbox interrupts */
61 - @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
62 - @ N.B. CLZ is an ARM5 instruction.
63 - mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
64 - sub \irqstat, \tmp, #1
65 - eor \irqstat, \irqstat, \tmp
70 - /* get core number */
71 - mrc p15, 0, \tmp, c0, c0, 5
72 - ubfx \tmp, \tmp, #0, #2
81 - /* get masked status */
82 - ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
83 - mov \irqnr, #(ARM_IRQ0_BASE + 31)
84 - and \tmp, \irqstat, #0x300 @ save bits 8 and 9
85 - /* clear bits 8 and 9, and test */
86 - bics \irqstat, \irqstat, #0x300
90 - ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
91 - movne \irqnr, #(ARM_IRQ1_BASE + 31)
92 - @ Mask out the interrupts also present in PEND0 - see SW-5809
93 - bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
94 - bicne \irqstat, #((1<<18) | (1<<19))
98 - ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
99 - movne \irqnr, #(ARM_IRQ2_BASE + 31)
100 - @ Mask out the interrupts also present in PEND0 - see SW-5809
101 - bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
102 - bicne \irqstat, #((1<<30))
104 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
106 + /* get core number */
107 + mrc p15, 0, \base, c0, c0, 5
108 + ubfx \base, \base, #0, #2
110 + /* get core's local interrupt controller */
111 + ldr \irqstat, = __io_address(ARM_LOCAL_IRQ_PENDING0) @ local interrupt source
112 + add \irqstat, \irqstat, \base, lsl #2
113 + ldr \tmp, [\irqstat]
115 + /* test for mailbox0 (IPI) interrupt */
119 + /* get core's mailbox interrupt control */
120 + ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
121 + add \irqstat, \irqstat, \base, lsl #4
122 + ldr \tmp, [\irqstat]
124 + rsb \irqnr, \tmp, #31
127 + str \tmp, [\irqstat] @ clear interrupt source
134 + /* check gpu interrupt */
138 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
139 + /* get masked status */
140 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
141 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
142 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
143 + /* clear bits 8 and 9, and test */
144 + bics \irqstat, \irqstat, #0x300
148 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
149 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
150 + @ Mask out the interrupts also present in PEND0 - see SW-5809
151 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
152 + bicne \irqstat, #((1<<18) | (1<<19))
156 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
157 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
158 + @ Mask out the interrupts also present in PEND0 - see SW-5809
159 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
160 + bicne \irqstat, #((1<<30))
163 - @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
164 - @ N.B. CLZ is an ARM5 instruction.
165 - sub \tmp, \irqstat, #1
166 - eor \irqstat, \irqstat, \tmp
169 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
170 + sub \tmp, \irqstat, #1
171 + eor \irqstat, \irqstat, \tmp
179 + /* handle local (e.g. timer) interrupts */
180 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
181 + mov \irqnr, #(ARM_IRQ_LOCAL_BASE + 31)
182 + sub \irqstat, \tmp, #1
183 + eor \irqstat, \irqstat, \tmp
189 + @ routine called with r0 = irq number, r1 = struct pt_regs *
194 1020: @ EQ will be set if no irqs pending
199 - .macro test_for_ipi, irqnr, irqstat, base, tmp
200 - /* get core number */
201 - mrc p15, 0, \tmp, c0, c0, 5
202 - ubfx \tmp, \tmp, #0, #2
203 - /* get core's mailbox interrupt control */
204 - ldr \irqstat, = __io_address(ARM_LOCAL_MAILBOX0_CLR0) @ mbox_clr
205 - add \irqstat, \irqstat, \tmp, lsl #4
206 - ldr \tmp, [\irqstat]
210 - rsb \irqnr, \tmp, #31
213 - str \tmp, [\irqstat] @ clear interrupt source
215 -1030: @ EQ will be set if no irqs pending
218 + * Interrupt handling. Preserves r7, r8, r9
220 + .macro arch_irq_handler_default
221 +1: get_irqnr_and_base r0, r2, r6, lr