1 From f844ea32cba0c4030594a0f590725477a5751f32 Mon Sep 17 00:00:00 2001
2 From: Annaliese McDermond <nh6z@nh6z.net>
3 Date: Thu, 21 Mar 2019 17:58:49 -0700
4 Subject: [PATCH] ASoC: tlv320aic32x4: Control clock gating with CCF
6 commit d25970b5fd51e9fcf0afbe190908ea4049454da4 upstream.
8 Control the clock gating to the various clock components to use
9 the CCF. This allows us to prepare_enalbe only 3 clocks and the
10 relationships assigned to them will cause upstream clockss to
11 enable automatically. Additionally we can do this in a single
14 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
15 Signed-off-by: Mark Brown <broonie@kernel.org>
17 sound/soc/codecs/tlv320aic32x4.c | 67 +++++++-------------------------
18 1 file changed, 13 insertions(+), 54 deletions(-)
20 --- a/sound/soc/codecs/tlv320aic32x4.c
21 +++ b/sound/soc/codecs/tlv320aic32x4.c
22 @@ -836,41 +836,25 @@ static int aic32x4_mute(struct snd_soc_d
23 static int aic32x4_set_bias_level(struct snd_soc_component *component,
24 enum snd_soc_bias_level level)
26 - struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
29 + struct clk_bulk_data clocks[] = {
35 + ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
41 - /* Switch on master clock */
42 - ret = clk_prepare_enable(aic32x4->mclk);
43 + ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
45 - dev_err(component->dev, "Failed to enable master clock\n");
46 + dev_err(component->dev, "Failed to enable clocks\n");
51 - snd_soc_component_update_bits(component, AIC32X4_PLLPR,
52 - AIC32X4_PLLEN, AIC32X4_PLLEN);
54 - /* Switch on NDAC Divider */
55 - snd_soc_component_update_bits(component, AIC32X4_NDAC,
56 - AIC32X4_NDACEN, AIC32X4_NDACEN);
58 - /* Switch on MDAC Divider */
59 - snd_soc_component_update_bits(component, AIC32X4_MDAC,
60 - AIC32X4_MDACEN, AIC32X4_MDACEN);
62 - /* Switch on NADC Divider */
63 - snd_soc_component_update_bits(component, AIC32X4_NADC,
64 - AIC32X4_NADCEN, AIC32X4_NADCEN);
66 - /* Switch on MADC Divider */
67 - snd_soc_component_update_bits(component, AIC32X4_MADC,
68 - AIC32X4_MADCEN, AIC32X4_MADCEN);
70 - /* Switch on BCLK_N Divider */
71 - snd_soc_component_update_bits(component, AIC32X4_BCLKN,
72 - AIC32X4_BCLKEN, AIC32X4_BCLKEN);
74 case SND_SOC_BIAS_PREPARE:
76 @@ -879,32 +863,7 @@ static int aic32x4_set_bias_level(struct
77 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
80 - /* Switch off BCLK_N Divider */
81 - snd_soc_component_update_bits(component, AIC32X4_BCLKN,
84 - /* Switch off MADC Divider */
85 - snd_soc_component_update_bits(component, AIC32X4_MADC,
88 - /* Switch off NADC Divider */
89 - snd_soc_component_update_bits(component, AIC32X4_NADC,
92 - /* Switch off MDAC Divider */
93 - snd_soc_component_update_bits(component, AIC32X4_MDAC,
96 - /* Switch off NDAC Divider */
97 - snd_soc_component_update_bits(component, AIC32X4_NDAC,
100 - /* Switch off PLL */
101 - snd_soc_component_update_bits(component, AIC32X4_PLLPR,
104 - /* Switch off master clock */
105 - clk_disable_unprepare(aic32x4->mclk);
106 + clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
108 case SND_SOC_BIAS_OFF: