1 From 4c19d1b2713fd0452edfc479cea4628229048994 Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Tue, 8 Dec 2015 14:00:43 -0800
4 Subject: [PATCH] drm/vc4: A few more non-functional changes to sync to
7 At this point all that's left is the force-enable of HDMI connector,
8 and using direct firmware calls to turn on V3D instead of the generic
11 Signed-off-by: Eric Anholt <eric@anholt.net>
13 drivers/gpu/drm/vc4/vc4_v3d.c | 2 +-
14 include/uapi/drm/vc4_drm.h | 182 +++++++++++++++++++++---------------------
15 2 files changed, 92 insertions(+), 92 deletions(-)
17 --- a/drivers/gpu/drm/vc4/vc4_v3d.c
18 +++ b/drivers/gpu/drm/vc4/vc4_v3d.c
19 @@ -109,7 +109,7 @@ static const struct {
21 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused)
23 - struct drm_info_node *node = (struct drm_info_node *) m->private;
24 + struct drm_info_node *node = (struct drm_info_node *)m->private;
25 struct drm_device *dev = node->minor->dev;
26 struct vc4_dev *vc4 = to_vc4_dev(dev);
28 --- a/include/uapi/drm/vc4_drm.h
29 +++ b/include/uapi/drm/vc4_drm.h
31 #ifndef _UAPI_VC4_DRM_H_
32 #define _UAPI_VC4_DRM_H_
37 #define DRM_VC4_SUBMIT_CL 0x00
38 #define DRM_VC4_WAIT_SEQNO 0x01
40 #define DRM_VC4_CREATE_SHADER_BO 0x05
41 #define DRM_VC4_GET_HANG_STATE 0x06
43 -#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
44 -#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
45 -#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
46 -#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
47 -#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
48 -#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
49 -#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
50 +#define DRM_IOCTL_VC4_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
51 +#define DRM_IOCTL_VC4_WAIT_SEQNO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
52 +#define DRM_IOCTL_VC4_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
53 +#define DRM_IOCTL_VC4_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
54 +#define DRM_IOCTL_VC4_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
55 +#define DRM_IOCTL_VC4_CREATE_SHADER_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
56 +#define DRM_IOCTL_VC4_GET_HANG_STATE DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
58 struct drm_vc4_submit_rcl_surface {
59 - uint32_t hindex; /* Handle index, or ~0 if not present. */
60 - uint32_t offset; /* Offset to start of buffer. */
61 + __u32 hindex; /* Handle index, or ~0 if not present. */
62 + __u32 offset; /* Offset to start of buffer. */
64 - * Bits for either render config (color_write) or load/store packet.
65 - * Bits should all be 0 for MSAA load/stores.
66 + * Bits for either render config (color_write) or load/store packet.
67 + * Bits should all be 0 for MSAA load/stores.
72 #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES (1 << 0)
78 @@ -76,7 +76,7 @@ struct drm_vc4_submit_cl {
79 * then writes out the state updates and draw calls necessary per tile
80 * to the tile allocation BO.
85 /* Pointer to the shader records.
87 @@ -85,16 +85,16 @@ struct drm_vc4_submit_cl {
88 * reference to the shader record has enough information to determine
89 * how many pointers are necessary (fixed number for shaders/uniforms,
90 * and an attribute count), so those BO indices into bo_handles are
91 - * just stored as uint32_ts before each shader record passed in.
92 + * just stored as __u32s before each shader record passed in.
94 - uint64_t shader_rec;
97 /* Pointer to uniform data and texture handles for the textures
98 * referenced by the shader.
100 * For each shader state record, there is a set of uniform data in the
101 * order referenced by the record (FS, VS, then CS). Each set of
102 - * uniform data has a uint32_t index into bo_handles per texture
103 + * uniform data has a __u32 index into bo_handles per texture
104 * sample operation, in the order the QPU_W_TMUn_S writes appear in
105 * the program. Following the texture BO handle indices is the actual
107 @@ -103,52 +103,52 @@ struct drm_vc4_submit_cl {
108 * because the kernel has to determine the sizes anyway during shader
112 - uint64_t bo_handles;
116 /* Size in bytes of the binner command list. */
117 - uint32_t bin_cl_size;
119 /* Size in bytes of the set of shader records. */
120 - uint32_t shader_rec_size;
121 + __u32 shader_rec_size;
122 /* Number of shader records.
124 * This could just be computed from the contents of shader_records and
125 * the address bits of references to them from the bin CL, but it
126 * keeps the kernel from having to resize some allocations it makes.
128 - uint32_t shader_rec_count;
129 + __u32 shader_rec_count;
130 /* Size in bytes of the uniform state. */
131 - uint32_t uniforms_size;
132 + __u32 uniforms_size;
134 /* Number of BO handles passed in (size is that times 4). */
135 - uint32_t bo_handle_count;
136 + __u32 bo_handle_count;
141 - uint8_t min_x_tile;
142 - uint8_t min_y_tile;
143 - uint8_t max_x_tile;
144 - uint8_t max_y_tile;
151 struct drm_vc4_submit_rcl_surface color_read;
152 struct drm_vc4_submit_rcl_surface color_write;
153 struct drm_vc4_submit_rcl_surface zs_read;
154 struct drm_vc4_submit_rcl_surface zs_write;
155 struct drm_vc4_submit_rcl_surface msaa_color_write;
156 struct drm_vc4_submit_rcl_surface msaa_zs_write;
157 - uint32_t clear_color[2];
160 + __u32 clear_color[2];
167 #define VC4_SUBMIT_CL_USE_CLEAR_COLOR (1 << 0)
171 /* Returned value of the seqno of this render job (for the
179 @@ -159,8 +159,8 @@ struct drm_vc4_submit_cl {
180 * block, just return the status."
182 struct drm_vc4_wait_seqno {
184 - uint64_t timeout_ns;
190 @@ -172,9 +172,9 @@ struct drm_vc4_wait_seqno {
193 struct drm_vc4_wait_bo {
196 - uint64_t timeout_ns;
203 @@ -184,11 +184,30 @@ struct drm_vc4_wait_bo {
204 * used in a future extension.
206 struct drm_vc4_create_bo {
211 /** Returned GEM handle for the BO. */
219 + * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
221 + * This doesn't actually perform an mmap. Instead, it returns the
222 + * offset you need to use in an mmap on the DRM device node. This
223 + * means that tools like valgrind end up knowing about the mapped
226 + * There are currently no values for the flags argument, but it may be
227 + * used in a future extension.
229 +struct drm_vc4_mmap_bo {
230 + /** Handle for the object being mapped. */
233 + /** offset into the drm node to use for subsequent mmap call. */
238 @@ -201,43 +220,24 @@ struct drm_vc4_create_bo {
240 struct drm_vc4_create_shader_bo {
241 /* Size of the data argument. */
244 /* Flags, currently must be 0. */
248 /* Pointer to the data. */
252 /** Returned GEM handle for the BO. */
255 /* Pad, must be 0. */
260 - * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
262 - * This doesn't actually perform an mmap. Instead, it returns the
263 - * offset you need to use in an mmap on the DRM device node. This
264 - * means that tools like valgrind end up knowing about the mapped
267 - * There are currently no values for the flags argument, but it may be
268 - * used in a future extension.
270 -struct drm_vc4_mmap_bo {
271 - /** Handle for the object being mapped. */
274 - /** offset into the drm node to use for subsequent mmap call. */
279 struct drm_vc4_get_hang_state_bo {
291 @@ -246,34 +246,34 @@ struct drm_vc4_get_hang_state_bo {
293 struct drm_vc4_get_hang_state {
294 /** Pointer to array of struct drm_vc4_get_hang_state_bo. */
298 * On input, the size of the bo array. Output is the number
299 * of bos to be returned.
304 - uint32_t start_bin, start_render;
305 + __u32 start_bin, start_render;
307 - uint32_t ct0ca, ct0ea;
308 - uint32_t ct1ca, ct1ea;
309 - uint32_t ct0cs, ct1cs;
310 - uint32_t ct0ra0, ct1ra0;
312 - uint32_t bpca, bpcs;
313 - uint32_t bpoa, bpos;
323 + __u32 ct0ca, ct0ea;
324 + __u32 ct1ca, ct1ea;
325 + __u32 ct0cs, ct1cs;
326 + __u32 ct0ra0, ct1ra0;
340 /* Pad that we may save more registers into in the future. */
345 #endif /* _UAPI_VC4_DRM_H_ */